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1. 发明授权

US06449839B1 Electrical circuit board and a method for making the same 失效
标题翻译：电路板及其制造方法
公开(公告)号：US06449839B1
公开(公告)日：2002-09-17
申请号：US09655986
申请日：2000-09-06
申请人： Andrew Z. Glovatsky , Thomas Krautheim , Robert E. Belke, Jr. , Vivek Amir Jairazbhoy , Cuong V. Pham
发明人： Andrew Z. Glovatsky , Thomas Krautheim , Robert E. Belke, Jr. , Vivek Amir Jairazbhoy , Cuong V. Pham
IPC分类号： H05K302
CPC分类号： H05K3/4084 , H05K1/056 , H05K3/062 , H05K3/4092 , H05K3/44 , H05K3/445 , H05K2201/0305 , H05K2201/0361 , H05K2201/0379 , H05K2201/0397 , H05K2201/09554 , H05K2203/0195 , H05K2203/063 , Y10T29/49128 , Y10T29/49144 , Y10T29/49156
摘要： A method for forming connections within a multi-layer electronic circuit board 10. In one non-limiting embodiment, the method includes selectively forming air bridges over portions of the circuit board 10 and selectively collapsing the air bridges with a metallurgical bonding tool, effective to interconnect layers of the circuit board 10.
摘要翻译：一种用于在多层电子电路板10内形成连接的方法。在一个非限制性实施例中，该方法包括在电路板10的部分上选择性地形成空气桥，并用冶金接合工具选择性地折叠气桥，电路板10的互连层。

2. 发明授权

US06752015B2 Fluid flow device having reduced fluid ingress 失效
标题翻译：具有减少的流体入口的流体流动装置
公开(公告)号：US06752015B2
公开(公告)日：2004-06-22
申请号：US10253190
申请日：2002-09-24
申请人： David J. Thompson , Robert E. Belke, Jr. , Edward P. McLeskey
发明人： David J. Thompson , Robert E. Belke, Jr. , Edward P. McLeskey
IPC分类号： G01F168
CPC分类号： F02D41/18 , F02D41/3005 , F02D2400/18 , G01F1/6845
摘要： The present invention involves a device for detecting a condition of a flowing fluid within a vehicle having reduced sulfur ingress. The device includes a base plate having a receiving surface and a circumferential edge and a printed circuit board disposed on the receiving surface of the base plate. The device further includes a housing having peripheral side walls attaching to the receiving surface adjacent the circumferential edge to define a peripheral interface enclosing the printed circuit board within the housing. The device further includes an adhesive material disposed at the interface to adhere the housing to the base plate. The adhesive material has a predetermined thermal expansion coefficient and a predetermined elastic modulus to reduce fluid ingress through the interface and to accommodate thermal expansions of the base plate and the housing.
摘要翻译：本发明涉及一种用于检测具有降低的硫进入的车辆内的流动流体的状况的装置。该装置包括具有接收表面和周缘的基板和设置在基板的接收表面上的印刷电路板。该装置还包括壳体，该壳体具有附接到邻近周缘的接收表面的外围侧壁，以限定围绕该外壳内的印刷电路板的周边接口。该装置还包括设置在界面处以将壳体附接到基板的粘合材料。粘合剂材料具有预定的热膨胀系数和预定的弹性模量，以减少通过界面的流体进入并适应底板和壳体的热膨胀。

3. 发明授权

US4876120A Tailorable multi-layer printed wiring boards of controlled coefficient of thermal expansion 失效
标题翻译：可控多层印刷线路板，具有受控的热膨胀系数
公开(公告)号：US4876120A
公开(公告)日：1989-10-24
申请号：US40981
申请日：1987-04-21
申请人： Robert E. Belke , Louis Zakraysek , Walter O. Pillar
发明人： Robert E. Belke , Louis Zakraysek , Walter O. Pillar
IPC分类号： B32B27/06 , C09K19/38 , H05K1/03 , H05K3/46
CPC分类号： B32B27/06 , C09K19/3823 , H05K1/0346 , H05K1/0366 , H05K1/036 , H05K2201/0141 , H05K2201/0145 , H05K2201/0278 , H05K2201/0293 , H05K2201/068 , H05K3/4611 , H05K3/4626 , Y10S428/901 , Y10T428/1077 , Y10T428/2481 , Y10T428/24893 , Y10T428/24917 , Y10T428/31678 , Y10T428/31681 , Y10T428/31721
摘要： Disclosed are improved laminates useful in the manufacture of multi-layer printed wiring boards (MLPWB) and laminates. Such improved composites contain at least one layer which is formed from a liquid crystal polymer selected from the group consisting of poly(para-phenylene benzobisthiazole), poly(paraphenylene benzobisoxazole), poly(2,5-benzothiazole), poly(2,5-benzoxazole), and mixtures thereof. The presently preferred liquid crystal polymer comprises poly(para-phenylene benzobisthiazole). The negative coefficient of thermal expansion and high modulus of elasticity of the liquid crystal polymers enable a laminate and MLPWB to be manufactured therefrom having a tailored coefficient of thermal expansion, broadly ranging from about 0 to 15 ppm/.degree. C. MLPWBs constructed of polymeric core layers also are possible utilizing the preferred liquid crystal polymers of the present invention.
摘要翻译：公开了可用于制造多层印刷线路板（MLPWB）和层压板的改进的层压板。这种改进的复合材料包含至少一层，其由选自聚（对亚苯基苯并噻唑），聚（对苯撑苯并异恶唑），聚（2,5-苯并噻唑），聚（2,5）苯并恶唑）及其混合物。目前优选的液晶聚合物包括聚（对亚苯基苯并噻唑）。液晶聚合物的负膨胀系数和高弹性模量使得能够制造层压板和MLPWB，其具有大致为约0至15ppm /℃的约定热膨胀系数。由聚合物芯构成的MLPWB 利用本发明的优选液晶聚合物也可以使用层。

4. 发明授权

US06977337B1 Electronic assembly packaging 失效
标题翻译：电子组装包装
公开(公告)号：US06977337B1
公开(公告)日：2005-12-20
申请号：US10869729
申请日：2004-06-16
申请人： Anthony Nicolo Satullo , Robert E. Belke , Hong Zhou , Diane M. Jett , Bertrand R. Mohr , John Trublowski , Michael S. Schulke , Adam W. Schubring
发明人： Anthony Nicolo Satullo , Robert E. Belke , Hong Zhou , Diane M. Jett , Bertrand R. Mohr , John Trublowski , Michael S. Schulke , Adam W. Schubring
IPC分类号： H01J5/00 , H01L23/28 , H05K5/04 , H05K7/20 , H05K9/00
CPC分类号： H05K7/20436 , H05K9/0015
摘要： The present invention provides an assembly for protecting automotive electronics. The assembly includes a circuit board, a cover, and a metal housing. The metal housing is disposed over and around the circuit board. The cover and metal housing are crimped together to create a seal that protects the circuit board inside the metal housing and attaches the cover to the metal housing.
摘要翻译：本发明提供一种用于保护汽车电子的组件。组件包括电路板，盖和金属外壳。金属外壳设置在电路板的上方和周围。盖和金属壳体被压接在一起以形成密封件，其保护金属壳体内部的电路板并将盖子附接到金属壳体。

5. 发明授权

US06613239B2 Method for making an electrical circuit board 失效
公开(公告)号：US06613239B2
公开(公告)日：2003-09-02
申请号：US09836644
申请日：2001-04-17
申请人： Andrew Z. Glovatsky , Robert E. Belke , Delin Li , Lakhi N. Goenka , Mohan R. Paruchuri , Marc A. Straub , Richard K. McMillan , Ram S. Raghava , Thomas B. Krautheim , Michael A. Howey , Vivek A. Jairazbhoy
发明人： Andrew Z. Glovatsky , Robert E. Belke , Delin Li , Lakhi N. Goenka , Mohan R. Paruchuri , Marc A. Straub , Richard K. McMillan , Ram S. Raghava , Thomas B. Krautheim , Michael A. Howey , Vivek A. Jairazbhoy
IPC分类号： B44C122
CPC分类号： H05K3/4641 , H05K3/062 , H05K3/4038 , H05K3/4623 , H05K2201/0305 , H05K2201/0361 , H05K2201/0397 , H05K2201/09554 , H05K2201/09881 , H05K2203/0733 , H05K2203/1184 , Y10T29/49155
摘要： A method 10 for making multi-layer electronic circuit boards having metallized apertures 34, 36 which may be selectively and electrically grounded or isolated from an electrical ground plane.

6. 发明授权

US5738797A Three-dimensional multi-layer circuit structure and method for forming the same 失效
标题翻译：三维多层电路结构及其形成方法
公开(公告)号：US5738797A
公开(公告)日：1998-04-14
申请号：US649377
申请日：1996-05-17
申请人： Robert E. Belke, Jr. , Michael G. Todd , Andrew Z. Glovatsky , Alice D. Zitzmann
发明人： Robert E. Belke, Jr. , Michael G. Todd , Andrew Z. Glovatsky , Alice D. Zitzmann
IPC分类号： C23F1/02 , H05K3/00 , H05K3/06 , H05K3/20 , H05K3/46 , B44C1/22 , C23F1/00
CPC分类号： H05K3/4685 , C23F1/02 , H05K3/062 , H05K3/205 , H05K2201/0361 , H05K2201/0394 , H05K2201/09018 , H05K2201/09118 , H05K2203/0152 , H05K2203/0369 , H05K2203/0376 , H05K3/0014
摘要： A three dimensional multi-layer circuit structure is formed by partially etching a foil having a coating. A pre-circuit is formed by providing a metal foil, applying a photodefinable photoresist to each side of the metal foil, selectively exposing and developing the photoresist leaving exposed areas and unexposed areas and, plating the unexposed areas with a second metal. The pre-circuit is placed in an etching solution and removed after the etching solution partially etches the metal foil to undercut the second metal. The partially etched pre-circuit is then bent into a predetermined shape. The partially etched pre-circuit is then inserted into a mold cavity so that at least one surface of the circuit structure is adjacent to the mold. The mold is filled with a polymer resin so that the polymer resin encapsulates at least a portion of the partially etched pre-circuit and substantially fills the undercut. The molded circuit structure is then removed from the mold and the metallic foil is further etched to complete the forming of the circuit.
摘要翻译：通过部分蚀刻具有涂层的箔形成三维多层电路结构。通过提供金属箔，在金属箔的每一侧上施加可光限定的光致抗蚀剂，选择性地暴露和显影光致抗蚀剂以形成暴露区域和未曝光区域，以及用第二金属镀覆未曝光区域来形成预制电路。将预电路放置在蚀刻溶液中，并且在蚀刻溶液部分蚀刻金属箔以切割第二金属之后移除。然后将部分蚀刻的预循环弯曲成预定的形状。然后将部分蚀刻的预制电路插入模腔中，使得电路结构的至少一个表面与模具相邻。模具填充有聚合物树脂，使得聚合物树脂封装部分蚀刻的预循环的至少一部分并且基本上填充底切。然后将模制电路结构从模具中取出，并且金属箔被进一步蚀刻以完成电路的形成。

7. 发明授权

US5579573A Method for fabricating an undercoated chip electrically interconnected to a substrate 失效
标题翻译：制造与基片电连接的底涂芯片的方法
公开(公告)号：US5579573A
公开(公告)日：1996-12-03
申请号：US320812
申请日：1994-10-11
申请人： Jay D. Baker , Cuong V. Pham , Robert E. Belke, Jr.
发明人： Jay D. Baker , Cuong V. Pham , Robert E. Belke, Jr.
IPC分类号： H01L21/56 , H05K3/34 , H01L21/50 , H05K3/38
CPC分类号： H01L24/29 , H01L21/563 , H01L24/32 , H01L2224/1319 , H01L2224/16225 , H01L2224/274 , H01L2224/32225 , H01L2224/73104 , H01L2224/73203 , H01L2224/73204 , H01L2224/83191 , H01L2224/83856 , H01L2924/01005 , H01L2924/01006 , H01L2924/01047 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , Y10T29/49144 , Y10T29/49146
摘要： Method for fabricating an undercoated chip electrically interconnected to a substrate. The method includes the initial step of depositing a predetermined quantity of a liquid undercoat material onto the chip or the substrate. The method continues with the step of interconnecting the chip to the substrate so as to form an electrical interconnection bond therebetween. Finally, the method concludes with the step of heating, reflowing and curing the undercoat material during or after the step of electrically interconnecting the chip to the substrate.
摘要翻译： `制造与基片电连接的底涂芯片的方法。该方法包括将预定量的液体底涂层材料沉积到芯片或基底上的初始步骤。该方法继续将芯片与衬底互连以在其间形成电互连结的步骤。最后，该方法的结论是在将芯片与衬底电互连的步骤期间或之后加热，回流和固化底涂层材料的步骤。

8. 发明授权

US4806704A Metal matrix composite and structure using metal matrix composites for electronic applications 失效
标题翻译：金属基复合材料和结构使用金属基复合材料进行电子应用
公开(公告)号：US4806704A
公开(公告)日：1989-02-21
申请号：US59030
申请日：1987-06-08
申请人： Robert E. Belke, Jr. , George F. Trojanowski , Louis Zakraysek
发明人： Robert E. Belke, Jr. , George F. Trojanowski , Louis Zakraysek
IPC分类号： H01L23/06 , H01L23/10 , H01L23/14
CPC分类号： H01L23/06 , H01L23/10 , H01L23/142 , H01L2224/48091 , H01L2224/48472 , H01L24/48 , H01L2924/00014 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/16195 , H01L2924/163
摘要： The invention relates to a metal matrix composite used to support and/or enclose discrete electronic semiconductor devices, monolithic integrated circuits, hybrid circuits, and multi-layer printed wiring boards. The matrices herein disclosed employ aluminum as the matrix with Beta Eucryptite as the additive in a volume percent of up to 60. The preferred range of from 55 to 45 percent by volume of the additive has a coefficient of thermal expansion matching the common semiconductor materials and common ceramics used for electronic enclosures. The composite uses low cost materials, and due to the affinity of the additive to aluminum is easily prepared. The resulting structures have good thermal conductivity and low weight.
摘要翻译：本发明涉及用于支撑和/或封闭分立电子半导体器件，单片集成电路，混合电路和多层印刷线路板的金属基质复合材料。本文公开的基体使用铝作为基质，其中β铕基合金作为添加剂，体积百分比高达60.体积百分比为55至45％的添加剂的优选范围具有与常见的半导体材料相匹配的热膨胀系数，普通陶瓷用于电子外壳。该复合材料使用低成本材料，并且由于添加剂对铝的亲和性容易制备。所得结构具有良好的导热性和低重量。

9. 发明授权

US4679122A Metal core printed circuit board 失效
标题翻译：金属芯印刷电路板
公开(公告)号：US4679122A
公开(公告)日：1987-07-07
申请号：US886751
申请日：1986-07-11
申请人： Robert E. Belke, Jr. , Raymond A. Shirk , Hsiu H. Lin , Louis Zakraysek
发明人： Robert E. Belke, Jr. , Raymond A. Shirk , Hsiu H. Lin , Louis Zakraysek
IPC分类号： H05K1/03 , H05K1/05 , H05K3/44 , H05K3/46
CPC分类号： H05K1/056 , H05K1/0346 , H05K2201/0129 , H05K2201/0355 , H05K3/445 , H05K3/4644
摘要： A novel metal core printed circuit board and a method of making it are described. The circuit board comprises a metal substrate, a patternable metal foil, and an insulating layer of thermoplastic resin whose glass transition temperature is exceeded during assembly under pressure to bond the resin to the metal substrate and to the foil by high temperature wetting. The circuit board also provides holes whose interior is lined with a resin united fusing to the resin in the insulating layer by high temperature wetting accompanied by pressure. The thermoplastic resin is a polyetherimide engineering plastic. The layers of the printed circuit board described above, including any additional layers of insulating resin and foil, may be bonded in a single step in a laminating press. The finished circuit board may be a structural component of a chassis, has good heat conductivity, good high voltage performance, is practical for high frequency transmission paths, is tolerant of the high temperature necessary for soldering, and has a high continuous service temperature.
摘要翻译：描述了一种新颖的金属芯印刷电路板及其制造方法。电路板包括金属基板，可图案化的金属箔和热塑性树脂的绝缘层，其在压力下组装时玻璃化转变温度被超过，以通过高温润湿将树脂粘合到金属基底和箔上。电路板还提供孔，其内部衬有树脂，通过伴随压力的高温润湿将绝缘层中的树脂熔合在一起。热塑性树脂是聚醚酰亚胺工程塑料。上述印刷电路板的层，包括任何额外的绝缘树脂和箔层可以在层压压机中以单一步骤结合。完成的电路板可以是底盘的结构部件，具有良好的导热性，良好的高电压性能，对于高频传输路径是实用的，耐受焊接所需的高温，并且具有高的连续工作温度。

10. 发明授权

US4466874A Method of electroding a poly(vinylidene fluoride) solid 失效
标题翻译：电熔聚（偏二氟乙烯）固体的方法
公开(公告)号：US4466874A
公开(公告)日：1984-08-21
申请号：US537060
申请日：1983-09-29
申请人： Robert E. Belke, Jr. , Richard J. Hill , Raymond A. Shirk , David P. Smith
发明人： Robert E. Belke, Jr. , Richard J. Hill , Raymond A. Shirk , David P. Smith
IPC分类号： C23C14/02 , C23C14/20 , C23C14/35 , H01L41/047 , H01L41/22 , C23C15/00
CPC分类号： C08J7/123 , C23C14/022 , C23C14/205 , H01L41/0477 , H01L41/29 , C08J2327/16
摘要： The invention deals with a method of electroding a poly(vinylidene fluoride) solid in a piezoelectric application. The electroding method entails surface preparation of the poly(vinylidene fluoride) by a variety of steps including plasma etching to create temporary molecular scale surface irregularities followed by sputtering a metallic layer before deterioration of the plasma etched surface. The chromium may be the initial metal sputtered, followed by a sputtered copper layer, followed in turn by at least one heavier electrodeposited conductive layer. The method may be conducted without deterioration of the piezoelectric properties of the material. The method has been found to provide very good adhesion between the electrode and the PVF.sub.2 surface.
摘要翻译：本发明涉及在压电应用中电聚聚（偏二氟乙烯）固体的方法。电铸方法需要通过各种步骤表面制备聚（偏二氟乙烯），包括等离子体蚀刻以产生临时的分子量表面不规则性，随后在等离子体蚀刻表面劣化之前溅射金属层。铬可以是溅射的初始金属，随后是溅射的铜层，接着又是至少一个较重的电沉积导电层。该方法可以在不劣化材料的压电性能的情况下进行。已经发现该方法在电极和PVF2表面之间提供非常好的粘合性。

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