专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06449839B1 Electrical circuit board and a method for making the same 失效
标题翻译：电路板及其制造方法
公开(公告)号：US06449839B1
公开(公告)日：2002-09-17
申请号：US09655986
申请日：2000-09-06
申请人： Andrew Z. Glovatsky , Thomas Krautheim , Robert E. Belke, Jr. , Vivek Amir Jairazbhoy , Cuong V. Pham
发明人： Andrew Z. Glovatsky , Thomas Krautheim , Robert E. Belke, Jr. , Vivek Amir Jairazbhoy , Cuong V. Pham
IPC分类号： H05K302
CPC分类号： H05K3/4084 , H05K1/056 , H05K3/062 , H05K3/4092 , H05K3/44 , H05K3/445 , H05K2201/0305 , H05K2201/0361 , H05K2201/0379 , H05K2201/0397 , H05K2201/09554 , H05K2203/0195 , H05K2203/063 , Y10T29/49128 , Y10T29/49144 , Y10T29/49156
摘要： A method for forming connections within a multi-layer electronic circuit board 10. In one non-limiting embodiment, the method includes selectively forming air bridges over portions of the circuit board 10 and selectively collapsing the air bridges with a metallurgical bonding tool, effective to interconnect layers of the circuit board 10.
摘要翻译：一种用于在多层电子电路板10内形成连接的方法。在一个非限制性实施例中，该方法包括在电路板10的部分上选择性地形成空气桥，并用冶金接合工具选择性地折叠气桥，电路板10的互连层。

2. 发明授权

US5579573A Method for fabricating an undercoated chip electrically interconnected to a substrate 失效
标题翻译：制造与基片电连接的底涂芯片的方法
公开(公告)号：US5579573A
公开(公告)日：1996-12-03
申请号：US320812
申请日：1994-10-11
申请人： Jay D. Baker , Cuong V. Pham , Robert E. Belke, Jr.
发明人： Jay D. Baker , Cuong V. Pham , Robert E. Belke, Jr.
IPC分类号： H01L21/56 , H05K3/34 , H01L21/50 , H05K3/38
CPC分类号： H01L24/29 , H01L21/563 , H01L24/32 , H01L2224/1319 , H01L2224/16225 , H01L2224/274 , H01L2224/32225 , H01L2224/73104 , H01L2224/73203 , H01L2224/73204 , H01L2224/83191 , H01L2224/83856 , H01L2924/01005 , H01L2924/01006 , H01L2924/01047 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , Y10T29/49144 , Y10T29/49146
摘要： Method for fabricating an undercoated chip electrically interconnected to a substrate. The method includes the initial step of depositing a predetermined quantity of a liquid undercoat material onto the chip or the substrate. The method continues with the step of interconnecting the chip to the substrate so as to form an electrical interconnection bond therebetween. Finally, the method concludes with the step of heating, reflowing and curing the undercoat material during or after the step of electrically interconnecting the chip to the substrate.
摘要翻译： `制造与基片电连接的底涂芯片的方法。该方法包括将预定量的液体底涂层材料沉积到芯片或基底上的初始步骤。该方法继续将芯片与衬底互连以在其间形成电互连结的步骤。最后，该方法的结论是在将芯片与衬底电互连的步骤期间或之后加热，回流和固化底涂层材料的步骤。

3. 发明授权

US07947911B1 Anti-tamper mesh 有权
标题翻译：防篡改网
公开(公告)号：US07947911B1
公开(公告)日：2011-05-24
申请号：US11944771
申请日：2007-11-26
申请人： Cuong V. Pham , David E. Chubin , Robert A. Clarke , Aaron D. Kuan
发明人： Cuong V. Pham , David E. Chubin , Robert A. Clarke , Aaron D. Kuan
IPC分类号： H05K7/02
CPC分类号： H05K3/125 , H05K1/0275 , H05K1/0284 , H05K1/0289 , H05K3/4664 , H05K2201/0999 , H05K2201/10151 , H05K2203/0126 , H05K2203/013 , H05K2203/1554 , Y10T29/49147 , Y10T29/49155
摘要： A method of forming an anti-tamper mesh on an electronic device. The method includes forming at least one terminal on the electronic device and forming a conductive mesh on at least one surface of the electronic device, wherein the conductive mesh is in electrical contact with the terminal, and wherein the terminal facilitates electrical conduction between the conductive mesh and an electrical detection circuit.
摘要翻译：一种在电子设备上形成防篡改网的方法。该方法包括在电子设备上形成至少一个端子并在电子器件的至少一个表面上形成导电网，其中导电网与端子电接触，并且其中端子有利于导电网之间的导电和电检测电路。

4. 发明授权

US08399781B1 Anti-tamper mesh 有权
标题翻译：防篡改网
公开(公告)号：US08399781B1
公开(公告)日：2013-03-19
申请号：US13045348
申请日：2011-03-10
申请人： Cuong V. Pham , David E. Chubin , Robert A. Clarke , Aaron D. Kuan
发明人： Cuong V. Pham , David E. Chubin , Robert A. Clarke , Aaron D. Kuan
IPC分类号： H01L23/48
CPC分类号： H05K3/125 , H05K1/0275 , H05K1/0284 , H05K1/0289 , H05K3/4664 , H05K2201/0999 , H05K2201/10151 , H05K2203/0126 , H05K2203/013 , H05K2203/1554 , Y10T29/49147 , Y10T29/49155
摘要： An electronic device includes at least one terminal formed on the electronic device. The electronic device also includes at least one of a semiconductor device, an integrated circuit chip, and a computer. A seamless conductive mesh is formed on at least one surface of the electronic device. The conductive mesh is in electrical contact with the terminal. The terminal facilitates electrical conduction between the conductive mesh and an electrical detection circuit. The electronic device also may include a pattern having traces formed on at least two surfaces where each of the traces includes a continuous loop of conductive material is formed on at least two surfaces. The electronic device also may include a first plurality of conductive loops formed on the electronic device that are continuous and surround the electronic device in a first direction and a second plurality of conductive loops formed on the electronic device that are continuous and surround the electronic device in a second direction.
摘要翻译：电子设备包括形成在电子设备上的至少一个终端。电子设备还包括半导体器件，集成电路芯片和计算机中的至少一个。在电子设备的至少一个表面上形成无缝导电网。导电网与端子电接触。该端子促进导电网和电检测电路之间的导电。电子设备还可以包括具有形成在至少两个表面上的迹线的图案，其中每个迹线包括导电材料的连续环形成在至少两个表面上。电子设备还可以包括形成在电子设备上的第一多个导电环路，其在第一方向上是连续的并围绕电子设备，并且形成在电子设备上的第二多个导电环路，其连续并围绕电子设备第二个方向。

5. 发明授权

US5510721A Method and adjustment for known good die testing using resilient conductive straps 失效
标题翻译：使用弹性导电带的已知良好模具测试的方法和调整
公开(公告)号：US5510721A
公开(公告)日：1996-04-23
申请号：US358297
申请日：1994-12-19
申请人： Bethany J. Walles , Cuong V. Pham , Lawrence L. Kneisel , Brian J. Hayden
发明人： Bethany J. Walles , Cuong V. Pham , Lawrence L. Kneisel , Brian J. Hayden
IPC分类号： G01R31/26 , G01R1/04 , G01R1/073
CPC分类号： G01R1/0735 , G01R1/0483
摘要： A test apparatus for testing a know-good die integrated circuit is disclosed. The test apparatus uses conductive straps extending across trenches. The straps align with bond pads on the integrated circuit. When the bond pads are brought into contact with the straps, the straps exert a counterforce in the opposite direction to ensure a good electrical contact while testing the integrated circuit.
摘要翻译：公开了一种用于测试专有芯片集成电路的测试装置。测试装置使用延伸穿过沟槽的导电带。带子与集成电路上的接合焊盘对齐。当接合垫与带子接触时，带子沿相反方向施加反作用力，以在测试集成电路时确保良好的电接触。

6. 发明授权

US5275058A Method and apparatus for detecting wire bond pull test failure modes 失效
标题翻译：检测引线拉拔试验失败模式的方法和装置
公开(公告)号：US5275058A
公开(公告)日：1994-01-04
申请号：US968938
申请日：1992-10-30
申请人： Cuong V. Pham , Brian J. Hayden
发明人： Cuong V. Pham , Brian J. Hayden
IPC分类号： G01N3/00 , G01N3/06 , G01N19/04 , H01L21/66 , G01N3/08
CPC分类号： G01N19/04 , G01N3/00 , H01L24/78 , H01L24/85 , G01N2203/0296 , G01N2203/0617 , H01L22/12 , H01L2224/48472 , H01L2224/78 , H01L2224/859 , H01L2924/00014 , H01L2924/14
摘要： Provided is a method and apparatus for electrically detecting the location of bond failure and wire breakage occurring during tensile strength testing of a wire sample having first and second bond foots affixed to respective first and second support pads. The method and apparatus monitors the voltage levels of first and second electrically conductive probes. The first probe has a primary lead in electrical contact with the first support pad and a secondary lead in electrical contact with the first bond foot. Similarly, the second electrically conductive probe has a primary lead in electrical contact with the second support pad and a secondary lead in electrical contact with the second bond foot. Voltage detection circuitry is provided in electrical contact with the first and second probes for detecting the voltage level at each of the respective primary and secondary leads to generate the respective corresponding output signals. Comparator circuitry is further provided in electrical contact with the voltage detection circuitry for receiving and comparing each of the output signals to a selected reference value and generating a supplemental output signal indicating the location of bond failure or wire breakage.
摘要翻译：提供了一种用于电检测在具有固定到相应的第一和第二支撑垫的第一和第二接合脚的线样品的拉伸强度测试期间发生的接合失效和断线位置的方法和装置。该方法和装置监测第一和第二导电探针的电压电平。第一探针具有与第一支撑垫电接触的主导线和与第一键脚电接触的次导线。类似地，第二导电探针具有与第二支撑垫电接触的主导线和与第二接合脚电接触的次导线。提供与第一和第二探针电接触的电压检测电路，用于检测各个主引线和次引线中的每一个的电压电平，以产生相应的相应的输出信号。进一步提供比较器电路与电压检测电路电接触，用于接收并将每个输出信号与所选参考值进行比较，并产生指示键合故障或断线位置的补充输出信号。

7. 发明授权

US07705439B2 Destructor integrated circuit chip, interposer electronic device and methods 有权
标题翻译：析晶器集成电路芯片，插件电子器件及方法
公开(公告)号：US07705439B2
公开(公告)日：2010-04-27
申请号：US11043626
申请日：2005-01-25
申请人： Cuong V. Pham , David E. Chubin , Aaron D. Kuan , Colleen L. Khalifa
发明人： Cuong V. Pham , David E. Chubin , Aaron D. Kuan , Colleen L. Khalifa
IPC分类号： H01L23/02
CPC分类号： H01L23/57 , H01L23/3128 , H01L24/16 , H01L24/48 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2924/00014 , H01L2924/09701 , H01L2924/14 , H01L2924/15192 , Y10S257/922 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor chip includes a first integrated circuit chip and a depression substrate attached to the integrated circuit chip, wherein the integrated circuit chip and the depression substrate define a cavity therebetween. The semiconductor chip also includes a stress sensitive material located in the cavity and a chemical located in the cavity, wherein detection of tampering causes a reaction by the chemical such that the semiconductor chip is at least partially destroyed.
摘要翻译：半导体芯片包括附接到集成电路芯片的第一集成电路芯片和凹陷基板，其中集成电路芯片和凹陷基板在其间限定空腔。半导体芯片还包括位于空腔中的应力敏感材料和位于空腔中的化学物质，其中篡改的检测导致化学品的反应，使得半导体芯片至少部分地被破坏。

8. 发明授权

US07640658B1 Methods for forming an anti-tamper pattern 有权
标题翻译：用于形成防篡改图案的方法
公开(公告)号：US07640658B1
公开(公告)日：2010-01-05
申请号：US11252402
申请日：2005-10-18
申请人： Cuong V. Pham , David E. Chubin , Robert A. Clarke , Aaron D. Kuan
发明人： Cuong V. Pham , David E. Chubin , Robert A. Clarke , Aaron D. Kuan
IPC分类号： H05K3/02 , H05K3/10
CPC分类号： H05K3/125 , H05K1/0275 , H05K1/0284 , H05K1/0289 , H05K3/4664 , H05K2201/0999 , H05K2201/10151 , H05K2203/0126 , H05K2203/013 , H05K2203/1554 , Y10T29/49147 , Y10T29/49155
摘要： A method of forming an anti-tamper mesh on an electronic device. The method includes forming at least one terminal on the electronic device and forming a conductive mesh on at least one surface of the electronic device, wherein the conductive mesh is in electrical contact with the terminal, and wherein the terminal facilitates electrical conduction between the conductive mesh and an electrical detection circuit.
摘要翻译：一种在电子设备上形成防篡改网的方法。该方法包括在电子设备上形成至少一个端子并在电子器件的至少一个表面上形成导电网，其中导电网与端子电接触，并且其中端子有利于导电网之间的导电和电检测电路。

9. 发明授权

US5427301A Ultrasonic flip chip process and apparatus 失效
标题翻译：超声倒装芯片工艺及设备
公开(公告)号：US5427301A
公开(公告)日：1995-06-27
申请号：US239106
申请日：1994-05-06
申请人： Cuong V. Pham , Brian J. Hayden , Bethany J. Walles
发明人： Cuong V. Pham , Brian J. Hayden , Bethany J. Walles
IPC分类号： B23K20/10 , H01L21/60 , H01L21/607
CPC分类号： H01L24/75 , B23K20/10 , B23K20/106 , H01L24/81 , H01L2224/13144 , H01L2224/75 , H01L2224/75743 , H01L2224/81205 , H01L2224/81801 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/09701 , H01L2924/10253
摘要： A process for bonding a flip chip (20) to a substrate (22) comprising positioning the flip chip (20) above the substrate (22). The flip chip (20) has an active face provided with conductive bumps so that its active face is oriented toward the substrate (22). The flip chip (20) is placed on the substrate (22) so that the bumps align with a bonding pattern on the substrate (22). An ultrasonic horn (30) is lowered having a flat surface onto a back side of the flip chip (20). Force is applied through the ultrasonic horn (30) to the back side of the flip chip (20), which is normal to the substrate (22) so that minimal lateral displacement of the flip chip (20) and the substrate (22) results. The ultrasonic horn (30) is then activated while the force is applied so that the ultrasonic energy is isothermally transferred across the flip chip (20) to the substrate (22) and a diffusion bond is created therebetween.
摘要翻译：一种用于将倒装芯片（20）接合到衬底（22）的工艺，包括将所述倒装芯片（20）定位在所述衬底（22）上方。倒装芯片（20）具有设置有导电凸块的有源面，使得其有源面朝向衬底（22）。将倒装芯片（20）放置在基板（22）上，使得凸块与衬底（22）上的接合图案对准。在倒装芯片（20）的背面上，具有平坦表面的超声波喇叭（30）被降低。力通过超声波喇叭（30）施加到倒装芯片（20）的与衬底（22）垂直的背面，使得倒装芯片（20）和衬底（22）的最小横向位移产生。然后在施加力的同时激活超声波喇叭（30），使超声能量通过倒装芯片（20）等温转移到衬底（22），并且在其间产生扩散接合。

10. 发明授权

US07880248B1 Destructor integrated circuit chip, interposer electronic device and methods 有权
标题翻译：析晶器集成电路芯片，插件电子器件及方法
公开(公告)号：US07880248B1
公开(公告)日：2011-02-01
申请号：US12368256
申请日：2009-02-09
申请人： Cuong V. Pham , David E. Chubin , Colleen L. Khalifa
发明人： Cuong V. Pham , David E. Chubin , Colleen L. Khalifa
IPC分类号： G01P15/08
CPC分类号： H01L23/573 , H01L23/576 , H01L2224/13 , H01L2224/16225 , H01L2224/48091 , H01L2224/48465 , H01L2924/10158 , Y10S257/922 , H01L2924/00014 , H01L2924/00012
摘要： A semiconductor device. The device includes a substrate and an integrated circuit chip. The device also includes an electrically or thermally reactive layer located between a top surface of the substrate and a bottom surface of the integrated circuit chip, wherein the reactive layer is positioned such that detection of tampering causes the reactive layer to be electrically or thermally energized such that the semiconductor device is at least partially destroyed.
摘要翻译：半导体器件。该器件包括衬底和集成电路芯片。该装置还包括位于基板的顶表面和集成电路芯片的底表面之间的电或热反应层，其中反应层被定位成使得检测篡改导致反应层被电或热激励，例如半导体器件至少部分被破坏。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式