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1. 发明授权

US07480888B1 Design structure for facilitating engineering changes in integrated circuits 失效
标题翻译：集成电路工程变更的设计结构
公开(公告)号：US07480888B1
公开(公告)日：2009-01-20
申请号：US12124771
申请日：2008-05-21
申请人： Clarence Rosser Ogilvie , Charles B. Winn , David Wills Milton , Kenneth Anthony Lauricella , Nitin Sharma , Paul Mark Schanely , Robert Dov Herzl , Robert Spencer Horton , Tad Jeffrey Wilder , Douglas P. Nadeau
发明人： Clarence Rosser Ogilvie , Charles B. Winn , David Wills Milton , Kenneth Anthony Lauricella , Nitin Sharma , Paul Mark Schanely , Robert Dov Herzl , Robert Spencer Horton , Tad Jeffrey Wilder , Douglas P. Nadeau
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A design structure embodied in a machine-readable medium is disclosed in one embodiment of the invention as including a flexible logic block to facilitate engineering changes at selected locations within an IC. The flexible logic block has a consistent and identifiable structure such that a simple automated process may be used to reconfigure the structure to perform different logical operations. In certain embodiments, the flexible logic block includes a circuit, such as a multiplexer, having multiple inputs and at least one output. A metal interconnect structure is coupled to the inputs and enables connection of each of the inputs to one of several electrical potentials using a focused-ion-beam (FIB) tool. In this way, the circuit may be configured to perform different logical operations after components in the IC exist in hardware.
摘要翻译：在本发明的一个实施例中公开了体现在机器可读介质中的设计结构，包括用于促进在IC内的选定位置进行工程变更的灵活逻辑块。灵活的逻辑块具有一致且可识别的结构，使得可以使用简单的自动化过程来重新配置结构以执行不同的逻辑操作。在某些实施例中，柔性逻辑块包括具有多个输入和至少一个输出的电路，例如多路复用器。金属互连结构耦合到输入端，并且能够使用聚焦离子束（FIB）工具将每个输入端连接到几个电势之一。以这种方式，电路可以被配置为在硬件中存在IC中的部件之后执行不同的逻辑操作。

2. 发明授权

US6157981A Real time invariant behavior cache 失效
标题翻译：实时不变行为缓存
公开(公告)号：US6157981A
公开(公告)日：2000-12-05
申请号：US85956
申请日：1998-05-27
申请人： Bartholomew Blaner , Henry Harvey Burkhart , Robert Dov Herzl , Kenneth Anthony Lauricella , Clarence Rosser Ogilvie , Arnold Steven Tran
发明人： Bartholomew Blaner , Henry Harvey Burkhart , Robert Dov Herzl , Kenneth Anthony Lauricella , Clarence Rosser Ogilvie , Arnold Steven Tran
IPC分类号： G06F9/445 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0802 , G06F9/445
摘要： A memory and memory architecture for use by a processor executing real time code and a system on a chip including the processor and memory containing the code. An effective address is maintained in a cache directory. In the preferred embodiment memory, individual functions are loaded into physical memory at permanently selected locations and selected by the effective address in the cache directory. By preselecting task storage locations, system performance may be tuned or optimized to assure predictable performance or task execution.
摘要翻译：一种由执行实时代码的处理器使用的存储器和存储器架构以及包括处理器和包含代码的存储器的芯片上的系统。高速缓存目录中保留有效的地址。在优选实施例的存储器中，将各个功能在永久选择的位置加载到物理存储器中，并通过高速缓存目录中的有效地址进行选择。通过预选任务存储位置，可以调整或优化系统性能以确保可预测的性能或任务执行。

3. 发明授权

US5953510A Bidirectional data bus reservation priority controls having token logic 失效
标题翻译：具有令牌逻辑的双向数据总线预留优先级控制
公开(公告)号：US5953510A
公开(公告)日：1999-09-14
申请号：US755237
申请日：1991-09-05
申请人： Robert Dov Herzl , David Andrew Schroter
发明人： Robert Dov Herzl , David Andrew Schroter
IPC分类号： G06F9/52 , G06F12/08 , G06F13/18 , G06F13/368 , G06F13/37 , G06F13/38 , G06F15/16 , G06F15/177 , G06F13/14
CPC分类号： G06F13/37 , G06F13/18
摘要： A data bus reservation system controls data transfer between storage control elements (SCEs) in a multi-processor system. Each SCE is assigned a default bidirectional (BIDI) data bus for transfer of data. If a request for data transfer is made and the default data bus is already reserved, then the requestor must wait for the data bus to become available and a token passed to the requestor. When the token is passed to the requester, it has priority to reserve an available data bus. The token is passed to a different processor with each machine cycle. Additionally, there is error checking logic which checks a confirmation sent to the other SCE when the BIDI bus has been reserved.
摘要翻译：数据总线预留系统控制多处理器系统中的存储控制元件（SCE）之间的数据传输。为每个SCE分配一个用于传输数据的默认双向（BIDI）数据总线。如果进行了数据传输请求，并且默认数据总线已经被保留，则请求者必须等待数据总线变得可用并且令牌传递给请求者。当令牌传递给请求者时，优先保留可用的数据总线。每个机器周期将令牌传递给不同的处理器。另外，当BIDI总线被保留时，存在检查发送到另一个SCE的确认的错误检查逻辑。

4. 发明授权

US5930832A Apparatus to guarantee TLB inclusion for store operations 失效
标题翻译：用于保证商店运营中TLB包含的设备
公开(公告)号：US5930832A
公开(公告)日：1999-07-27
申请号：US660560
申请日：1996-06-07
申请人： Jay Gerald Heaslip , Robert Dov Herzl , Arnold Steven Tran
发明人： Jay Gerald Heaslip , Robert Dov Herzl , Arnold Steven Tran
IPC分类号： G06F12/10
CPC分类号： G06F12/1054
摘要： A computer system includes a processor and a cache and memory management unit. The processor includes a means for retiring instructions in program order. The cache and memory management unit includes means for detecting when a translation has been evicted from a lookaside buffer and means for communicating eviction information to the means for retiring instructions in program order. The means for retiring instructions in program order includes means for holding a storage related instruction which causes a miss in the lookaside buffer or in the cache in a first pass of execution until the instruction becomes the oldest storage related instruction in program sequence and further includes means responsive to the eviction information for flushing all storage related instructions except the current storage related instruction. The system avoids the occurrence of misses in the buffer late in execution (e.g., PASS 2 or later), thus avoiding a necessity for complex recovery provisions.
摘要翻译：计算机系统包括处理器和高速缓存和存储器管理单元。处理器包括以程序顺序退出指令的装置。高速缓存和存储器管理单元包括用于检测翻译是否已被从后视缓冲器驱逐的装置，以及用于以程序顺序将用于退出指令的装置传送驱逐信息的装置。用于以程序顺序退出指令的装置包括用于保持存储相关指令的装置，该指令在执行的第一次执行中导致后备缓冲器或高速缓存中的未命中，直到指令成为程序序列中最旧的存储相关指令，并且还包括装置响应于驱逐信息，用于冲洗除了当前存储相关指令之外的所有存储相关指令。该系统避免缓冲区在执行时间晚（例如PASS 2或更高版本）中发生错误，从而避免复杂恢复规定的必要性。

5. 发明授权

US5835714A Method and apparatus for reservation of data buses between multiple storage control elements 失效
标题翻译：用于在多个存储控制元件之间预留数据总线的方法和装置
公开(公告)号：US5835714A
公开(公告)日：1998-11-10
申请号：US459875
申请日：1995-06-02
申请人： Robert Dov Herzl , David Andrew Schroter
发明人： Robert Dov Herzl , David Andrew Schroter
IPC分类号： G06F9/52 , G06F12/08 , G06F13/18 , G06F13/368 , G06F13/37 , G06F13/38 , G06F15/16 , G06F15/177
CPC分类号： G06F13/37 , G06F13/18
摘要： A data bus reservation system controls data transfer between storage control elements (SCEs) in a multi-processor system. Each SCE is assigned a default bidirectional (BIDI) data bus for transfer of data. If a request for data transfer is made and the default data bus is already reserved, then the requester must wait for the data bus to become available and a token passed to the requester. When the token is passed to the requester, it has priority to reserve an available data bus. The token is passed to a different processor with each machine cycle. Additionally, there is error checking logic which checks a confirmation sent to the other SCE when the BIDI bus has been reserved.
摘要翻译：数据总线预留系统控制多处理器系统中的存储控制元件（SCE）之间的数据传输。为每个SCE分配一个用于传输数据的默认双向（BIDI）数据总线。如果进行了数据传输请求，并且默认数据总线已经被保留，则请求者必须等待数据总线变为可用并且令牌传递给请求者。当令牌传递给请求者时，优先保留可用的数据总线。每个机器周期将令牌传递给不同的处理器。另外，当BIDI总线被保留时，存在检查发送到另一个SCE的确认的错误检查逻辑。

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