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1. 发明授权

US06338133B1 Measured, allocation of speculative branch instructions to processor execution units 失效
标题翻译：测量，分配给处理器执行单元的推测分支指令
公开(公告)号：US06338133B1
公开(公告)日：2002-01-08
申请号：US09267200
申请日：1999-03-12
申请人： David Andrew Schroter
发明人： David Andrew Schroter
IPC分类号： G06F938
CPC分类号： G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3857
摘要： A method and system for branch dispatching of instructions in a data processor. A processor having one or more buffers for storing instructions and one or more execution units for executing instructions is utilized. Each unit has a corresponding queue which holds instructions pending execution. First, a threshold level (selected maximum number of instructions in the instruction queue) is set. The current utilization measure for one or more execution units in the data processing system is determined. The current utilization measure is compared to the predetermined threshold value; and a speculative branch instruction is dispatched to a selected execution unit when the current utilization measure is less than the predetermined threshold value.
摘要翻译：一种用于在数据处理器中分支调度指令的方法和系统。利用具有用于存储指令的一个或多个缓冲器和用于执行指令的一个或多个执行单元的处理器。每个单元都有一个对应的队列，其中保存指令等待执行。首先，设置阈值级别（指令队列中指定的最大指令数）。确定数据处理系统中的一个或多个执行单元的当前利用措施。将当前利用度量与预定阈值进行比较; 并且当当前利用度量小于预定阈值时，将推测性分支指令调度到所选择的执行单元。

2. 发明授权

US5835714A Method and apparatus for reservation of data buses between multiple storage control elements 失效
标题翻译：用于在多个存储控制元件之间预留数据总线的方法和装置
公开(公告)号：US5835714A
公开(公告)日：1998-11-10
申请号：US459875
申请日：1995-06-02
申请人： Robert Dov Herzl , David Andrew Schroter
发明人： Robert Dov Herzl , David Andrew Schroter
IPC分类号： G06F9/52 , G06F12/08 , G06F13/18 , G06F13/368 , G06F13/37 , G06F13/38 , G06F15/16 , G06F15/177
CPC分类号： G06F13/37 , G06F13/18
摘要： A data bus reservation system controls data transfer between storage control elements (SCEs) in a multi-processor system. Each SCE is assigned a default bidirectional (BIDI) data bus for transfer of data. If a request for data transfer is made and the default data bus is already reserved, then the requester must wait for the data bus to become available and a token passed to the requester. When the token is passed to the requester, it has priority to reserve an available data bus. The token is passed to a different processor with each machine cycle. Additionally, there is error checking logic which checks a confirmation sent to the other SCE when the BIDI bus has been reserved.
摘要翻译：数据总线预留系统控制多处理器系统中的存储控制元件（SCE）之间的数据传输。为每个SCE分配一个用于传输数据的默认双向（BIDI）数据总线。如果进行了数据传输请求，并且默认数据总线已经被保留，则请求者必须等待数据总线变为可用并且令牌传递给请求者。当令牌传递给请求者时，优先保留可用的数据总线。每个机器周期将令牌传递给不同的处理器。另外，当BIDI总线被保留时，存在检查发送到另一个SCE的确认的错误检查逻辑。

3. 发明授权

US06275918B1 Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator threshold 失效
标题翻译：从增加访问指示符阈值的数量获取历史表信息中的载入目标操作数预取地址
公开(公告)号：US06275918B1
公开(公告)日：2001-08-14
申请号：US09268307
申请日：1999-03-16
申请人： William Elton Burky , Peter Steven Lenk , Dung Quoc Nguyen , David Andrew Schroter , Shih-Hsiung Stephen Tung , Michael Thomas Vaden
发明人： William Elton Burky , Peter Steven Lenk , Dung Quoc Nguyen , David Andrew Schroter , Shih-Hsiung Stephen Tung , Michael Thomas Vaden
IPC分类号： G06F934
CPC分类号： G06F9/383 , G06F9/3455 , G06F9/3832
摘要： A method and system for improving pre-fetch accuracy in a data processing system utilizing a pre-fetch history table is disclosed. The method compares a portion of an instruction address to an address located as an entry in a pre-fetch history table based on the status of a validity bit contained in the entry. If the validity bit is set and the addresses match, an indicator field within the entry is checked to see if it is equal to or greater than a threshold level. When the indicator field is greater than the threshold level, a target operand address is pre-fetched based on stride and direction.
摘要翻译：公开了一种利用预取历史表改善数据处理系统中的预取精度的方法和系统。该方法基于条目中包含的有效位的状态，将指令地址的一部分与位于预取历史表中的条目的地址进行比较。如果有效位被设置并且地址匹配，则检查条目内的指示符字段以查看其是否等于或大于阈值级别。当指示符字段大于阈值电平时，将根据步幅和方向预取目标操作数地址。

4. 发明授权

US06792524B1 System and method cancelling a speculative branch 失效
标题翻译：系统和方法取消推测分支
公开(公告)号：US06792524B1
公开(公告)日：2004-09-14
申请号：US09137653
申请日：1998-08-20
申请人： Milford John Peterson , David Andrew Schroter , Albert James Van Norstrand
发明人： Milford John Peterson , David Andrew Schroter , Albert James Van Norstrand
IPC分类号： G06F944
CPC分类号： G06F9/3842 , G06F9/3844
摘要： For each predicted branch within a processor, an entry is maintained within a branch history table. The entry within the branch history table also includes an indication of the past record for that particular branch instruction, which indicates how correct the branch prediction has been in the past. When the field value associated with the predicted branch exceeds a certain threshold, indicating that the past predictions associated with that branch instruction have been at an unacceptable level, then the speculative branch instructions dispatching is suspended for that particular branch instruction. Alternative embodiments utilize a global indicator for suspending or cancelling instruction dispatch when the frequency of previous incorrect branch predictions increases beyond a preselected threshold.
摘要翻译：对于处理器内的每个预测分支，条目保持在分支历史表中。分支历史表中的条目还包括针对该特定分支指令的过去记录的指示，其指示分支预测在过去如何正确。当与预测分支相关联的字段值超过某个阈值时，指示与该分支指令相关联的过去预测已经处于不可接受的水平，则针对该特定分支指令暂停推测分支指令分派。当先前错误分支预测的频率增加超过预选阈值时，替代实施例利用全局指示符来暂停或取消指令分派。

5. 发明授权

US6061785A Data processing system having an apparatus for out-of-order register operations and method therefor 失效
标题翻译：数据处理系统具有无序寄存器操作的装置及其方法
公开(公告)号：US6061785A
公开(公告)日：2000-05-09
申请号：US24804
申请日：1998-02-17
申请人： Kevin Arthur Chiarot , A. James Van Norstrand, Jr. , David Andrew Schroter
发明人： Kevin Arthur Chiarot , A. James Van Norstrand, Jr. , David Andrew Schroter
IPC分类号： G06F9/305 , G06F9/32 , G06F9/38 , G06F15/00
CPC分类号： G06F9/30094 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： An apparatus for condition register (CR) renaming and methods of using the same are implemented. In a central processing unit (CPU) having a pipelined architecture, logical operations on CR operands may be executed out-of-order using the CR renaming mechanism. Any instruction that updates the CR data has an associated instruction identifier (IID) stored in a register. Subsequent condition register logical (LCR) instructions that use data in the CR use the stored IID to determine when the CR data has been updated by the execution of the instruction corresponding to the stored IID. When an instruction causing a CR data value update finishes executing, the updated data is obtained by snooping the finish bus of the corresponding execution unit. In this way, these instructions can obtain CR data prior to completion of the preceding instructions. Because the updated CR data is available to the LCR next to execute before the updating instruction completes, deserialized execution of LCR instructions is thereby realized.
摘要翻译：实现了条件寄存器（CR）重命名的装置及其使用方法。在具有流水线架构的中央处理单元（CPU）中，使用CR重命名机制可以执行对无效操作数的逻辑运算。更新CR数据的任何指令都具有存储在寄存器中的关联指令标识符（IID）。使用CR中的数据的后续条件寄存器逻辑（LCR）指令使用存储的IID来确定通过执行与存储的IID相对应的指令来更新CR数据。当导致CR数据值更新的指令完成执行时，通过窥探相应执行单元的完成总线来获得更新的数据。以这种方式，这些指令可以在完成前面的指令之前获得CR数据。因为在更新指令完成之前更新的CR数据可用于下一个执行的LCR，从而实现了反序列化执行LCR指令。

6. 发明授权

US6035394A System for providing high performance speculative processing of complex load/store instructions by generating primitive instructions in the load/store unit and sequencer in parallel 失效
标题翻译：用于通过在并行装载/存储单元和定序器中产生原始指令来提供复杂加载/存储指令的高性能推测性处理的系统
公开(公告)号：US6035394A
公开(公告)日：2000-03-07
申请号：US24805
申请日：1998-02-17
申请人： David Scott Ray , Kevin Arthur Chiarot , David Andrew Schroter , A. James Van Norstrand, Jr. , Barry Duane Williamson
发明人： David Scott Ray , Kevin Arthur Chiarot , David Andrew Schroter , A. James Van Norstrand, Jr. , Barry Duane Williamson
IPC分类号： G06F9/30 , G06F9/312 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/3017 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： One aspect of the invention relates to a method for operating a superscalar processor having an instruction cache, a sequencing unit, a load/store unit, a cache, an architectural register file and a rename register file. In one particular version of the invention, the method includes the steps of forwarding an instruction from the instruction cache to the sequencing unit operable to access multiple architectural registers; generating a plurality of primitive instructions responsive to the forwarded instruction in which an individual primitive instruction is operable to access an individual architectural register; and sequentially issuing the primitive instructions to move data between the data cache and the rename register file.
摘要翻译：本发明的一个方面涉及一种用于操作具有指令高速缓存，排序单元，加载/存储单元，高速缓存，架构寄存器文件和重命名寄存器文件的超标量处理器的方法。在本发明的一个特定版本中，该方法包括以下步骤：将指令从指令高速缓存转发到可操作以访问多个架构寄存器的排序单元; 响应于转发的指令产生多个原语指令，其中单个原语指令可操作以访问单个体系结构寄存器; 并顺序地发出原始指令以在数据高速缓存和重命名寄存器文件之间移动数据。

7. 发明授权

US5953510A Bidirectional data bus reservation priority controls having token logic 失效
标题翻译：具有令牌逻辑的双向数据总线预留优先级控制
公开(公告)号：US5953510A
公开(公告)日：1999-09-14
申请号：US755237
申请日：1991-09-05
申请人： Robert Dov Herzl , David Andrew Schroter
发明人： Robert Dov Herzl , David Andrew Schroter
IPC分类号： G06F9/52 , G06F12/08 , G06F13/18 , G06F13/368 , G06F13/37 , G06F13/38 , G06F15/16 , G06F15/177 , G06F13/14
CPC分类号： G06F13/37 , G06F13/18
摘要： A data bus reservation system controls data transfer between storage control elements (SCEs) in a multi-processor system. Each SCE is assigned a default bidirectional (BIDI) data bus for transfer of data. If a request for data transfer is made and the default data bus is already reserved, then the requestor must wait for the data bus to become available and a token passed to the requestor. When the token is passed to the requester, it has priority to reserve an available data bus. The token is passed to a different processor with each machine cycle. Additionally, there is error checking logic which checks a confirmation sent to the other SCE when the BIDI bus has been reserved.
摘要翻译：数据总线预留系统控制多处理器系统中的存储控制元件（SCE）之间的数据传输。为每个SCE分配一个用于传输数据的默认双向（BIDI）数据总线。如果进行了数据传输请求，并且默认数据总线已经被保留，则请求者必须等待数据总线变得可用并且令牌传递给请求者。当令牌传递给请求者时，优先保留可用的数据总线。每个机器周期将令牌传递给不同的处理器。另外，当BIDI总线被保留时，存在检查发送到另一个SCE的确认的错误检查逻辑。

8. 发明授权

US06430680B1 Processor and method of prefetching data based upon a detected stride 失效
标题翻译：基于检测到的步幅预取数据的处理器和方法
公开(公告)号：US06430680B1
公开(公告)日：2002-08-06
申请号：US09052567
申请日：1998-03-31
申请人： William Elton Burky , David Andrew Schroter , Shih-Hsiung Stephen Tung , Michael Thomas Vaden
发明人： William Elton Burky , David Andrew Schroter , Shih-Hsiung Stephen Tung , Michael Thomas Vaden
IPC分类号： G06F900
CPC分类号： G06F9/3455 , G06F9/3832
摘要： A processor and method of fetching data within a data processing system are disclosed. According to the method, a first difference between a first load address and a second load address is calculated. In addition, a determination is made whether a second difference between a third load address and the second load address is equal to the first difference. In response to a determination that the first difference and the second difference are equal, a fourth load address, which is generated by adding the third address and the second difference, is transmitted to the memory as a memory fetch address. In an embodiment of the data processing system including a processor having an associated cache, the fourth load address is transmitted to the memory only if the fourth load address is not resident in the cache or the target of an outstanding memory fetch request.
摘要翻译：公开了一种在数据处理系统内取出数据的处理器和方法。根据该方法，计算第一加载地址和第二加载地址之间的第一差。此外，确定第三加载地址和第二加载地址之间的第二差是否等于第一差。响应于确定第一差异和第二差异相等，通过将第三地址和第二差值相加产生的第四加载地址作为存储器提取地址被发送到存储器。在包括具有关联高速缓存的处理器的数据处理系统的实施例中，仅当第四加载地址不驻留在高速缓存中或未完成的存储器提取请求的目标时才将第四加载地址发送到存储器。

9. 发明授权

US06401192B1 Apparatus for software initiated prefetch and method therefor 失效
标题翻译：软件启动预取装置及其方法
公开(公告)号：US06401192B1
公开(公告)日：2002-06-04
申请号：US09166435
申请日：1998-10-05
申请人： David Andrew Schroter , Michael Thomas Vaden
发明人： David Andrew Schroter , Michael Thomas Vaden
IPC分类号： G06F900
CPC分类号： G06F9/383 , G06F9/30047 , G06F9/3455 , G06F12/0862 , G06F2212/6028
摘要： A mechanism and method for software hint initiated prefetch is provided. The prefetch may be directed to a prefetch of data for loading into a data cache, instructions for entry into an instruction cache or for either, in an embodiment having a combined cache. In response to a software instruction in an instruction stream, a plurality of prefetch specification data values are loaded into a register having a plurality of entries corresponding thereto. Prefetch specification data values include the address of the first cache line to be prefetched, and the stride, or the incremental offset, of the address of subsequent lines to be prefetched. Prefetch requests are generated by a prefetch control state machine using the prefetch specification data values stored in the register. Prefetch requests are issued to a hierarchy of cache memory devices. If a cache hit occurs having the specified cache coherency, the prefetch is vitiated. Otherwise, the request is passed to system memory for retrieval of the requested cache line.
摘要翻译：提供了软件提示启动预取的机制和方法。预取可以被引导到用于加载到数据高速缓存中的数据的预取，用于进入指令高速缓存的指令，或者在具有组合高速缓存的实施例中。响应于指令流中的软件指令，将多个预取指定数据值加载到具有与其对应的多个条目的寄存器中。预取指定数据值包括要预取的第一个高速缓存行的地址以及要预取的后续行的地址的步幅或增量偏移量。预取请求由预取控制状态机使用寄存器中存储的预取指定数据值生成。预取请求被发布到高速缓存存储器设备的层次结构。如果发生具有指定高速缓存一致性的高速缓存命中，则预取将被破坏。否则，请求被传递到系统内存以检索所请求的高速缓存行。

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