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1. 发明授权

US09182991B2 Multi-threaded processor instruction balancing through instruction uncertainty 有权
标题翻译：多线程处理器指令平衡通过指令不确定
公开(公告)号：US09182991B2
公开(公告)日：2015-11-10
申请号：US13366999
申请日：2012-02-06
申请人： Alper Buyuktosunoglu , Brian R. Prasky , Vijayalakshmi Srinivasan
发明人： Alper Buyuktosunoglu , Brian R. Prasky , Vijayalakshmi Srinivasan
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/3851
摘要： A computer system for instruction execution includes a processor having a pipeline. The system is configured to perform a method including fetching, in the pipeline, a plurality of instructions, wherein the plurality of instructions includes a plurality of branch instructions, for each of the plurality of branch instructions, assigning a branch uncertainty to each of the plurality of branch instructions, for each of the plurality of instructions, assigning an instruction uncertainty that is a summation of branch uncertainties of older unresolved branches and balancing the instructions, based on a current summation of instruction uncertainty, in the pipeline.
摘要翻译：用于指令执行的计算机系统包括具有流水线的处理器。该系统被配置为执行一种方法，包括在流水线中取出多个指令，其中多个指令包括多个分支指令，对于多个分支指令中的每一个，向多个指令中的每一个指派分支不确定度对于所述多个指令中的每一个指令，分配指示不确定性，所述指令不确定性是基于所述流水线中的指令不确定性的当前求和而作为旧的未解析分支的分支不确定性的总和并且平衡所述指令。

2. 发明申请

US20130311812A1 Power Shifting in Multicore Platforms by Varying SMT Levels 有权
公开(公告)号：US20130311812A1
公开(公告)日：2013-11-21
申请号：US13529161
申请日：2012-06-21
申请人： Pradip Bose , Alper Buyuktosunoglu , Dilma M. Da Silva , Hubertus Franke , Priyanka Tembey
发明人： Pradip Bose , Alper Buyuktosunoglu , Dilma M. Da Silva , Hubertus Franke , Priyanka Tembey
IPC分类号： G06F1/26 , G06F9/46 , G06F11/30
CPC分类号： G06F1/3206 , G06F1/26 , G06F1/3203 , G06F1/329 , G06F9/4893 , G06F9/50 , Y02D10/24
摘要： Power consumption in a microprocessor platform is managed by setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications. The multi-core microprocessor platform contains a plurality of physical cores, and each physical core is configurable into a plurality of logical cores. A simultaneous multithreading level in at least one physical core is adjusted by changing the number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level. Performance and power data based on simultaneous multi-threading levels are used in selecting the physical core to be adjusted.

3. 发明申请

US20130311811A1 Power Shifting in Multicore Platforms by Varying SMT Levels 有权
公开(公告)号：US20130311811A1
公开(公告)日：2013-11-21
申请号：US13476179
申请日：2012-05-21
申请人： Pradip Bose , Alper Buyuktosunoglu , Dilma Menezes Da Silva , Hubertus Franke , Priyanka Tembey
发明人： Pradip Bose , Alper Buyuktosunoglu , Dilma Menezes Da Silva , Hubertus Franke , Priyanka Tembey
IPC分类号： G06F1/28 , G06F9/30
CPC分类号： G06F1/3206 , G06F1/26 , G06F1/3203 , G06F1/329 , G06F9/4893 , G06F9/50 , Y02D10/24
摘要： Power consumption in a microprocessor platform is managed by setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications. The multi-core microprocessor platform contains a plurality of physical cores, and each physical core is configurable into a plurality of logical cores. A simultaneous multithreading level in at least one physical core is adjusted by changing the number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level. Performance and power data based on simultaneous multi-threading levels are used in selecting the physical core to be adjusted.

4. 发明授权

US08564262B2 Voltage regulator module with power gating and bypass 失效
标题翻译：电压调节器模块，带电源门控和旁路
公开(公告)号：US08564262B2
公开(公告)日：2013-10-22
申请号：US12944392
申请日：2010-11-11
申请人： Pradip Bose , Alper Buyuktosunoglu , Hans M. Jacobson , Seongwon Kim
发明人： Pradip Bose , Alper Buyuktosunoglu , Hans M. Jacobson , Seongwon Kim
IPC分类号： G05G1/56
CPC分类号： G05F1/575 , G05F1/565
摘要： Mechanisms are provided for either power gating or bypassing a voltage regulator. Responsive to receiving an asserted power gate signal to power gate the output voltage of the voltage regulator, at least one of first control circuitry power gates the output voltage of a first circuit or second control circuitry power gates the output voltage of a second circuit such that substantially no voltage to is output by the first circuit to a primary output node. Responsive to receiving an asserted bypass signal to bypass the output voltage of the voltage regulator, at least one of the first control circuitry bypasses the output voltage of the first circuit or the second control circuitry bypasses the output voltage of a second circuit such that substantially the voltage of a voltage source is output by the first circuit to the primary output node.
摘要翻译：提供电源门控或旁路电压调节器的机制。响应于接收到被断言的电源门信号以对所述电压调节器的输出电压进行电源门控，第一控制电路电源的至少一个功率门是第一电路或第二控制电路电路的输出电压门控第二电路的输出电压，使得基本上没有电压被第一电路输出到主输出节点。响应于接收断言的旁路信号以绕过电压调节器的输出电压，第一控制电路中的至少一个旁路第一电路或第二控制电路的输出电压旁路第二电路的输出电压，使得基本上电压源的电压由第一电路输出到主输出节点。

5. 发明授权

US08271809B2 On-chip power proxy based architecture 有权
标题翻译：基于片上功率代理的架构
公开(公告)号：US08271809B2
公开(公告)日：2012-09-18
申请号：US12424161
申请日：2009-04-15
申请人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd
发明人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd
IPC分类号： G06F1/26 , G06F1/28 , G06F1/32
CPC分类号： G06F11/348 , G06F11/3006 , G06F11/3024 , G06F11/3062 , G06F2201/88 , Y02D10/34
摘要： Illustrative embodiments estimate power consumption within a multi-core microprocessor chip. An authorized user selects a set of activities to be monitored. A value for each activity of the set of activities is stored in a separate counter of a set of counters, forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. The set of activities are grouped into subsets. The stored values corresponding to each activity in each subset are summed, forming a total value for each subset. The total value of each subset is multiplied by a factor corresponding to the subset, forming a scaled value for each subset. The scaled value of each subset is summed, forming a power usage value. A power manager adjusts the operational parameters of the unit based on a comparison of the power usage value to a threshold value.
摘要翻译：说明性实施例估计多核微处理器芯片内的功率消耗。授权用户选择要监视的一组活动。一组活动的每个活动的值存储在一组计数器的单独计数器中，形成一组存储的值。该值包括计数乘以活动特有的权重因子。该组活动被分组成子集。将对应于每个子集中的每个活动的存储值相加，形成每个子集的总值。每个子集的总值乘以与子集对应的因子，形成每个子集的缩放值。将每个子集的缩放值相加，形成功率使用值。功率管理器基于功率使用值与阈值的比较来调整单元的操作参数。

6. 发明授权

US08271765B2 Managing instructions for more efficient load/store unit usage 有权
标题翻译：管理更有效的加载/存储单元使用说明
公开(公告)号：US08271765B2
公开(公告)日：2012-09-18
申请号：US12420143
申请日：2009-04-08
申请人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd , Dung Quoc Nguyen , Bruce Joseph Ronchetti
发明人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd , Dung Quoc Nguyen , Bruce Joseph Ronchetti
IPC分类号： G06F9/00
CPC分类号： G06F9/3861 , G06F9/3824 , G06F9/3836 , G06F11/348 , G06F2201/88 , Y02D10/34
摘要： The illustrative embodiments described herein provide a computer-implemented method, apparatus, and a system for managing instructions. A load/store unit receives a first instruction at a port. The load/store unit rejects the first instruction in response to determining that the first instruction has a first reject condition. Then, the instruction sequencing unit activates a first bit in response to the load/store unit rejection the first instruction. The instruction sequencing unit blocks the first instruction from reissue while the first bit is activated. The processor unit determines a class of rejection of the first instruction. The instruction sequencing unit starts a timer. The length of the timer is based on the class of rejection of the first instruction. The instruction sequencing unit resets the first bit in response to the timer expiring. The instruction sequencing unit allows the first instruction to become eligible for reissue in response to resetting the first bit.
摘要翻译：本文描述的说明性实施例提供了一种计算机实现的方法，装置和用于管理指令的系统。加载/存储单元在端口接收第一条指令。响应于确定第一指令具有第一拒绝条件，加载/存储单元拒绝第一指令。然后，指令排序单元响应于加载/存储单元来激活第一位以拒绝第一指令。当第一位被激活时，指令排序单元阻止重新发行的第一条指令。处理器单元确定第一指令的拒绝类。指令排序单元启动定时器。定时器的长度取决于第一条指令的拒绝类型。指令排序单元重置响应定时器超时的第一位。响应于重置第一位，指令排序单元允许第一指令变得有资格重新发行。

7. 发明申请

US20120210328A1 Guarded, Multi-Metric Resource Control for Safe and Efficient Microprocessor Management 失效
标题翻译：保护，多度量资源控制安全高效的微处理器管理
公开(公告)号：US20120210328A1
公开(公告)日：2012-08-16
申请号：US13024781
申请日：2011-02-10
申请人： Pradip Bose , Alper Buyuktosunoglu , Niti Madan
发明人： Pradip Bose , Alper Buyuktosunoglu , Niti Madan
IPC分类号： G06F9/50
CPC分类号： G06F11/3058 , G06F1/3206 , G06F1/3234 , G06F9/5094 , Y02D10/22
摘要： A mechanism is provided for guarded, multi-metric resource control. Monitoring is performed for an intended action to address a negative condition from a resource manager in a plurality of resource managers in the data processing system. Responsive to receiving the intended action, a determination is made as to whether the intended action will cause an additional negative condition within the data processing system. Responsive to determining that the intended action will cause the additional negative condition within the data processing system, at least one alternative action is identified to be implemented in the data processing system that addresses the negative condition while not causing any additional negative condition. The at least one alternative action is then implemented in the data processing system.
摘要翻译：提供了一种用于保护的多度量资源控制的机制。执行针对数据处理系统中的多个资源管理器中的资源管理器处理负面条件的预期动作的监视。响应于接收预期的动作，确定预期动作是否将在数据处理系统内引起额外的负面情况。响应于确定预期动作将导致数据处理系统内的附加负面条件，至少一个备选动作被识别为在不引起任何附加负面条件的情况下处理负条件的数据处理系统中实现。然后在数据处理系统中实现至少一个备选动作。

8. 发明授权

US08219833B2 Two-level guarded predictive power gating 有权
标题翻译：两级守卫预测能力门控
公开(公告)号：US08219833B2
公开(公告)日：2012-07-10
申请号：US12539941
申请日：2009-08-12
申请人： Jayanta Basak , Pradip Bose , Alper Buyuktosunoglu , Anita Lungu
发明人： Jayanta Basak , Pradip Bose , Alper Buyuktosunoglu , Anita Lungu
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F11/3466 , Y02D10/34
摘要： A mechanism is provided for two-level guarded predictive power gating of a set of units within the data processing system. A success determines whether a unit within the set of units is power gated during a monitoring interval. If the unit is power gated, the success monitor determines whether a count of idle cycles for the unit is below a breakeven point. If the count is above the breakeven point, the success monitor increments a success efficiency counter. If the count is below the breakeven point, the success monitor determines whether the unit needs to be woke up. If the unit needs to be woke up, the success monitor increments a harmful efficiency counter. If the value of the harmful efficiency counter is less than the value from the success efficiency counter, the success monitor enables power gating for the unit via a first-level power-gating mechanism.
摘要翻译：提供了一种用于数据处理系统内的一组单元的两级保护预测能力门控的机制。一个成功的确定在一个监视间隔期间该单元组内的一个单元是否电源门控。如果该单元是电源门控，则成功监视器确定该单元的空闲周期计数是否低于盈亏平衡点。如果计数高于盈亏平衡点，则成功监视器会增加成功效率计数器。如果计数低于盈亏平衡点，则成功监视器确定该单元是否需要醒来。如果单位需要醒来，成功监测器会增加一个有害的效率计数器。如果有害效率计数器的值小于成功效率计数器的值，则成功监视器可通过一级电源门控机构对单元进行功率门控。

9. 发明授权

US08156287B2 Adaptive data prefetch 失效
标题翻译：自适应数据预取
公开(公告)号：US08156287B2
公开(公告)日：2012-04-10
申请号：US12354219
申请日：2009-01-15
申请人： Pradip Bose , Alper Buyuktosunoglu , Miles Robert Dooley , Michael Stephen Floyd , David Scott Ray , Bruce Joseph Ronchetti
发明人： Pradip Bose , Alper Buyuktosunoglu , Miles Robert Dooley , Michael Stephen Floyd , David Scott Ray , Bruce Joseph Ronchetti
IPC分类号： G06F13/00 , G06F1/00
CPC分类号： G06F12/0862 , G06F1/3203 , G06F12/0897 , G06F2212/6022
摘要： A data processing system includes a processor, a unit that includes a multi-level cache, a prefetch system and a memory. The data processing system can operate in a first mode and a second mode. The prefetch system can change behavior in response to a desired power consumption policy set by an external agent or automatically via hardware based on on-chip power/performance thresholds.
摘要翻译：数据处理系统包括处理器，包括多级缓存，预取系统和存储器的单元。数据处理系统可以在第一模式和第二模式中操作。预取系统可以响应于由外部代理设置的所需功耗策略或基于片上功率/性能阈值的硬件自动地改变行为。

10. 发明申请

US20120054528A1 METHOD AND SYSTEM FOR CONTROLLING POWER IN A CHIP THROUGH A POWER-PERFORMANCE MONITOR AND CONTROL UNIT 有权
标题翻译：通过功率性能监视器和控制单元控制芯片中的功率的方法和系统
公开(公告)号：US20120054528A1
公开(公告)日：2012-03-01
申请号：US13292712
申请日：2011-11-09
申请人： PRADIP BOSE , Alper Buyuktosunoglu , Chen-Yong Cher , Prabhakar N. Kudva
发明人： PRADIP BOSE , Alper Buyuktosunoglu , Chen-Yong Cher , Prabhakar N. Kudva
IPC分类号： G06F1/00 , G06F11/30
CPC分类号： G06F1/206 , G06F1/3203 , Y02D10/16
摘要： A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要翻译：用于控制微处理器系统中的功率和性能的系统和方法包括集成到微处理器系统中的监视和控制系统。监视和控制系统包括具有多个层的层次结构。层次结构中的每层都响应来自更高级别的命令，并且命令提供关于操作和功率分配的指令，使得较高级别提供操作模式和预算以降低级别，并且较低级别向较高级别提供反馈在全球和本地控制和管理微处理器系统中的电力使用。

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