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    • 3. 发明授权
    • Vertical quadruple conduction channel insulated gate transistor
    • 垂直四通导通绝缘栅晶体管
    • US08679903B2
    • 2014-03-25
    • US11829514
    • 2007-07-27
    • Richard A. Blanchard
    • Richard A. Blanchard
    • H01L21/00H01L21/84H01L21/8238
    • H01L21/26533H01L21/76243H01L29/4238H01L29/66666H01L29/7827H01L29/7831H01L29/78642
    • A method is provided for fabricating a vertical insulated gate transistor. A horizontal isolation region is formed in a substrate to separate and electrically isolate upper and lower portions of the substrate. A vertical semiconductor pillar with one or more flanks and a cavity is formed so as to rest on the upper portion, and a dielectrically isolated gate is formed so as to include an internal portion within the cavity and an external portion resting on the flanks and on the upper portion. One or more internal walls of the cavity are coated with an isolating layer and the cavity is filled with a gate material so as to form the internal portion of the gate within the cavity and the external portion of the gate that rests on the flanks, and to form two connecting semiconductor regions extending between source and drain regions of the transistor.
    • 提供一种用于制造垂直绝缘栅极晶体管的方法。 在衬底中形成水平隔离区以分离和电隔离衬底的上部和下部。 形成具有一个或多个侧面和空腔的垂直半导体柱,以便搁置在上部上,并且形成介电隔离的栅极,以便在空腔内包括内部部分,并且将外部部分搁置在侧面上, 上部分。 空腔的一个或多个内壁涂覆有隔离层,并且空腔填充有栅极材料,以便形成位于空腔内的栅极的内部部分和搁置在侧面上的栅极的外部部分,以及 以形成在晶体管的源极和漏极区之间延伸的两个连接半导体区域。
    • 10. 发明授权
    • Power semiconductor device having a voltage sustaining layer with a terraced trench formation of floating islands
    • 功率半导体器件具有具有形成浮岛的梯形沟槽形式的电压维持层
    • US08049271B2
    • 2011-11-01
    • US12772258
    • 2010-05-03
    • Richard A. BlanchardJean-Michel Guillot
    • Richard A. BlanchardJean-Michel Guillot
    • H01L29/78
    • H01L29/7802H01L29/0623H01L29/0634H01L29/66272H01L29/66348H01L29/66712H01L29/66734H01L29/7813
    • A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region. A filler material is deposited in the terraced trench to substantially fill the trench, thus completing the voltage sustaining region. At least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.
    • 提供了形成功率半导体器件的方法。 该方法开始于提供第二导电类型的衬底,然后在衬底上形成电压维持区域。 通过在衬底上沉积第一导电类型的外延层并在外延层中形成至少一个梯形沟槽形成电压维持区。 梯形沟槽具有多个宽度不同的部分,以在其间限定至少一个环形凸缘。 阻挡材料沿着沟槽的壁沉积。 通过阻挡材料注入第二导电类型的掺杂剂,所述阻挡材料衬在环形凸缘和所述沟槽底部并进入外延层的相邻部分。 掺杂剂扩散以在外延层中形成至少一个环形掺杂区域和位于环形掺杂区域下方的至少一个其它区域。 填充材料沉积在梯形沟槽中以基本上填充沟槽,从而完成电压维持区域。 在电压维持区域上形成第二导电类型的至少一个区域以限定它们之间的接合。