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1. 发明授权

US08193565B2 Multi-level lateral floating coupled capacitor transistor structures 有权
标题翻译：多电平横向浮动耦合电容晶体管结构
公开(公告)号：US08193565B2
公开(公告)日：2012-06-05
申请号：US12426004
申请日：2009-04-17
申请人： Robert Kuo-Chang Yang , Muhammed Ayman Shibib , Richard A. Blanchard
发明人： Robert Kuo-Chang Yang , Muhammed Ayman Shibib , Richard A. Blanchard
IPC分类号： H01L29/66
CPC分类号： H01L29/0847 , H01L27/0733 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/407 , H01L29/7835
摘要： A semiconductor device includes a source region, a drain region, a gate region, and a drift region. The drift region further includes an active drift region and inactive floating charge control (FCC) regions. The active drift region conducts current between the source region and the drain region when voltage is applied to the gate region. The inactive FCC regions, which field-shape the active drift region to improve breakdown voltage, are vertically stacked in the drift region and are separated by the active drift region. Vertically stacking the inactive FCC regions reduce on-resistance while maintaining higher breakdown voltages.
摘要翻译：半导体器件包括源极区，漏极区，栅极区和漂移区。漂移区域还包括有源漂移区域和无效浮动充电控制（FCC）区域。当电压施加到栅极区域时，有源漂移区域在源极区域和漏极区域之间导通电流。场地形成有源漂移区域以改善击穿电压的无活性FCC区域被垂直地堆叠在漂移区域中并且被有源漂移区域分离。垂直堆叠不活动的FCC区域可以降低导通电阻，同时保持更高的击穿电压。

2. 发明申请

US20120211834A1 MULTI-LEVEL LATERAL FLOATING COUPLED CAPACITOR TRANSISTOR STRUCTURES 有权
标题翻译：多级横向浮动耦合电容器晶体管结构
公开(公告)号：US20120211834A1
公开(公告)日：2012-08-23
申请号：US13461646
申请日：2012-05-01
申请人： Robert Kuo-Chang Yang , Muhammed Ayman Shibib , Richard A. Blanchard
发明人： Robert Kuo-Chang Yang , Muhammed Ayman Shibib , Richard A. Blanchard
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L27/0733 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/407 , H01L29/7835
摘要： A semiconductor device includes an active region having a first floating charge control structure and a termination region having a second floating charge control structure. The second floating charge control structure is at least twice as long as the first floating control structure.
摘要翻译：半导体器件包括具有第一浮动电荷控制结构的有源区和具有第二浮置电荷控制结构的端接区。第二浮动充电控制结构至少是第一浮动控制结构的两倍。

3. 发明申请

US20100123171A1 Multi-level Lateral Floating Coupled Capacitor Transistor Structures 有权
标题翻译：多级横向浮动耦合电容晶体管结构
公开(公告)号：US20100123171A1
公开(公告)日：2010-05-20
申请号：US12426004
申请日：2009-04-17
申请人： Robert Kuo-Chang Yang , Muhammed Ayman Shibib , Richard A. Blanchard
发明人： Robert Kuo-Chang Yang , Muhammed Ayman Shibib , Richard A. Blanchard
IPC分类号： H01L27/06
CPC分类号： H01L29/0847 , H01L27/0733 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/407 , H01L29/7835
摘要： A semiconductor device includes a source region, a drain region, a gate region, and a drift region. The drift region further includes an active drift region and inactive floating charge control (FCC) regions. The active drift region conducts current between the source region and the drain region when voltage is applied to the gate region. The inactive FCC regions, which field-shape the active drift region to improve breakdown voltage, are vertically stacked in the drift region and are separated by the active drift region. Vertically stacking the inactive FCC regions reduce on-resistance while maintaining higher breakdown voltages.
摘要翻译：半导体器件包括源极区，漏极区，栅极区和漂移区。漂移区域还包括有源漂移区域和无效浮动充电控制（FCC）区域。当电压施加到栅极区域时，有源漂移区域在源极区域和漏极区域之间导通电流。场地形成有源漂移区域以改善击穿电压的无活性FCC区域被垂直地堆叠在漂移区域中并且被有源漂移区域分离。垂直堆叠不活动的FCC区域可以降低导通电阻，同时保持更高的击穿电压。

4. 发明授权

US08580644B2 Multi-level lateral floating coupled capacitor transistor structures 有权
标题翻译：多电平横向浮动耦合电容晶体管结构
公开(公告)号：US08580644B2
公开(公告)日：2013-11-12
申请号：US13461646
申请日：2012-05-01
申请人： Robert Kuo-Chang Yang , Muhammed Ayman Shibib , Richard A. Blanchard
发明人： Robert Kuo-Chang Yang , Muhammed Ayman Shibib , Richard A. Blanchard
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L29/0847 , H01L27/0733 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/407 , H01L29/7835
摘要： A semiconductor device includes an active region having a first floating charge control structure and a termination region having a second floating charge control structure. The second floating charge control structure is at least twice as long as the first floating control structure.
摘要翻译：半导体器件包括具有第一浮动电荷控制结构的有源区和具有第二浮置电荷控制结构的端接区。第二浮动充电控制结构至少是第一浮动控制结构的两倍。

5. 发明申请

US20080296636A1 Devices and integrated circuits including lateral floating capacitively coupled structures 审中-公开
标题翻译：器件和集成电路包括横向浮动电容耦合结构
公开(公告)号：US20080296636A1
公开(公告)日：2008-12-04
申请号：US12156670
申请日：2008-06-02
申请人： Mohamed N. Darwish , Richard A. Harris , Muhammed Ayman Shibib , Andrew J. Morrish , Robert Kuo-Chang Yang
发明人： Mohamed N. Darwish , Richard A. Harris , Muhammed Ayman Shibib , Andrew J. Morrish , Robert Kuo-Chang Yang
IPC分类号： H01L29/808 , H01L21/28 , H01L29/06
CPC分类号： H01L29/7835 , H01L21/765 , H01L21/823481 , H01L27/0266 , H01L27/0629 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/407 , H01L29/808
摘要： According to the present invention, semiconductor device breakdown voltage can be increased by embedding field shaping regions within a drift region of the semiconductor device. A controllable current path extends between two device terminals on the top surface of a planar substrate, and the controllable current path includes the drift region. Each field shaping region includes two or more electrically conductive regions that are electrically insulated from each other, and which are capacitively coupled to each other to form a voltage divider dividing a potential between the first and second terminals. One or more of the electrically conductive regions are isolated from any external electrical contact. Such field shaping regions can provide enhanced electric field uniformity in current-carrying parts of the drift region, thereby increasing device breakdown voltage. Further aspects of the invention relate to device integration, efficient fabrication of field shaping regions and device isolation features using the same mask for both, and improved device structures.
摘要翻译：根据本发明，可以通过在半导体器件的漂移区域内嵌入场成形区域来增加半导体器件击穿电压。可控电流路径在平面基板的顶表面上的两个器件端子之间延伸，并且可控电流路径包括漂移区域。每个场整形区域包括彼此电绝缘并且彼此电容耦合以形成分压第一和第二端子之间的电势的分压器的两个或更多个导电区域。一个或多个导电区域与任何外部电触点隔离。这种场成形区域可以在漂移区域的载流部分中提供增强的电场均匀性，从而增加器件击穿电压。本发明的其它方面涉及器件集成，场成形区域的有效制造和使用相同掩模的器件隔离特征和改进的器件结构。

6. 发明授权

US07297606B2 Metal-oxide-semiconductor device including a buried lightly-doped drain region 有权
标题翻译：金属氧化物半导体器件包括埋入的轻掺杂漏极区域
公开(公告)号：US07297606B2
公开(公告)日：2007-11-20
申请号：US11116903
申请日：2005-04-28
申请人： Muhammed Ayman Shibib , Shuming Xu
发明人： Muhammed Ayman Shibib , Shuming Xu
IPC分类号： H01L21/336
CPC分类号： H01L29/402 , H01L29/0615 , H01L29/0847 , H01L29/0873 , H01L29/4175 , H01L29/66659 , H01L29/7835
摘要： An MOS device includes a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed in the semiconductor layer, and a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions. The MOS device further includes a buried LDD region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being spaced laterally from the drain region, and a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer. The second LDD region is self-aligned with the gate and spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.
摘要翻译： MOS器件包括形成在半导体层中的第一导电类型的半导体层，第二导电类型的源极区和形成在半导体层中并与源极区隔开的第二导电类型的漏极区。栅极形成在半导体层的上表面附近，并且至少部分地在源区和漏区之间形成。 MOS器件还包括形成在栅极和漏极区域之间的半导体层中的第二导电类型的埋入LDD区域，所述掩埋LDD区域与漏极区域横向间隔开，并且形成第一导电类型的第二LDD区域在掩埋的LDD区域中并且靠近半导体层的上表面。第二LDD区域与栅极自对准并且与栅极横向隔开，使得栅极相对于第二LDD区域不重叠。

7. 发明授权

US07190563B2 Electrostatic discharge protection in a semiconductor device 有权
标题翻译：半导体器件中的静电放电保护
公开(公告)号：US07190563B2
公开(公告)日：2007-03-13
申请号：US10403570
申请日：2003-03-31
申请人： Muhammed Ayman Shibib
发明人： Muhammed Ayman Shibib
IPC分类号： H02H3/22
CPC分类号： H01L27/0266
摘要： An electrostatic discharge (ESD) protection circuit for protecting a circuit from an ESD event, the ESD protection circuit comprises a metal-oxide semiconductor (MOS) device including a gate terminal, a first source/drain terminal, a second source/drain terminal and a bulk terminal, the bulk and first source/drain terminals being operatively coupled across the circuit to be protected, the gate and second source/drain terminals being coupled together; and a voltage generation circuit coupled between the bulk and gate terminals of the MOS device. The voltage generation circuit is configured to generate a voltage difference between the bulk and gate terminals of the MOS device during at least a portion of the ESD event. In this manner, a current handling capability of the MOS device is increased, thereby advantageously enabling a smaller sized device having a significantly smaller capacitance associated therewith to be employed in the ESD protection circuit.
摘要翻译：一种用于保护电路免受ESD事件的静电放电（ESD）保护电路，ESD保护电路包括金属氧化物半导体（MOS）器件，其包括栅极端子，第一源极/漏极端子，第二源极/漏极端子和体积端子，体积和第一源极/漏极端子可操作地耦合在待保护的电路上，栅极和第二源极/漏极端子耦合在一起; 以及耦合在MOS器件的体栅极和栅极端子之间的电压产生电路。电压产生电路被配置为在ESD事件的至少一部分期间产生MOS器件的体栅极和栅极端子之间的电压差。以这种方式，增加了MOS器件的电流处理能力，从而有利地使得能够在ESD保护电路中采用具有与其相关的显着更小的电容的较小尺寸的器件。

8. 发明授权

US06576506B2 Electrostatic discharge protection in double diffused MOS transistors 有权
公开(公告)号：US06576506B2
公开(公告)日：2003-06-10
申请号：US09896669
申请日：2001-06-29
申请人： Muhammed Ayman Shibib
发明人： Muhammed Ayman Shibib
IPC分类号： H01L21336
CPC分类号： H01L27/0255 , Y10S438/983
摘要： The specification describes a DMOS transistor that is fully integrated with an electrostatic protection diode (ESD). The ESD diode is isolated from the DMOS device by a trench. The trench is metallized to tie the guard ring of the ESD to the substrate thereby increasing the current handling capabilities of the ESD. The trench also provides a convenient buried contact to the RF ground.

9. 发明授权

US06013934A Semiconductor structure for thermal shutdown protection 失效
标题翻译：用于热关断保护的半导体结构
公开(公告)号：US06013934A
公开(公告)日：2000-01-11
申请号：US819828
申请日：1997-03-18
申请人： Milton Luther Embree , Muhammed Ayman Shibib
发明人： Milton Luther Embree , Muhammed Ayman Shibib
IPC分类号： H01L27/02 , H01L29/78 , H02H9/02
CPC分类号： H01L29/7824 , H01L27/0248
摘要： A semiconductor structure having a temperature sensor placed in close proximity to gate and source and/or drain electrodes. The sensor is compatible with conventional semiconductor processing and is typically made from doped polysilicon having a large temperature coefficient of resistivity. At least one sensor may be placed under, but insulated from, source or drain electrodes to protect against high electric fields. The sensor is also compatible with bipolar semiconductor structures.
摘要翻译：具有放置在栅极和源极和/或漏极附近的温度传感器的半导体结构。该传感器与传统的半导体处理兼容，并且通常由具有大的电阻温度系数的掺杂多晶硅制成。至少一个传感器可以放置在源电极或漏电极之下但与之隔绝，以防止高电场。传感器也兼容双极半导体结构。

10. 发明授权

US5773338A Bipolar transistor with MOS-controlled protection for reverse-biased emitter-based junction 失效
标题翻译：具有MOS控制保护的双极晶体管，用于反向偏置发射极基结
公开(公告)号：US5773338A
公开(公告)日：1998-06-30
申请号：US562235
申请日：1995-11-21
申请人： Muhammed Ayman Shibib
发明人： Muhammed Ayman Shibib
IPC分类号： H01L27/02 , H01L29/73 , H01L29/72
CPC分类号： H01L27/0248 , H01L29/7302
摘要： A bipolar transistor with MOS-controlled protection for a reverse-biased emitter-base junction is disclosed. A bipolar transistor and a MOS transistor are configured with the drain and the gate electrically coupled to the emitter, and the source and body electrically coupled to the base. A reverse-bias at the emitter-base junction, which is less than a breakdown voltage for the emitter-base junction, activates the MOS transistor which substantially reduces the resistance between the emitter and the base. Preferably, a first semiconductor region provides both the drain and the emitter, and a second semiconductor region provides both the body and the base, for reduced surface area on an integrated circuit chip.
摘要翻译：公开了一种具有用于反向偏置发射极 - 基极结的MOS控制保护的双极晶体管。双极晶体管和MOS晶体管被配置为具有电耦合到发射极的漏极和栅极，并且源极和主体电耦合到基极。在发射极 - 基极结处的反向偏压小于发射极 - 基极结的击穿电压，激活MOS晶体管，其大大降低了发射极和基极之间的电阻。优选地，第一半导体区域提供漏极和发射极两者，并且第二半导体区域提供主体和基极，以减小集成电路芯片上的表面积。

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