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1. 发明授权

US06583016B1 Doped spacer liner for improved transistor performance 有权
标题翻译：掺杂间隔衬垫，用于改善晶体管性能
公开(公告)号：US06583016B1
公开(公告)日：2003-06-24
申请号：US10105522
申请日：2002-03-26
申请人： Andy C. Wei , Mark B. Fuselier , Ping-Chin Yeh
发明人： Andy C. Wei , Mark B. Fuselier , Ping-Chin Yeh
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L21/265 , H01L21/2652 , H01L29/6656 , H01L29/6659 , H01L29/66659 , H01L29/78603 , H01L29/78624
摘要： Semiconductor devices with improved transistor performance are fabricated by ion-implanting a dopant into the oxide liner to prevent or substantially reduce dopant out-diffusion from the shallow source/drain extensions. Embodiments include ion implanting a P-type dopant, such as B or BF2, using the gate electrode as a mask, to form shallow source/drain extensions, depositing a conformal oxide liner, and ion implanting the P-type impurity into the oxide liner at substantially the same dopant concentration as in the shallow source/drain extensions. Subsequent processing includes depositing a spacer layer, etching to form sidewall spacers, ion implanting to form deep moderate or heavy source/drain implants and activation annealing.
摘要翻译：具有改善的晶体管性能的半导体器件通过将掺杂剂离子注入到氧化物衬垫中来制造，以防止或基本上减少来自浅源极/漏极延伸部的掺杂剂扩散。实施例包括使用栅电极作为掩模离子注入诸如B或BF 2的P型掺杂剂，以形成浅源极/漏极延伸部，沉积共形氧化物衬垫，以及将P型杂质注入氧化物衬垫在与浅源极/漏极延伸部分基本上相同的掺杂剂浓度下。随后的处理包括沉积间隔层，蚀刻以形成侧壁间隔物，离子注入以形成深度中等或重的源/漏植入物和活化退火。

2. 发明授权

US07432136B2 Transistors with controllable threshold voltages, and various methods of making and operating same 失效
标题翻译：具有可控阈值电压的晶体管，以及制作和操作相同的各种方法
公开(公告)号：US07432136B2
公开(公告)日：2008-10-07
申请号：US10140441
申请日：2002-05-06
申请人： Mark B. Fuselier , Derick J. Wristers , Andy C. Wei
发明人： Mark B. Fuselier , Derick J. Wristers , Andy C. Wei
IPC分类号： H01L21/00 , H01L21/8238 , H01L21/336
CPC分类号： H01L29/78648 , H01L29/78603 , H01L29/78606 , H01L29/78609
摘要： In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, the active layer being doped with a first type of dopant material, the bulk substrate having an inner well formed therein adjacent a surface of the bulk substrate and under the active layer, the inner well being doped with the first type of dopant material, forming a transistor above the SOI substrate in an area above the inner well and applying a voltage to the inner well to vary a threshold voltage of the transistor. In some embodiments, the method further comprises forming an NMOS transistor, wherein the active layer and the inner well are doped with a P-type dopant material. In other embodiments, the method further comprises forming a PMOS transistor, wherein the active layer and the inner well are doped with an N-type dopant material. In another illustrative embodiment, the method comprises providing a consumer product comprised of at least one integrated circuit product, the integrated circuit product being comprised of at least one transistor formed in an active layer of an SOI substrate, the SOI substrate further comprising an inner well formed adjacent a surface of a bulk substrate of the SOI substrate, the inner well being formed under the active layer, the active layer and the inner well being doped with a first type of dopant material, sensing an activity level of the integrated circuit product and applying a voltage of a magnitude and a polarity to the inner well of at least one transistor, the magnitude and polarity of the applied voltage being determined based upon the sensed activity level of the integrated circuit product.
摘要翻译：在一个说明性实施例中，该方法包括提供由有源层，掩埋绝缘层和体基板构成的SOI衬底，所述有源层掺杂有第一类型的掺杂剂材料，所述主体衬底具有形成在其中的内阱所述体衬底的表面并且在所述有源层下方，所述内阱掺杂有所述第一类型的掺杂剂材料，在所述内阱上方的区域中在所述SOI衬底上方形成晶体管，并向所述内阱施加电压以改变晶体管的阈值电压。在一些实施例中，该方法还包括形成NMOS晶体管，其中有源层和内阱掺杂有P型掺杂剂材料。在其他实施例中，该方法还包括形成PMOS晶体管，其中有源层和内阱掺杂有N型掺杂剂材料。在另一说明性实施例中，该方法包括提供由至少一个集成电路产品组成的消费产品，所述集成电路产品由形成在SOI衬底的有源层中的至少一个晶体管组成，所述SOI衬底还包括内部阱形成在所述SOI衬底的本体衬底的表面附近，所述内阱形成在所述有源层下方，所述有源层和所述内阱掺杂有第一类型的掺杂剂材料，感测所述集成电路产品的活动水平，以及对至少一个晶体管的内部阱施加大小和极性的电压，所施加的电压的大小和极性基于感测到的集成电路产品的活动水平来确定。

3. 发明授权

US07544999B2 SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate 有权
标题翻译： SOI半导体器件在体硅衬底中具有增强的自对准电介质区域
公开(公告)号：US07544999B2
公开(公告)日：2009-06-09
申请号：US11072661
申请日：2005-03-04
申请人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
发明人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
IPC分类号： H01L27/12
CPC分类号： H01L29/66772 , H01L29/78603
摘要： In one illustrative embodiment, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, and forming a plurality of dielectric regions in the bulk substrate after the gate electrode is formed, the dielectric regions being self-aligned with respect to the gate electrode, the dielectric regions having a dielectric constant that is less than a dielectric constant of the bulk substrate. In further embodiments, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, performing at least one oxygen implant process after the gate electrode and the protective layer are formed to introduce oxygen atoms into the bulk substrate to thereby form a plurality of oxygen-doped regions in the bulk substrate, and performing at least one anneal process to convert the oxygen-doped regions to dielectric regions comprised of silicon dioxide in the bulk substrate. In one illustrative embodiment, the device comprises a gate electrode formed above an SOI structure comprised of a bulk substrate, a buried insulation layer, and an active layer, and a plurality of dielectric regions comprised of silicon dioxide formed in the bulk substrate, the dielectric regions being self-aligned with respect to the gate electrode.
摘要翻译：在一个说明性实施例中，该方法包括在由大量衬底，掩埋绝缘层和有源层组成的SOI衬底之上形成栅电极，该栅电极具有形成在其上的保护层，并且在该衬底中形成多个电介质区域在栅电极形成之后，电介质区域相对于栅电极自对准，介质区域的介电常数小于体基板的介电常数。在另外的实施例中，该方法包括在由大量衬底，掩埋绝缘层和有源层组成的SOI衬底之上形成栅电极，栅极具有形成在其上的保护层，在栅极之后执行至少一个氧注入工艺形成电极和保护层，以将氧原子引入本体衬底中，从而在本体衬底中形成多个氧掺杂区域，并且执行至少一个退火工艺以将氧掺杂区域转换成由硅构成的电介质区域散装衬底中的二氧化物。在一个说明性实施例中，该器件包括形成在SOI结构之上的栅电极，该SOI结构包括体衬底，掩埋绝缘层和有源层，以及由形成在本体衬底中的二氧化硅构成的多个电介质区域，区域相对于栅电极自对准。

4. 发明授权

US07129142B2 Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same 有权
公开(公告)号：US07129142B2
公开(公告)日：2006-10-31
申请号：US10167184
申请日：2002-06-11
申请人： Derick J. Wristers , Andy C. Wei , Mark B. Fuselier
发明人： Derick J. Wristers , Andy C. Wei , Mark B. Fuselier
IPC分类号： H01L21/336
CPC分类号： H01L27/1203 , H01L21/84
摘要： In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, forming a doped region in the bulk substrate under the active layer, forming a plurality of transistors above the SOI substrate in an area above the doped region and applying a voltage to the doped region to vary a threshold voltage of at least one of the plurality of transistors. In another illustrative embodiment, the method comprises providing a consumer product comprised of at least one integrated circuit product, the integrated circuit product being comprised of a plurality of transistors formed in an active layer of an SOI substrate above a doped region formed in a bulk substrate of the SOI substrate, the doped region being formed under the active layer, sensing an activity level of the integrated circuit product and applying a voltage of a magnitude and a polarity to the doped region, the magnitude and polarity of the applied voltage being determined based upon the sensed activity level of the integrated circuit product.

5. 发明授权

US07180136B2 Biased, triple-well fully depleted SOI structure 有权
公开(公告)号：US07180136B2
公开(公告)日：2007-02-20
申请号：US11111409
申请日：2005-04-21
申请人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
发明人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
IPC分类号： H01L27/01
CPC分类号： H01L29/78648 , H01L29/78603 , H01L29/78606 , H01L29/78609
摘要： In one illustrative embodiment, the device comprises a transistor formed above a silicon-on-insulator substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the bulk substrate being doped with a first type of dopant material and a first well formed in the bulk substrate, the first well being doped with a second type of dopant material that is of a type opposite the first type of dopant material. The device further comprises a second well formed in the bulk substrate within the first well, the second well being doped with a dopant material that is the same type as the first type of dopant material, the transistor being formed in the active layer above the second well, an electrical contact for the first well and an electrical contact for said second well. In one illustrative embodiment, a method of forming a transistor above a silicon-on-insulator substrate comprised of a bulk substrate, a buried oxide layer and an active layer, the bulk substrate being doped with a first type of dopant material is disclosed. The method comprises performing a first ion implant process using a dopant material that is of a type opposite the first type of dopant material to form a first well region within the bulk substrate, performing a second ion implant process using a dopant material that is the same type as the first type of dopant material to form a second well region in the bulk substrate within the first well, the transistor being formed in the active layer above the second well, forming a conductive contact to the first well and forming a conductive contact to the second well. The method further comprises a contact well formed in the bulk substrate within the first well, the contact well being comprised of a dopant material that is of the same type as the second type of dopant material, the contact well within the first well having a dopant concentration that is greater than a dopant concentration of the first well.

6. 发明授权

US06780686B2 Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions 有权
标题翻译：用于完全耗尽的SOI结构的掺杂方法，以及包含所得掺杂区的器件
公开(公告)号：US06780686B2
公开(公告)日：2004-08-24
申请号：US10104319
申请日：2002-03-21
申请人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
发明人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
IPC分类号： H01L21339
CPC分类号： H01L29/66772 , H01L29/78609 , H01L2924/0002 , H01L2924/00
摘要： The present invention is generally directed to doping methods for fully-depleted SOI structures, and a device comprising such resulting doped regions. In one illustrative embodiment, the device comprises a transistor formed above a silicon-on-insulator substrate comprised of a bulk substrate, a buried oxide layer and an active layer, the transistor being comprised of a gate electrode, the bulk substrate being doped with a dopant material at a first concentration level. The device further comprises a first doped region formed in the bulk substrate, the first doped region being doped with a dopant material that is the same type as the bulk substrate dopant material, wherein the concentration level of dopant material in the first doped region is greater than the first dopant concentration level in the bulk substrate, the first doped region being substantially aligned with the gate electrode.
摘要翻译：本发明一般涉及用于完全耗尽的SOI结构的掺杂方法，以及包括这样得到的掺杂区的器件。在一个说明性实施例中，该器件包括形成在绝缘体上硅衬底上的晶体管，该晶体管由体衬底，掩埋氧化物层和有源层组成，该晶体管由栅电极组成，该体衬底掺杂有掺杂剂材料在第一浓度水平。该器件还包括形成在本体衬底中的第一掺杂区域，该第一掺杂区域掺杂与本体衬底掺杂剂材料相同类型的掺杂剂材料，其中第一掺杂区域中掺杂剂材料的浓度水平较大比第一掺杂浓度水平高的第一掺杂浓度水平，第一掺杂区域基本上与栅电极对准。

7. 发明授权

US06876037B2 Fully-depleted SOI device 有权
标题翻译：全耗尽的SOI器件
公开(公告)号：US06876037B2
公开(公告)日：2005-04-05
申请号：US10796731
申请日：2004-03-09
申请人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
发明人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
IPC分类号： H01L27/12 , H01L21/336 , H01L29/786 , H01L27/01
CPC分类号： H01L29/66772 , H01L29/78609 , H01L2924/0002 , H01L2924/00
摘要： The present invention is generally directed to a fully-depleted SOI device structure. In one illustrative embodiment, the device comprises first, second and third doped regions formed in the bulk substrate, wherein the dopant concentration level in the doped regions is greater than the dopant concentration in the bulk substrate. The first doped region is substantially aligned with the gate electrode of the device, while the second and third doped regions are vertically spaced apart from the first doped region.
摘要翻译：本发明一般涉及一种完全耗尽的SOI器件结构。在一个说明性实施例中，该器件包括形成在本体衬底中的第一，第二和第三掺杂区域，其中掺杂区域中的掺杂剂浓度水平大于本体衬底中的掺杂剂浓度。第一掺杂区域基本上与器件的栅电极对准，而第二和第三掺杂区域与第一掺杂区域垂直间隔开。

8. 发明授权

US07335568B2 Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same 有权
标题翻译：在SOI衬底的本体衬底中形成掺杂区域以控制形成在其上的晶体管的操作特性的方法，以及包括其的集成电路器件
公开(公告)号：US07335568B2
公开(公告)日：2008-02-26
申请号：US11533460
申请日：2006-09-20
申请人： Derick J. Wristers , Andy C. Wei , Mark B. Fuselier
发明人： Derick J. Wristers , Andy C. Wei , Mark B. Fuselier
IPC分类号： H01L21/336
CPC分类号： H01L27/1203 , H01L21/84
摘要： In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, forming a doped region in the bulk substrate under the active layer, forming a plurality of transistors above the SOI substrate in an area above the doped region and applying a voltage to the doped region to vary a threshold voltage of at least one of the plurality of transistors. In another illustrative embodiment, the method comprises providing a consumer product comprised of at least one integrated circuit product, the integrated circuit product being comprised of a plurality of transistors formed in an active layer of an SOI substrate above a doped region formed in a bulk substrate of the SOI substrate, the doped region being formed under the active layer, sensing an activity level of the integrated circuit product and applying a voltage of a magnitude and a polarity to the doped region, the magnitude and polarity of the applied voltage being determined based upon the sensed activity level of the integrated circuit product.
摘要翻译：在一个说明性实施例中，该方法包括提供由有源层，掩埋绝缘层和体基板组成的SOI衬底，在有源层下方的本体衬底中形成掺杂区域，在SOI衬底上方形成多个晶体管在所述掺杂区域之上的区域，并且向所述掺杂区域施加电压以改变所述多个晶体管中的至少一个晶体管的阈值电压。在另一个说明性实施例中，该方法包括提供由至少一个集成电路产品组成的消费产品，该集成电路产品由多个晶体管组成，该多个晶体管形成在形成于本体衬底中的掺杂区域上的SOI衬底的有源层中的SOI衬底，所述掺杂区域形成在有源层下方，感测所述集成电路产品的活动电平并且向所述掺杂区域施加幅度和极性的电压，所述施加电压的幅度和极性基于根据感测到的集成电路产品的活动水平。

9. 发明授权

US06919236B2 Biased, triple-well fully depleted SOI structure, and various methods of making and operating same 有权
标题翻译：偏置，三阱全耗尽的SOI结构，以及各种制作和操作方法
公开(公告)号：US06919236B2
公开(公告)日：2005-07-19
申请号：US10104939
申请日：2002-03-21
申请人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
发明人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
IPC分类号： H01L27/08 , H01L21/8238 , H01L27/092 , H01L29/786 , H01L21/00
CPC分类号： H01L29/78648 , H01L29/78603 , H01L29/78606 , H01L29/78609
摘要： In one example, a method of forming a transistor above a silicon-on-insulator substrate comprised of a bulk substrate, a buried oxide layer and an active layer, the bulk substrate being doped with a first type of dopant material is disclosed. The method comprises performing a first ion implant process using a dopant material that is of a type opposite the first type of dopant material to form a first well region within the bulk substrate, performing a second ion implant process using a dopant material that is the same type as the first type of dopant material to form a second well region in the bulk substrate within the first well, the transistor being formed in the active layer above the second well, forming a conductive contact to the first well and forming a conductive contact to the second well.
摘要翻译：在一个示例中，公开了一种在绝缘体上硅衬底上形成晶体管的方法，该衬底由体衬底，埋氧层和有源层组成，所述体衬底掺杂有第一类掺杂剂材料。该方法包括使用与第一类型的掺杂剂材料相反的类型的掺杂剂材料来执行第一离子注入工艺，以在本体衬底内形成第一阱区域，使用相同的掺杂剂材料执行第二离子注入工艺作为第一类型的掺杂剂材料形成在第一阱内的体衬底中的第二阱区，晶体管形成在第二阱上方的有源层中，形成与第一阱的导电接触并形成导电接触第二口

10. 发明授权

US06884702B2 Method of making an SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate 失效
标题翻译：制造在本体硅衬底中具有增强的自对准电介质区域的SOI半导体器件的方法
公开(公告)号：US06884702B2
公开(公告)日：2005-04-26
申请号：US10162299
申请日：2002-06-04
申请人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
发明人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
IPC分类号： H01L21/76 , H01L21/02 , H01L21/336 , H01L21/762 , H01L27/12 , H01L29/786 , H01L21/425
CPC分类号： H01L29/66772 , H01L29/78603
摘要： In one illustrative embodiment, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, and forming a plurality of dielectric regions in the bulk substrate after the gate electrode is formed, the dielectric regions being self-aligned with respect to the gate electrode, the dielectric regions having a dielectric constant that is less than a dielectric constant of the bulk substrate. In further embodiments, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, performing at least one oxygen implant process after the gate electrode and the protective layer are formed to introduce oxygen atoms into the bulk substrate to thereby form a plurality of oxygen-doped regions in the bulk substrate, and performing at least one anneal process to convert the oxygen-doped regions to dielectric regions comprised of silicon dioxide in the bulk substrate. In one illustrative embodiment, the device comprises a gate electrode formed above an SOI structure comprised of a bulk substrate, a buried insulation layer, and an active layer, and a plurality of dielectric regions comprised of silicon dioxide formed in the bulk substrate, the dielectric regions being self-aligned with respect to the gate electrode.
摘要翻译：在一个说明性实施例中，该方法包括在由大量衬底，掩埋绝缘层和有源层组成的SOI衬底之上形成栅电极，该栅电极具有形成在其上的保护层，并且在该衬底中形成多个电介质区域在栅电极形成之后，电介质区域相对于栅电极自对准，介质区域的介电常数小于体基板的介电常数。在另外的实施例中，该方法包括在由大量衬底，掩埋绝缘层和有源层组成的SOI衬底之上形成栅电极，栅极具有形成在其上的保护层，在栅极之后执行至少一个氧注入工艺形成电极和保护层，以将氧原子引入本体衬底中，从而在本体衬底中形成多个氧掺杂区域，并且执行至少一个退火工艺以将氧掺杂区域转换成由硅构成的电介质区域散装衬底中的二氧化物。在一个说明性实施例中，该器件包括形成在SOI结构之上的栅电极，该SOI结构包括体衬底，掩埋绝缘层和有源层，以及由形成在本体衬底中的二氧化硅构成的多个电介质区域，区域相对于栅电极自对准。

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