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1. 发明申请

US20040196899A1 Method and arrangement for a power amplifier 失效
标题翻译：功率放大器的方法和布置
公开(公告)号：US20040196899A1
公开(公告)日：2004-10-07
申请号：US10492524
申请日：2004-04-14
发明人： Shu-Ang Zhou , Michael Faulkner
IPC分类号： H03K007/08
CPC分类号： H04B1/0483 , H03F1/32 , H03F2200/331
摘要： The present invention relates to an arrangement and a method for amplifying high frequency RF signals having amplitude and phase variations. The objective problem of the present invention is to provide an efficient power amplifier for amplifying high frequency RF signals. The object is achieved by introducing a Signal Conditioning Device (SCD) that converts baseband signals SI and SQ into tri-states signals STI, STQ. The tri-states signals STI, STQ are time multiplexed, which results in that a single power amplifier can be used to amplify the signal on the In-phase (I) channel and the signal on the Quadrature (Q) channel. Hence, the present invention does not require a power combiner.
摘要翻译：本发明涉及放大具有振幅和相位变化的高频RF信号的装置和方法。本发明的客观问题是提供一种用于放大高频RF信号的高效功率放大器。该目的通过引入将基带信号SI和SQ转换为三态信号STI，STQ的信号调节装置（SCD）来实现。三态信号STI，STQ被时分复用，这导致单个功率放大器可用于放大同相（I）信道上的信号和正交（Q）信道上的信号。因此，本发明不需要功率组合器。

2. 发明申请

US20040108913A1 Robust fractional clock-based pulse generator for digital pulse width modulator 有权
$Robust fractional clock-based pulse generator for digital pulse width modulator$
标题翻译：用于数字脉宽调制器的鲁棒分数时钟脉冲发生器
公开(公告)号：US20040108913A1
公开(公告)日：2004-06-10
申请号：US10315836
申请日：2002-12-10
申请人： Intersil Americas Inc.
发明人： Lawrence G. Pearce , William David Bartlett
IPC分类号： H03K007/08
CPC分类号： H03L7/0805 , H03K5/06 , H03K7/08 , H03L7/0812
摘要： A tapped delay line generates a fractional clock pulse signal for controlling a PWM pulse generator, such as used in a DC-DC converter. Operational parameters of the tapped delay are adjusted to maintain a desired fractional precision of the duty-cycle of the PWM clock pulse signal. In a first, phase locked loop (PLL) based embodiment, the tapped delay line-based digital PWM pulse generator includes a compensating phase locked-loop formed around an auxiliary tapped delay line that implements the voltage controlled oscillator of the PLL. In a second embodiment, the PWM pulse generator is configured as an nullopen-loopnull tapped delay line phase detector architecture, which avoids having to correlate parameters of the PLL delay line with those of the PWM delay line.
摘要翻译：抽头延迟线产生用于控制PWM脉冲发生器的分数时钟脉冲信号，例如在DC-DC转换器中使用的。调整抽头延迟的操作参数以保持PWM时钟脉冲信号占空比的期望分数精度。在基于锁相环（PLL）的第一实施例中，基于抽头的延迟线数字PWM脉冲发生器包括一个形成在辅助抽头延迟线周围的补偿锁相环，该延迟线实现PLL的压控振荡器。在第二实施例中，PWM脉冲发生器被配置为“开环”抽头延迟线相位检测器架构，避免了将PLL延迟线的参数与PWM延迟线的参数相关联。

3. 发明申请

US20030076880A1 Method and circuit for controlling switching frequency signal 失效
标题翻译：控制开关频率信号的方法和电路
公开(公告)号：US20030076880A1
公开(公告)日：2003-04-24
申请号：US10271337
申请日：2002-10-15
发明人： Pei Pei Yang , Darcherng Su , Ko-Chin Wang
IPC分类号： H03K007/08
CPC分类号： H03K7/08 , H02M3/156
摘要： A method and a circuit for controlling a switching frequency signal used in a direct current to direct current (DC to DC) converter are proposed. The DC to DC converter generates an output voltage to drive a system. The switching frequency signal is generated by inputting a modulation frequency to a pulse width modulation (PWM) circuit. The method includes steps of: 1. generating a control signal from the system to stop the pulse width modulation (PWM) circuit to generate the switching frequency signal when a signal is received by the system; and 2. restarting the pulse width modulation (PWM) circuit to generate the switching frequency signal in order to increase the output voltage to drive the system when the output voltage from the DC to DC converter is under a predetermined voltage.
摘要翻译：提出了一种用于控制直流到直流（DC-DC）转换器中使用的开关频率信号的方法和电路。 DC到DC转换器产生驱动系统的输出电压。通过将调制频率输入到脉宽调制（PWM）电路来产生开关频率信号。该方法包括以下步骤：1.当系统接收到信号时，产生来自系统的控制信号以停止脉宽调制（PWM）电路以产生开关频率信号; 以及2.当DC-DC转换器的输出电压低于预定电压时，重启脉冲宽度调制（PWM）电路以产生开关频率信号，以增加输出电压以驱动系统。

4. 发明申请

US20030062964A1 Sigma-delta pulse-width-modulated signal generator circuit 有权
标题翻译： Sigma-delta脉冲宽度调制信号发生器电路
公开(公告)号：US20030062964A1
公开(公告)日：2003-04-03
申请号：US10232954
申请日：2002-08-29
申请人： STMicroelectronics S.A.
发明人： Yannick Guedon , Philippe Maige
IPC分类号： H03K007/08
CPC分类号： H03K7/08 , H03K5/26 , H03L7/099 , H03L2207/06
摘要： A circuit for generating a pulse-width-modulated signal comprises a phase-locked loop (PLL) having a duty-cycle-insensitive phase comparator and a Sigma-Delta pulse width modulation circuit suitable for providing the voltage-controlled oscillator function of the PLL. Thereby, frequency of the signal generated is synchronized by the PLL to the specified frequency of a synchronization signal, and is thus independent of the duty cycle.
摘要翻译：用于产生脉宽调制信号的电路包括具有占空比不敏感相位比较器和适用于提供PLL的压控振荡器功能的Σ-Δ脉宽调制电路的锁相环（PLL）。因此，所生成的信号的频率由PLL同步到同步信号的指定频率，因此与占空比无关。

5. 发明申请

US20030016064A1 Device and method for calibrating the pulse duration of a signal source 有权
标题翻译：用于校准信号源的脉冲持续时间的装置和方法
公开(公告)号：US20030016064A1
公开(公告)日：2003-01-23
申请号：US10186596
申请日：2002-07-01
发明人： Udo Hartmann , Gunnar Krause
IPC分类号： H03K003/017 , H03K005/04 , H03K007/08 , G01R035/00
CPC分类号： H03K5/04 , H03K5/082 , H03K5/1565
摘要： An apparatus for calibrating the pulse duration of an output signal of a signal source may be used, in particular, for measuring and setting a duty cycle of a signal output from the signal source. The apparatus includes a comparator having a first input, a second input and an output. A reference voltage supply is provided, which is connected to the first input of the comparator. A charge storing capacitor, the charge state of which is adjustable as a function of the pulse duration of the output signal of the signal source, is connected to the second input of the comparator. Finally, the apparatus includes a processor for setting the pulse duration as a function of the comparison signal output at the output of the comparator. The apparatus for signal calibration allows an on-chip calibration and renders complicated external calibration systems superfluous.
摘要翻译：可以使用用于校准信号源的输出信号的脉冲持续时间的装置，特别是用于测量和设置从信号源输出的信号的占空比。该装置包括具有第一输入，第二输入和输出的比较器。提供参考电压源，其连接到比较器的第一输入端。充电状态可以根据信号源的输出信号的脉冲持续时间调节的电荷存储电容器连接到比较器的第二输入端。最后，该装置包括一个处理器，用于根据在比较器的输出处输出的比较信号设置脉冲持续时间。用于信号校准的设备允许进行片上校准，并使复杂的外部校准系统成为多余的。

6. 发明申请

US20020180545A1 Processor with pulse width modulation generator with fault input prioritization 有权
标题翻译：具有脉冲宽度调制发生器的处理器，具有故障输入优先级
公开(公告)号：US20020180545A1
公开(公告)日：2002-12-05
申请号：US09870650
申请日：2001-06-01
发明人： Stephen A. Bowling
IPC分类号： H03K007/08
CPC分类号： H02P27/08 , G05B2219/34217
摘要： A processor that has pulse width modulation generation circuitry that provides an improved capability to deal with fault conditions, and particularly with multiple concurrent fault conditions, occurring in external circuitry and devices that are connected to PWM hardware included in a processor. A pulse width modulation generator for a processor includes fault priority circuitry having a plurality of fault inputs operable to receive fault input signals and a fault output operable to output a fault output signal, the fault priority circuitry operable to receive fault input signals on a plurality of fault inputs concurrently, and output a fault output signal corresponding to a fault input having a highest priority among the fault inputs that are receiving fault input signals, and pulse width modulation circuitry having at least one pulse width modulation output operable to output at least one pulse width modulated signal and a fault input operable to receive the fault output signal from the fault priority circuitry, the pulse width modulation circuitry operable to drive the pulse width modulation output to a defined state associated with the selected fault input.
摘要翻译：具有脉冲宽度调制生成电路的处理器，其提供改进的处理故障状况的能力，特别是与外部电路和连接到处理器中的PWM硬件的设备相关的多个并发故障条件。用于处理器的脉宽调制发生器包括具有可操作以接收故障输入信号的多个故障输入的故障优先电路和可操作以输出故障输出信号的故障输出，所述故障优先电路可操作以在多个故障输入信号上接收故障输入信号同时输出故障输入信号，并输出对应于正在接收故障输入信号的故障输入中具有最高优先级的故障输入的故障输出信号，以及具有至少一个脉冲宽度调制输出的脉宽调制电路，其可操作以输出至少一个脉冲宽度调制信号和可操作以从故障优先电路接收故障输出信号的故障输入，脉宽调制电路可操作以将脉宽调制输出驱动到与选定故障输入相关联的限定状态。

7. 发明申请

US20020167370A1 Microcontroller available for remote transmission 失效
标题翻译：微控制器可用于远程传输
公开(公告)号：US20020167370A1
公开(公告)日：2002-11-14
申请号：US10082102
申请日：2002-02-26
发明人： Yia-Min Jue , Wen-Yuh Shieh
IPC分类号： H03K007/08
CPC分类号： H04B10/503
摘要： The present invention is related to an improved architecture of an integrated circuit with remote transmission function. For no additional carrier circuit is needed, for example in a preferred embodiment, an infrared signal is served as the medium for remote transmission to connect with other interfaces, so as for integration design of the infrared transmission arrangement and the integrated circuit, thereby saving elements in hardware design and the time and costs for design, and improving the working efficiency. Furthermore, a multiplexer receives a select control signal to control the output type, so as for the pin of the integrated circuit for remote transmission applicable for general input/output port in other situations in addition to the infrared transmission.
摘要翻译：本发明涉及具有远程传输功能的集成电路的改进架构。为了不需要额外的载波电路，例如在优选实施例中，红外信号被用作用于远程传输的介质以与其他接口连接，以便用于红外传输装置和集成电路的集成设计，从而节省元件在硬件设计和设计的时间和成本上，提高工作效率。此外，多路复用器接收选择控制信号以控制输出类型，以及除了红外线传输之外的其它情况下，用于远程传输的集成电路的引脚适用于一般输入/输出端口。

8. 发明申请

US20020114386A1 Fractional N synthesizer with reduced fractionalization spurs 有权
$Fractional N synthesizer with reduced fractionalization spurs$
标题翻译：分数N合成器具有减少的分数杂散
公开(公告)号：US20020114386A1
公开(公告)日：2002-08-22
申请号：US09790445
申请日：2001-02-21
发明人： Anders Eklof
IPC分类号： H03B021/00 , H03K007/08 , H03K009/08 , H03D003/24
CPC分类号： H03L7/1976 , H03B21/00 , H03K9/08 , H03L7/091
摘要： A fractional N synthesizer is disclosed. The synthesizer includes a phase detector that receives first and second input signals and generates a pulse width modulated (PWM) output signal having a pulse width indicative of the phase relationship between the input signals. A pulse-width-to-amplitude (PW/A) conversion circuit connected to a loop filter where the conversion circuit receives the phase detector output signal and generates a PW/A output signal having an amplitude indicative of the phase detector output signal pulse width. The phase detector output signal may comprise a periodic series of pulses having varying pulse widths and the PW/A output signal amplitude changes at the end of each pulse to reflect the corresponding pulse width. The conversion circuit may include a current circuit connected to a capacitor, where the current signal receives the phase detector output and sources a constant current during a charging phase of the phase detector output signal.
摘要翻译：公开了一种分数N合成器。合成器包括相位检测器，其接收第一和第二输入信号并产生具有指示输入信号之间的相位关系的脉冲宽度的脉宽调制（PWM）输出信号。连接到环路滤波器的脉冲宽度到幅度（PW / A）转换电路，其中转换电路接收相位检测器输出信号并产生具有指示相位检测器输出信号脉冲宽度的幅度的PW / A输出信号。相位检测器输出信号可以包括具有变化的脉冲宽度的脉冲的周期性脉冲串，并且PW / A输出信号幅度在每个脉冲结束时变化以反映相应的脉冲宽度。转换电路可以包括连接到电容器的电流电路，其中电流信号接收相位检测器输出并且在相位检测器输出信号的充电阶段期间发出恒定电流。

9. 发明申请

US20020093391A1 Pulse width modulation method, pulse width modulator and power converter 有权
标题翻译：脉宽调制方式，脉宽调制器和功率转换器
公开(公告)号：US20020093391A1
公开(公告)日：2002-07-18
申请号：US09941873
申请日：2001-08-30
发明人： Seiji Ishida , Keijiro Sakai , Toshiaki Okuyama , Hiroshi Fujii , Hiroyuki Tomita , Tatsuo Ando , Yuhachi Takakura , Hideo Kimura
IPC分类号： H03K007/08
CPC分类号： H03K7/08 , H02M7/53871
摘要： In detecting an output current of a power converter based on a DC current Idc of the power converter, the pulse width of the DC current Idc becomes narrower when the pulse width of a line voltage is narrower, and its detection becomes difficult. A voltage command correction unit 9 according to the present invention corrects voltage commands such that pulse width of a line voltage becomes zero when the pulse width of the line voltage is less than the minimum pulse width, not to output a line pulse, and an error generated by the correction is integrated. This integrated error is added to the line voltage in the next time, and the integrated pulse width of the line voltage is outputted when the pulse width becomes larger than or equal to the minimum pulse width.
摘要翻译：在基于功率转换器的直流电流Idc来检测功率转换器的输出电流时，当线电压的脉冲宽度变窄时，直流电流Idc的脉冲宽度变窄，其检测变得困难。根据本发明的电压指令校正单元9校正电压指令，使得当线电压的脉冲宽度小于最小脉冲宽度时线路电压的脉冲宽度变为零，不输出线路脉冲和误差由校正产生的是整合。在下一次将该积分误差加到线电压上，当脉冲宽度大于或等于最小脉冲宽度时，输出线电压的积分脉冲宽度。

10. 发明申请

US20020013935A1 Programmable logic controller method, system and apparatus 有权
标题翻译：可编程逻辑控制器方法，系统和设备
公开(公告)号：US20020013935A1
公开(公告)日：2002-01-31
申请号：US09732571
申请日：2000-12-08
申请人： Siemens Aktiengesellschaft
发明人： Mark Steven Boggs , Temple L. Fulton , Steve Hausman , Gary McNabb , Alan McNutt , Steven W. Stimmel
IPC分类号： G06F009/44 , G06F013/00 , H03K007/08 , H03M013/00
CPC分类号： G06F11/3636 , G05B19/056 , G06F1/025
摘要： A programmable logic controller with enhanced and extended the capabilities. A digital input filter implement filters with considerable less logic by simulating the action of a capacitor being driven by a constant current source whose output voltage is sensed by a comparator with a large amount of hysterisis. A pulse catch circuit captures the input pulse even though the update occurs between scan cycles. A pulse output controller includes a hardware pipeline mechanism to allow for smooth, hardware-controlled transitions from wave-form to wave-form. A free port link allows the user to control the port either manually or by operation of a user program. In order to provide higher performance for communication using PPI protocol, the PLC includes a built-in protocol. An n-bit modem protocol ensures data integrity without use of a parity type data integrity system. A hide instruction protects proprietary software by encrypting the sensitive code and decrypting the code during compilation and, thereafter, re-encrypting the code. A system function call allows the user to create and/or download new PLC functions and implement them as PLC operating system functions. An STL status function debugs programs during run-time and while the program is executing. A micro PLC arrangement provides compact size and efficiency.
摘要翻译：可编程逻辑控制器，具有增强和扩展能力。数字输入滤波器通过模拟由恒定电流源驱动的电容器的动作来实现具有相当少的逻辑的滤波器，其输出电压由具有大量滞后的比较器感测。即使在扫描周期之间进行更新，脉冲捕捉电路捕获输入脉冲。脉冲输出控制器包括硬件流水线机制，以允许从波形到波形的平滑的，硬件控制的转换。自由端口链接允许用户手动或通过用户程序的操作来控制端口。为了提供使用PPI协议的通信的更高性能，PLC包括内置协议。 n位调制解调器协议确保数据完整性，而不使用奇偶校验类型数据完整性系统。隐藏指令通过加密敏感代码并在编译期间解密代码，然后重新加密代码来保护专有软件。系统功能调用允许用户创建和/或下载新的PLC功能，并将其实现为PLC操作系统功能。 STL状态功能在运行时和程序执行期间调试程序。微型PLC布局提供了紧凑的尺寸和效率。

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