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1. 发明申请

US20060189049A1 Four-transistor Schmitt trigger inverter 有权
标题翻译：四晶体管施密特触发器
公开(公告)号：US20060189049A1
公开(公告)日：2006-08-24
申请号：US11408220
申请日：2006-04-20
申请人： Themistokles Afentakis , Apostolos Voutsas , Paul Schuele
发明人： Themistokles Afentakis , Apostolos Voutsas , Paul Schuele
IPC分类号： H01L21/84 , H01L29/94
CPC分类号： H03K3/3565 , H01L29/78624 , H01L29/78642 , H01L29/78648
摘要： A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.
摘要翻译：提供了一个四晶体管施密特触发器。施密特触发逆变器由n沟道MOS（NMOS）双栅极薄膜晶体管（DG-TFT）和p沟道MOS（PMOS）DG-TFT制成，两个DG-TFT都具有顶栅极，背栅极和源极/漏极区域。（常规）NMOS TFT具有连接到NMOS DG-TFT第一S / D区和PMOS DG-TFT第一S / D区的栅极。 NMOS TFT还具有连接到NMOS DG-TFT背栅和PMOS DG-TFT后栅的第一S / D区。（传统）PMOS TFT具有连接到NMOS TFT栅极的栅极和连接到NMOS TFT第一S / D区域的第一S / D区域。

2. 发明申请

US20060066512A1 Dual-gate transistor display 有权
公开(公告)号：US20060066512A1
公开(公告)日：2006-03-30
申请号：US11184699
申请日：2005-07-18
申请人： Themistokles Afentakis , Apostolos Voutsas , Paul Schuele
发明人： Themistokles Afentakis , Apostolos Voutsas , Paul Schuele
IPC分类号： G09G3/20
CPC分类号： G09G3/20 , G09G3/3208 , G09G3/3659 , G09G2300/08 , G09G2310/0262 , H01L29/78648
摘要： A dual-gate thin-film transistor (DG-TFT) voltage storage circuit is provided. The circuit includes a voltage storage element, a DG-TFT having a first source/drain (S/D) connected to a data line, a top gate connected to a first gate line, a second S/D region connected to the voltage storage element, and a bottom gate connected to a bias line. In one aspect, the circuit further includes a voltage shifter having an input connected to the first gate line and an output to supply a bias voltage on the bias line. Examples of a voltage storage element include a capacitor, a liquid crystal (LC) pixel, and a light emitting diode (LED) pixel.

3. 发明申请

US20060049461A1 Thin-film transistor with vertical channel region 有权
标题翻译：具有垂直沟道区域的薄膜晶体管
公开(公告)号：US20060049461A1
公开(公告)日：2006-03-09
申请号：US11261194
申请日：2005-10-28
申请人： Paul Schuele , Apostolos Voutsas
发明人： Paul Schuele , Apostolos Voutsas
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L27/12 , H01L29/78624 , H01L29/78642 , H01L29/78648 , H01L29/78675
摘要： A vertical thin-film transistor (V-TFT) is provided along with a method for forming the V-TFT. The method comprises: providing a substrate made from a material such as Si, quartz, glass, or plastic; conformally depositing an insulating layer overlying the substrate; forming a gate, having sidewalls and a thickness, overlying a substrate insulation layer; forming a gate oxide layer overlying the gate sidewalls, and a gate insulation layer overlying the gate top surface; etching the exposed substrate insulation layer; forming a first source/drain region overlying the gate insulation layer; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall with a channel length about equal to the thickness of the gate, interposed between the first and second source/drain regions.
摘要翻译：提供垂直薄膜晶体管（V-TFT）以及用于形成V-TFT的方法。该方法包括：提供由诸如Si，石英，玻璃或塑料的材料制成的衬底; 保形地沉积覆盖衬底的绝缘层; 形成具有覆盖衬底绝缘层的侧壁和厚度的栅极; 形成覆盖所述栅极侧壁的栅极氧化层，以及覆盖所述栅极顶表面的栅极绝缘层; 蚀刻暴露的基板绝缘层; 形成覆盖所述栅极绝缘层的第一源极/漏极区域; 在第一栅极侧壁附近形成覆盖衬底绝缘层的第二源极/漏极区域; 并且在第一和第二源极/漏极区域之间形成沟槽区域，该沟道区域覆盖具有大约等于栅极厚度的沟道长度的第一栅极侧壁。

4. 发明申请

US20050236671A1 Multi-planar layout vertical thin-film transistor inverter 失效
标题翻译：多平面布局立式薄膜晶体管逆变器
公开(公告)号：US20050236671A1
公开(公告)日：2005-10-27
申请号：US10862761
申请日：2004-06-07
申请人： Paul Schuele , Apostolos Voutsas
发明人： Paul Schuele , Apostolos Voutsas
IPC分类号： H01L29/10 , H01L29/76 , H01L29/786
CPC分类号： H01L27/12 , H01L29/78624 , H01L29/78642 , H01L29/78648 , H01L29/78675
摘要： A vertical thin-film transistor (V-TFT) inverter circuit and a method for forming a multi-planar layout TFT inverter circuit have been provided. The method comprising: forming a P-channel TFT with a gate, a first source/drain (S/D) region in a first horizontal plane, and a second S/D region in a second horizontal plane, different than the first horizontal plane; and, forming an N-channel TFT, adjacent the P-channel TFT, with a gate, a third S/D region in a third horizontal plane, and a fourth S/D region in the second horizontal plane, different than the third horizontal plane. Forming a P-channel TFT includes forming a P-channel top-drain vertical TFT (TDV-TFT), and forming an N-channel TFT includes forming an N-channel TDV-TFT.
摘要翻译：已经提供了垂直薄膜晶体管（V-TFT）逆变器电路和用于形成多平面布局TFT反相器电路的方法。该方法包括：形成具有栅极的P沟道TFT，第一水平面中的第一源极/漏极（S / D）区域和与第一水平面不同的第二水平面中的第二S / D区域 ; 以及在第三水平面上形成与P沟道TFT相邻的N沟道TFT，第三水平面中的第三S / D区和第二水平面中的第四S / D区，与第三水平面不同飞机形成P沟道TFT包括形成P沟道顶漏垂直TFT（TDV-TFT），并且形成N沟道TFT包括形成N沟道TDV-TFT。

5. 发明授权

US5955758A Method of forming a capacitor plate and a capacitor incorporating same 失效
标题翻译：形成电容器板的方法和结合其的电容器
公开(公告)号：US5955758A
公开(公告)日：1999-09-21
申请号：US738789
申请日：1996-10-29
申请人： Gurtej S. Sandhu , Paul Schuele , Wayne Kinney
发明人： Gurtej S. Sandhu , Paul Schuele , Wayne Kinney
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/108
CPC分类号： H01L27/11502 , H01L27/1085 , H01L27/11507 , H01L28/40 , H01L27/10852
摘要： A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing an electrically conductive first layer over the node; c) providing an electrically insulative barrier second layer over the first conductive layer; d) providing a third layer over the electrically insulative barrier layer, the third layer comprising a material which is either electrically conductive and resistant to oxidation, or forms an electrically conductive material upon oxidation; e) providing an insulating inorganic metal oxide dielectric layer over the electrically conductive third layer; f) providing an electrically conductive fourth layer over the insulating inorganic metal oxide dielectric layer; and g) providing an electrically conductive interconnect to extend over the second insulative layer and electrically interconnect the first and third conductive layers. A capacitor construction having such a dielectric layer in combination with the barrier layer and electrical interconnect of a first capacitor plate is disclosed.
摘要翻译：形成电容器的方法包括：a）提供与电容器进行电连接的节点; b）在节点上提供导电的第一层; c）在所述第一导电层之上提供电绝缘阻挡层第二层; d）在电绝缘阻挡层上提供第三层，第三层包括导电并耐氧化的材料，或者在氧化时形成导电材料; e）在导电的第三层之上提供绝缘的无机金属氧化物介电层; f）在绝缘无机金属氧化物介电层上提供导电第四层; 以及g）提供导电互连以在所述第二绝缘层上延伸并且使所述第一和第三导电层电互连。公开了一种电容器结构，其具有与阻挡层和第一电容器板的电互连结合的这种介电层。

6. 发明申请

US20070278600A1 Piezo-diode cantilever MEMS 有权
标题翻译：压电二极管悬臂MEMS
公开(公告)号：US20070278600A1
公开(公告)日：2007-12-06
申请号：US11717231
申请日：2007-03-13
申请人： Changqing Zhan , Paul Schuele , John Conley , John Hartzell
发明人： Changqing Zhan , Paul Schuele , John Conley , John Hartzell
IPC分类号： H01L29/84 , H01L21/02
CPC分类号： B81B3/0021 , H01L29/868
摘要： A piezo thin-film diode (piezo-diode) cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method deposits thin-films overlying a substrate. The substrate can be made of glass, polymer, quartz, metal foil, Si, sapphire, ceramic, or compound semiconductor materials. Amorphous silicon (a-Si), polycrystalline Si (poly-Si), oxides, a-SiGe, poly-SiGe, metals, metal-containing compounds, nitrides, polymers, ceramic films, magnetic films, and compound semiconductor materials are some examples of thin-film materials. A cantilever beam is formed from the thin-films, and a diode is embedded with the cantilever beam. The diode is made from a thin-film shared in common with the cantilever beam. The shared thin-film may a film overlying a cantilever beam top surface, a thin-film overlying a cantilever beam bottom surface, or a thin-film embedded within the cantilever beam.
摘要翻译：提供压电薄膜二极管（压电二极管）悬臂微机电系统（MEMS）及相关制造工艺。该方法沉积覆盖在基底上的薄膜。基板可以由玻璃，聚合物，石英，金属箔，Si，蓝宝石，陶瓷或化合物半导体材料制成。非晶硅（a-Si），多晶Si（poly-Si），氧化物，a-SiGe，poly-SiGe，金属，含金属的化合物，氮化物，聚合物，陶瓷膜，磁性膜和化合物半导体材料是一些例子的薄膜材料。悬臂梁由薄膜形成，二极管嵌入悬臂梁。二极管由与悬臂梁共用的薄膜制成。共享的薄膜可以是覆盖悬臂梁顶表面的薄膜，覆盖悬臂梁底表面的薄膜或嵌入在悬臂梁内的薄膜。

7. 发明申请

US20070222493A1 Digital-to-time converter 审中-公开
标题翻译：数字时间转换器
公开(公告)号：US20070222493A1
公开(公告)日：2007-09-27
申请号：US11439410
申请日：2006-05-23
申请人： Themistokles Afentakis , Apostolos Voutsas , Paul Schuele
发明人： Themistokles Afentakis , Apostolos Voutsas , Paul Schuele
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00039 , H03K2005/00058
摘要： A digital-to-time converter (DTC) is provided, made from a plurality of series-connected cells. Each cell has an input interface to accept a signal, a control interface to accept a digital command, a delayed signal path, a minimum delay signal path, and an output interface. The signal path is selected in response to the command. The time delay associated with the delayed signal path of each cell can be varied, so that the plurality of series-connected cells is able to provide a large range of delay combinations. For example, if there are n series-connected cells, then the jth series-connected cell, where j varies from 1 to n, conducts the signal through 2j MOS gates in the delayed signal path. Assuming a digital control word with n bit places, the jth series-connected cell accepts the jth bit place of the control word to select a delay path.
摘要翻译：提供了由多个串联连接的单元制成的数字 - 时间转换器（DTC）。每个单元具有接收信号的输入接口，接受数字命令的控制接口，延迟信号路径，最小延迟信号路径和输出接口。响应命令选择信号路径。可以改变与每个单元的延迟信号路径相关联的时间延迟，使得多个串联单元能够提供大范围的延迟组合。例如，如果存在n个串联连接的单元，那么其中j从1变化到n的第j个串联单元通过延迟信号路径中的2个MOS栅极传导信号。假设具有n位位置的数字控制字，第j个串联单元接受控制字的第j位，以选择延迟路径。

8. 发明申请

US20070218622A1 Method of fabricating local interconnects on a silicon-germanium 3D CMOS 有权
标题翻译：在硅 - 锗3D CMOS上制造局部互连的方法
公开(公告)号：US20070218622A1
公开(公告)日：2007-09-20
申请号：US11376542
申请日：2006-03-15
申请人： Jong-Jan Lee , Paul Schuele , Sheng Hsu , Jer-Shen Maa
发明人： Jong-Jan Lee , Paul Schuele , Sheng Hsu , Jer-Shen Maa
IPC分类号： H01L21/8238
CPC分类号： H01L21/823871 , H01L21/02532 , H01L21/02667 , H01L21/28525 , H01L21/76895 , H01L27/11 , H01L27/1108
摘要： A method of fabricating local interconnect on a silicon-germanium 3D CMOS includes fabricating an active silicon CMOS device on a silicon substrate. An insulator layer is deposited on the silicon substrate and a seed window is opened through the insulator layer to the silicon substrate and to a silicon CMOS device gate. A germanium thin film is deposited on the insulator layer and into windows, forming a contact between the germanium thin film and the silicon device. The germanium thin film is encapsulated in a dielectric material. The wafer is heated at a temperature sufficient to flow the germanium, while maintaining the other layers in a solid condition. The wafer is cooled to solidify the germanium as single crystal germanium and as polycrystalline germanium, which provides local interconnects. Germanium CMOS devices may be fabricated on the single crystal germanium thin film.
摘要翻译：在硅 - 锗3D CMOS上制造局部互连的方法包括在硅衬底上制造有源硅CMOS器件。绝缘体层沉积在硅衬底上，并且晶种窗通过绝缘体层向硅衬底和硅CMOS器件栅极打开。在绝缘体层和窗口上沉积锗薄膜，形成锗薄膜和硅器件之间的接触。锗薄膜被封装在电介质材料中。在足以使锗流动的温度下加热晶片，同时将其它层保持在固体状态。将晶片冷却以将锗固化为单晶锗和作为多晶锗，其提供局部互连。可以在单晶锗薄膜上制造锗CMOS器件。

9. 发明申请

US20060068532A1 Dual-gate thin-film transistor 审中-公开
标题翻译：双栅极薄膜晶体管
公开(公告)号：US20060068532A1
公开(公告)日：2006-03-30
申请号：US10953913
申请日：2004-09-28
申请人： Paul Schuele , Apostolos Voutsas
发明人： Paul Schuele , Apostolos Voutsas
IPC分类号： H01L21/84
CPC分类号： G09G3/20 , G09G3/3208 , G09G3/3659 , G09G2300/08 , G09G2310/0262 , H01L29/78648
摘要： A dual-gate thin film transistor (DG-TFT) and associated fabrication method are provided. The method comprises: forming a first (back) gate in a first horizontal plane; forming source/drain (S/D) regions and an intervening channel region in a second horizontal plane, overlying the first plane; and, forming a second (top) gate in a third horizontal plane, overlying the second plane. The S/D regions and intervening channel region have a combined length, smaller than the length of the first gate. A substrate insulating layer is formed over the substrate, made from a material such as SiO2. A first gate insulation layer is formed over the first gate. Amorphous silicon (a-Si) is deposited over the first gate insulation layer and crystallized. The S/D and channel regions are formed from the crystallized Si layer. A second gate oxide layer is formed over the channel region.
摘要翻译：提供了双栅极薄膜晶体管（DG-TFT）和相关制造方法。该方法包括：在第一水平面中形成第一（后）栅极; 在第一平面上形成源极/漏极（S / D）区域和在第二水平面中的中间沟道区域; 并且在第三水平面上形成覆盖第二平面的第二（顶部）门。 S / D区域和中间沟道区域具有小于第一栅极的长度的组合长度。在衬底上形成衬底绝缘层，由诸如SiO 2的材料制成。在第一栅极上形成第一栅极绝缘层。非晶硅（a-Si）沉积在第一栅绝缘层上并结晶。 S / D和沟道区域由结晶的Si层形成。在沟道区上形成第二栅氧化层。

10. 发明授权

US06259125B1 Scalable high dielectric constant capacitor 失效
标题翻译：可伸缩高介电常数电容器
公开(公告)号：US06259125B1
公开(公告)日：2001-07-10
申请号：US09073560
申请日：1998-05-06
申请人： Pierre C. Fazan , Paul Schuele
发明人： Pierre C. Fazan , Paul Schuele
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L28/55 , H01L28/60
摘要： A capacitor for high density DRAM applications comprises a high-∈ capacitor dielectric such as BST or PZT in an arrangement which obviates the need for barrier layers during fabrication. The fabrication process allows for electrode placement by simple sputter deposition and further provides for the possibility of capacitor spacing below that of conventional lithographic techniques.
摘要翻译：用于高密度DRAM应用的电容器包括诸如BST或PZT的高ε电容器电介质，其排列在制造期间不需要阻挡层。制造工艺允许通过简单的溅射沉积进行电极放置，并进一步提供电容器间隔的可能性低于常规光刻技术的可能性。

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