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1. 发明申请

US20060189049A1 Four-transistor Schmitt trigger inverter 有权
标题翻译：四晶体管施密特触发器
公开(公告)号：US20060189049A1
公开(公告)日：2006-08-24
申请号：US11408220
申请日：2006-04-20
申请人： Themistokles Afentakis , Apostolos Voutsas , Paul Schuele
发明人： Themistokles Afentakis , Apostolos Voutsas , Paul Schuele
IPC分类号： H01L21/84 , H01L29/94
CPC分类号： H03K3/3565 , H01L29/78624 , H01L29/78642 , H01L29/78648
摘要： A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.
摘要翻译：提供了一个四晶体管施密特触发器。施密特触发逆变器由n沟道MOS（NMOS）双栅极薄膜晶体管（DG-TFT）和p沟道MOS（PMOS）DG-TFT制成，两个DG-TFT都具有顶栅极，背栅极和源极/漏极区域。（常规）NMOS TFT具有连接到NMOS DG-TFT第一S / D区和PMOS DG-TFT第一S / D区的栅极。 NMOS TFT还具有连接到NMOS DG-TFT背栅和PMOS DG-TFT后栅的第一S / D区。（传统）PMOS TFT具有连接到NMOS TFT栅极的栅极和连接到NMOS TFT第一S / D区域的第一S / D区域。

2. 发明申请

US20060066512A1 Dual-gate transistor display 有权
公开(公告)号：US20060066512A1
公开(公告)日：2006-03-30
申请号：US11184699
申请日：2005-07-18
申请人： Themistokles Afentakis , Apostolos Voutsas , Paul Schuele
发明人： Themistokles Afentakis , Apostolos Voutsas , Paul Schuele
IPC分类号： G09G3/20
CPC分类号： G09G3/20 , G09G3/3208 , G09G3/3659 , G09G2300/08 , G09G2310/0262 , H01L29/78648
摘要： A dual-gate thin-film transistor (DG-TFT) voltage storage circuit is provided. The circuit includes a voltage storage element, a DG-TFT having a first source/drain (S/D) connected to a data line, a top gate connected to a first gate line, a second S/D region connected to the voltage storage element, and a bottom gate connected to a bias line. In one aspect, the circuit further includes a voltage shifter having an input connected to the first gate line and an output to supply a bias voltage on the bias line. Examples of a voltage storage element include a capacitor, a liquid crystal (LC) pixel, and a light emitting diode (LED) pixel.

3. 发明申请

US20060049461A1 Thin-film transistor with vertical channel region 有权
标题翻译：具有垂直沟道区域的薄膜晶体管
公开(公告)号：US20060049461A1
公开(公告)日：2006-03-09
申请号：US11261194
申请日：2005-10-28
申请人： Paul Schuele , Apostolos Voutsas
发明人： Paul Schuele , Apostolos Voutsas
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L27/12 , H01L29/78624 , H01L29/78642 , H01L29/78648 , H01L29/78675
摘要： A vertical thin-film transistor (V-TFT) is provided along with a method for forming the V-TFT. The method comprises: providing a substrate made from a material such as Si, quartz, glass, or plastic; conformally depositing an insulating layer overlying the substrate; forming a gate, having sidewalls and a thickness, overlying a substrate insulation layer; forming a gate oxide layer overlying the gate sidewalls, and a gate insulation layer overlying the gate top surface; etching the exposed substrate insulation layer; forming a first source/drain region overlying the gate insulation layer; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall with a channel length about equal to the thickness of the gate, interposed between the first and second source/drain regions.
摘要翻译：提供垂直薄膜晶体管（V-TFT）以及用于形成V-TFT的方法。该方法包括：提供由诸如Si，石英，玻璃或塑料的材料制成的衬底; 保形地沉积覆盖衬底的绝缘层; 形成具有覆盖衬底绝缘层的侧壁和厚度的栅极; 形成覆盖所述栅极侧壁的栅极氧化层，以及覆盖所述栅极顶表面的栅极绝缘层; 蚀刻暴露的基板绝缘层; 形成覆盖所述栅极绝缘层的第一源极/漏极区域; 在第一栅极侧壁附近形成覆盖衬底绝缘层的第二源极/漏极区域; 并且在第一和第二源极/漏极区域之间形成沟槽区域，该沟道区域覆盖具有大约等于栅极厚度的沟道长度的第一栅极侧壁。

4. 发明申请

US20050236671A1 Multi-planar layout vertical thin-film transistor inverter 失效
标题翻译：多平面布局立式薄膜晶体管逆变器
公开(公告)号：US20050236671A1
公开(公告)日：2005-10-27
申请号：US10862761
申请日：2004-06-07
申请人： Paul Schuele , Apostolos Voutsas
发明人： Paul Schuele , Apostolos Voutsas
IPC分类号： H01L29/10 , H01L29/76 , H01L29/786
CPC分类号： H01L27/12 , H01L29/78624 , H01L29/78642 , H01L29/78648 , H01L29/78675
摘要： A vertical thin-film transistor (V-TFT) inverter circuit and a method for forming a multi-planar layout TFT inverter circuit have been provided. The method comprising: forming a P-channel TFT with a gate, a first source/drain (S/D) region in a first horizontal plane, and a second S/D region in a second horizontal plane, different than the first horizontal plane; and, forming an N-channel TFT, adjacent the P-channel TFT, with a gate, a third S/D region in a third horizontal plane, and a fourth S/D region in the second horizontal plane, different than the third horizontal plane. Forming a P-channel TFT includes forming a P-channel top-drain vertical TFT (TDV-TFT), and forming an N-channel TFT includes forming an N-channel TDV-TFT.
摘要翻译：已经提供了垂直薄膜晶体管（V-TFT）逆变器电路和用于形成多平面布局TFT反相器电路的方法。该方法包括：形成具有栅极的P沟道TFT，第一水平面中的第一源极/漏极（S / D）区域和与第一水平面不同的第二水平面中的第二S / D区域 ; 以及在第三水平面上形成与P沟道TFT相邻的N沟道TFT，第三水平面中的第三S / D区和第二水平面中的第四S / D区，与第三水平面不同飞机形成P沟道TFT包括形成P沟道顶漏垂直TFT（TDV-TFT），并且形成N沟道TFT包括形成N沟道TDV-TFT。

5. 发明申请

US20070222493A1 Digital-to-time converter 审中-公开
标题翻译：数字时间转换器
公开(公告)号：US20070222493A1
公开(公告)日：2007-09-27
申请号：US11439410
申请日：2006-05-23
申请人： Themistokles Afentakis , Apostolos Voutsas , Paul Schuele
发明人： Themistokles Afentakis , Apostolos Voutsas , Paul Schuele
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00039 , H03K2005/00058
摘要： A digital-to-time converter (DTC) is provided, made from a plurality of series-connected cells. Each cell has an input interface to accept a signal, a control interface to accept a digital command, a delayed signal path, a minimum delay signal path, and an output interface. The signal path is selected in response to the command. The time delay associated with the delayed signal path of each cell can be varied, so that the plurality of series-connected cells is able to provide a large range of delay combinations. For example, if there are n series-connected cells, then the jth series-connected cell, where j varies from 1 to n, conducts the signal through 2j MOS gates in the delayed signal path. Assuming a digital control word with n bit places, the jth series-connected cell accepts the jth bit place of the control word to select a delay path.
摘要翻译：提供了由多个串联连接的单元制成的数字 - 时间转换器（DTC）。每个单元具有接收信号的输入接口，接受数字命令的控制接口，延迟信号路径，最小延迟信号路径和输出接口。响应命令选择信号路径。可以改变与每个单元的延迟信号路径相关联的时间延迟，使得多个串联单元能够提供大范围的延迟组合。例如，如果存在n个串联连接的单元，那么其中j从1变化到n的第j个串联单元通过延迟信号路径中的2个MOS栅极传导信号。假设具有n位位置的数字控制字，第j个串联单元接受控制字的第j位，以选择延迟路径。

6. 发明申请

US20060068532A1 Dual-gate thin-film transistor 审中-公开
标题翻译：双栅极薄膜晶体管
公开(公告)号：US20060068532A1
公开(公告)日：2006-03-30
申请号：US10953913
申请日：2004-09-28
申请人： Paul Schuele , Apostolos Voutsas
发明人： Paul Schuele , Apostolos Voutsas
IPC分类号： H01L21/84
CPC分类号： G09G3/20 , G09G3/3208 , G09G3/3659 , G09G2300/08 , G09G2310/0262 , H01L29/78648
摘要： A dual-gate thin film transistor (DG-TFT) and associated fabrication method are provided. The method comprises: forming a first (back) gate in a first horizontal plane; forming source/drain (S/D) regions and an intervening channel region in a second horizontal plane, overlying the first plane; and, forming a second (top) gate in a third horizontal plane, overlying the second plane. The S/D regions and intervening channel region have a combined length, smaller than the length of the first gate. A substrate insulating layer is formed over the substrate, made from a material such as SiO2. A first gate insulation layer is formed over the first gate. Amorphous silicon (a-Si) is deposited over the first gate insulation layer and crystallized. The S/D and channel regions are formed from the crystallized Si layer. A second gate oxide layer is formed over the channel region.
摘要翻译：提供了双栅极薄膜晶体管（DG-TFT）和相关制造方法。该方法包括：在第一水平面中形成第一（后）栅极; 在第一平面上形成源极/漏极（S / D）区域和在第二水平面中的中间沟道区域; 并且在第三水平面上形成覆盖第二平面的第二（顶部）门。 S / D区域和中间沟道区域具有小于第一栅极的长度的组合长度。在衬底上形成衬底绝缘层，由诸如SiO 2的材料制成。在第一栅极上形成第一栅极绝缘层。非晶硅（a-Si）沉积在第一栅绝缘层上并结晶。 S / D和沟道区域由结晶的Si层形成。在沟道区上形成第二栅氧化层。

7. 发明申请

US20070228471A1 Adjacent planar and non-planar thin-film transistor 审中-公开
标题翻译：相邻的平面和非平面薄膜晶体管
公开(公告)号：US20070228471A1
公开(公告)日：2007-10-04
申请号：US11807075
申请日：2007-05-25
申请人： Paul Schuele , Apostolos Voutsas
发明人： Paul Schuele , Apostolos Voutsas
IPC分类号： H01L27/12
CPC分类号： H01L27/12 , H01L29/78624 , H01L29/78642 , H01L29/78648 , H01L29/78675
摘要： A method is provided for concurrently forming MP-TFTs and P-TFTs. Generally, the method comprises: forming a P-TFT having source/drain (S/D) regions, an intervening channel region, and a gate, all in a first horizontal plane; and simultaneously forming a MP-TFT having a first gate in the first horizontal plane and at least one S/D region in a second horizontal plane, overlying the first horizontal plane. The vertical TFT (V-TFT) is an MP-TFT having vertical first gate sidewalls and a vertical channel region overlying a gate sidewall. The dual-gate TFT (DG-TFT) is an MP-TFT having a bottom gate, first and second S/D regions with top surfaces, an intervening channel region with a top surface, and a second, top gate with a bottom surface, all in a second horizontal plane, overlying the first horizontal plane.
摘要翻译：提供了用于同时形成MP-TFT和P-TFT的方法。通常，该方法包括：在第一水平面中形成具有源极/漏极（S / D）区域，中间沟道区域和栅极的P-TFT; 同时在第一水平面上形成具有第一栅极的MP-TFT和位于第一水平面上的第二水平面中的至少一个S / D区域。垂直TFT（V-TFT）是具有垂直的第一栅极侧壁和覆盖栅极侧壁的垂直沟道区的MP-TFT。双栅极TFT（DG-TFT）是具有底栅，具有顶表面的第一和第二S / D区，具有顶表面的中间沟道区和具有底表面的第二顶栅的MP-TFT 都在第二个水平面上，覆盖着第一个水平面。

8. 发明申请

US20060246637A1 Sidewall gate thin-film transistor 审中-公开
标题翻译：侧壁栅极薄膜晶体管
公开(公告)号：US20060246637A1
公开(公告)日：2006-11-02
申请号：US11479221
申请日：2006-06-30
申请人： Apostolos Voutsas , Paul Schuele
发明人： Apostolos Voutsas , Paul Schuele
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L27/1251 , H01L27/1214 , H01L29/6675 , H01L29/78642
摘要： A sidewall gate thin-film transistor (TFT) and associated fabrication method are provided. The method provides a substrate with a surface and forms a surface-normal feature. The surface-normal feature is normal with respect to the substrate surface, with a sidewall made from an electrical insulator. An active silicon (Si) layer is formed overlying the surface-normal feature, with a channel overlying the surface-normal feature sidewall. A gate insulator overlies the channel, and a sidewall gate overlies the gate insulator. More specifically, the gate insulator is formed from conformally depositing an electrical insulator layer overlying the active Si layer. The gate electrode layer is conformally deposited overlying the gate insulator layer and anisotropically etched, leaving a gate electrode sidewall adjacent to the gate insulator layer overlying the channel.
摘要翻译：提供了侧壁栅极薄膜晶体管（TFT）和相关的制造方法。该方法提供具有表面的基底并形成表面法线特征。表面法线特征相对于基底表面是正常的，具有由电绝缘体制成的侧壁。形成覆盖表面法线特征的活性硅（Si）层，覆盖表面法线特征侧壁的沟道。栅极绝缘体覆盖沟道，并且侧壁栅极覆盖栅极绝缘体。更具体地说，栅极绝缘体通过共形沉积覆盖有源Si层的电绝缘体层形成。栅极电极层被共形沉积在栅极绝缘体层上并各向异性蚀刻，留下与栅极绝缘体层相邻的栅电极侧壁。

9. 发明申请

US20060166415A1 Two-transistor tri-state inverter 审中-公开
标题翻译：双晶体三态逆变器
公开(公告)号：US20060166415A1
公开(公告)日：2006-07-27
申请号：US11387626
申请日：2006-03-23
申请人： Themistokles Afentakis , Apostolos Voutsas , Paul Schuele
发明人： Themistokles Afentakis , Apostolos Voutsas , Paul Schuele
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L27/1274 , H01L27/1214 , H01L29/78648 , H01L29/78672
摘要： A two-transistor tri-state inverter is provided, made from a NMOS dual-gate thin-film transistor (DG-TFT) having a top gate, a back gate, and source/drain regions. A PMOS DG-TFT also has a top gate, a back gate, and S/D regions, and the NMOS first S/D region is connected to a PMOS first S/D region. The NMOS top gate is connected to an input signal (Vin), the back gate is connected to a control signal (Vb), the first S/D region supplies an output signal (Vout), and a second S/D region is connected to a reference voltage. The PMOS top gate is connected to the input signal, the back gate is connected to an inverted control signal (−Vb), and a second S/D region is connected to a supply voltage having a higher voltage than the reference voltage.
摘要翻译：提供了由具有顶栅极，后栅极和源极/漏极区域的NMOS双栅极薄膜晶体管（DG-TFT）制成的双晶体管三态反相器。 PMOS DG-TFT还具有顶栅极，背栅极和S / D区域，并且NMOS第一S / D区域连接到PMOS第一S / D区域。 NMOS顶栅连接到输入信号（Vin），背栅极连接到控制信号（Vb），第一S / D区域提供输出信号（Vout），并且第二S / D区域被连接到参考电压。 PMOS顶栅连接到输入信号，后栅连接到反相控制信号（-Vb），第二S / D区连接到具有比参考电压高的电压的电源电压。

10. 发明申请

US20050239238A1 Simultaneous planar and non-planar thin-film transistor processes 失效
标题翻译：同时平面和非平面薄膜晶体管工艺
公开(公告)号：US20050239238A1
公开(公告)日：2005-10-27
申请号：US10985587
申请日：2004-11-09
申请人： Paul Schuele , Apostolos Voutsas
发明人： Paul Schuele , Apostolos Voutsas
IPC分类号： H01L29/10 , H01L29/76 , H01L29/786
CPC分类号： H01L27/12 , H01L29/78624 , H01L29/78642 , H01L29/78648 , H01L29/78675
摘要： A method is provided for concurrently forming MP-TFTs and P-TFTs. Generally, the method comprises: forming a P-TFT having source/drain (S/D) regions, an intervening channel region, and a gate, all in a first horizontal plane; and simultaneously forming a MP-TFT having a first gate in the first horizontal plane and at least one S/D region in a second horizontal plane, overlying the first horizontal plane. The vertical TFT (V-TFT) is an MP-TFT having vertical first gate sidewalls and a vertical channel region overlying a gate sidewall. The dual-gate TFT (DG-TFT) is an MP-TFT having a bottom gate, first and second S/D regions with top surfaces, an intervening channel region with a top surface, and a second, top gate with a bottom surface, all in a second horizontal plane, overlying the first horizontal plane.
摘要翻译：提供了用于同时形成MP-TFT和P-TFT的方法。通常，该方法包括：在第一水平面中形成具有源极/漏极（S / D）区域，中间沟道区域和栅极的P-TFT; 同时在第一水平面上形成具有第一栅极的MP-TFT和位于第一水平面上的第二水平面中的至少一个S / D区域。垂直TFT（V-TFT）是具有垂直的第一栅极侧壁和覆盖栅极侧壁的垂直沟道区的MP-TFT。双栅极TFT（DG-TFT）是具有底栅，具有顶表面的第一和第二S / D区，具有顶表面的中间沟道区和具有底表面的第二顶栅的MP-TFT 都在第二个水平面上，覆盖着第一个水平面。

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