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1. 发明申请

US20130001737A1 SEMICONDUCTOR DEVICES STRUCTURES INCLUDING AN ISOLATION STRUCTURE 失效
标题翻译：半导体器件结构包括隔离结构
公开(公告)号：US20130001737A1
公开(公告)日：2013-01-03
申请号：US13610303
申请日：2012-09-11
申请人： Pai-Hung Pan
发明人： Pai-Hung Pan
IPC分类号： H01L29/06
CPC分类号： H01L21/76224
摘要： A shallow isolation trench structure and methods of forming the same wherein the method of formation comprises a layered structure of a buffer film layer over a dielectric layer that is atop a semiconductor substrate. The buffer film layer comprises a material that is oxidation resistant and can be etched selectively to oxide films. The layered structure is patterned with a resist material and etched to form a shallow trench. A thin oxide layer is formed in the trench and the buffer film layer is selectively etched to move the buffer film layer back from the corners of the trench. An isolation material is then used to fill the shallow trench and the buffer film layer is stripped to form an isolation structure. When the structure is etched by subsequent processing step(s), a capped shallow trench isolation structure that covers the shallow trench corners is created.
摘要翻译：浅隔离沟槽结构及其形成方法，其中形成方法包括在半导体衬底顶上的介电层上的缓冲膜层的分层结构。缓冲膜层包括耐氧化的材料并且可以选择性地蚀刻到氧化物膜上。层状结构用抗蚀剂材料图案化并蚀刻以形成浅沟槽。在沟槽中形成薄的氧化物层，并且选择性地蚀刻缓冲膜层以使缓冲膜层从沟槽的角部移回。然后使用隔离材料填充浅沟槽，剥离缓冲膜层以形成隔离结构。当通过后续处理步骤蚀刻结构时，产生覆盖浅沟槽角的封闭的浅沟槽隔离结构。

2. 发明授权

US08338264B2 Methods for forming isolation structures for semiconductor devices 失效
标题翻译：形成半导体器件隔离结构的方法
公开(公告)号：US08338264B2
公开(公告)日：2012-12-25
申请号：US13023282
申请日：2011-02-08
申请人： Pai-Hung Pan
发明人： Pai-Hung Pan
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： A shallow isolation trench structure and methods of forming the same wherein the method of formation comprises a layered structure of a buffer film layer over a dielectric layer that is atop a semiconductor substrate. The buffer film layer comprises a material that is oxidation resistant and can be etched selectively to oxide films. The layered structure is patterned with a resist material and etched to form a shallow trench. A thin oxide layer is formed in the trench and the buffer film layer is selectively etched to move the buffer film layer back from the corners of the trench. An isolation material is then used to fill the shallow trench and the buffer film layer is stripped to form an isolation structure. When the structure is etched by subsequent processing step(s), a capped shallow trench isolation structure that covers the shallow trench corners is created.
摘要翻译：浅隔离沟槽结构及其形成方法，其中形成方法包括在半导体衬底顶上的介电层上的缓冲膜层的分层结构。缓冲膜层包括耐氧化的材料并且可以选择性地蚀刻到氧化物膜上。层状结构用抗蚀剂材料图案化并蚀刻以形成浅沟槽。在沟槽中形成薄的氧化物层，并且选择性地蚀刻缓冲膜层以使缓冲膜层从沟槽的角部移回。然后使用隔离材料填充浅沟槽，剥离缓冲膜层以形成隔离结构。当通过后续处理步骤蚀刻结构时，产生覆盖浅沟槽角的封闭的浅沟槽隔离结构。

3. 发明授权

US07170139B2 Semiconductor constructions 有权
标题翻译：半导体结构
公开(公告)号：US07170139B2
公开(公告)日：2007-01-30
申请号：US11025142
申请日：2004-12-28
申请人： Pai-Hung Pan
发明人： Pai-Hung Pan
IPC分类号： H01L29/76
CPC分类号： H01L21/28176 , H01L21/28167 , H01L21/28211
摘要： A semiconductor processing method of forming a conductive gate or gate line over a substrate includes, a) forming a conductive gate over a gate dielectric layer on a substrate, the gate having sidewalls and an interface with the gate dielectric layer; b) electrically insulating the gate sidewalls; and c) after electrically insulating the gate sidewalls, exposing the substrate to oxidizing conditions effective to oxidize at least a portion of the gate interface with the gate dielectric layer. According to one aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision of a first insulating material and subsequent anisotropic etch thereof to insulate the gate sidewalls. According to another aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision of first and second insulating materials and subsequent anisotropic etch thereof to insulate the gate sidewalls. According to another aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision and subsequent anisotropic etch of a first insulating material, followed by provision and subsequent anisotropic etch of a second insulating material.
摘要翻译：在衬底上形成导电栅极或栅极线的半导体处理方法包括：a）在衬底上的栅极电介质层上形成导电栅极，所述栅极具有侧壁和与栅极介电层的界面; b）电绝缘栅极侧壁; 以及c）在将所述栅极侧壁电绝缘之后，将所述衬底暴露于有效地氧化与所述栅极介电层的所述栅极界面的至少一部分的氧化条件。根据本发明的一个方面，在提供第一绝缘材料和随后的各向异性蚀刻之后，将衬底暴露于氧化条件下进行步骤，以使栅极侧壁绝缘。根据本发明的另一方面，在提供第一绝缘材料和第二绝缘材料之后进行将衬底暴露于氧化条件的步骤，然后进行其各向异性蚀刻以使栅极侧壁绝缘。根据本发明的另一方面，在提供第一绝缘材料的随后的各向异性蚀刻之后，随后对第二绝缘材料进行随后的各向异性蚀刻，进行将衬底暴露于氧化条件的步骤。

4. 发明授权

US07041548B1 Methods of forming a gate stack that is void of silicon clusters within a metallic silicide film thereof 失效
标题翻译：在其金属硅化物膜内形成无硅团簇的栅叠层的方法
公开(公告)号：US07041548B1
公开(公告)日：2006-05-09
申请号：US09614113
申请日：2000-07-12
申请人： Pai-Hung Pan , Louie Liu , Ravi Iyer
发明人： Pai-Hung Pan , Louie Liu , Ravi Iyer
IPC分类号： H01L21/8238
CPC分类号： H01L21/28052
摘要： A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.
摘要翻译：一种用于形成栅堆叠的方法，其通过在形成期间的温度降低来最小化或消除在栅叠层形成期间对栅介质层和/或硅衬底的损坏。温度降低防止在栅极堆叠中的金属硅化物膜内形成硅团簇，这已被发现在栅极蚀刻步骤期间造成损坏。本发明还包括在栅极蚀刻步骤之前分散硅簇的方法。

5. 发明授权

US06753243B2 SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY (DRAM) CIRCUITRY 有权
标题翻译：形成接触开口的半导体处理方法，形成存储器电路的方法，形成电连接的方法以及形成动态随机存取存储器（DRAM）电路的方法
公开(公告)号：US06753243B2
公开(公告)日：2004-06-22
申请号：US10280452
申请日：2002-10-25
申请人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
发明人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L2144
CPC分类号： H01L27/10888 , H01L21/32051 , H01L21/76895 , H01L21/76897 , H01L27/10855 , H01L27/10885
摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.
摘要翻译：描述形成接触开口，存储器电路和动态随机存取存储器（DRAM）电路的方法。在一个实施方案中，字线阵列和位线形成在衬底表面上并由中间绝缘层隔开。位线的导电部分向外露出，并且在衬底和位线的暴露的导电部分上形成一层材料。材料层的选定部分与中间层的部分一起被去除，足以使（a）暴露衬底表面的选定区域，并且（b）重新暴露位线的导电部分。随后形成导电材料以将暴露的衬底区域与各个位线的相关联的导电部分电连接。

6. 发明授权

US06677241B1 Methods of forming a gate stack that is void of silicon clusters within a metallic silicide film thereof 有权
公开(公告)号：US06677241B1
公开(公告)日：2004-01-13
申请号：US09614113
申请日：2000-07-12
申请人： Pai-Hung Pan , Louie Liu , Ravi Iyer
发明人： Pai-Hung Pan , Louie Liu , Ravi Iyer
IPC分类号： H01L21302
摘要： A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

7. 发明授权

US06613673B2 Technique for elimination of pitting on silicon substrate during gate stack etch 有权
公开(公告)号：US06613673B2
公开(公告)日：2003-09-02
申请号：US09942191
申请日：2001-08-29
申请人： Pai-Hung Pan , Louie Liu , Ravi Iyer
发明人： Pai-Hung Pan , Louie Liu , Ravi Iyer
IPC分类号： H01L2100
CPC分类号： H01L21/28052
摘要： A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

8. 发明授权

US06593616B2 Buried bit line memory circuitry 有权
公开(公告)号：US06593616B2
公开(公告)日：2003-07-15
申请号：US10060894
申请日：2002-01-29
申请人： Yongjun Jeff Hu , Pai-Hung Pan , Scott Jeffrey DeBoer
发明人： Yongjun Jeff Hu , Pai-Hung Pan , Scott Jeffrey DeBoer
IPC分类号： H01K2972
CPC分类号： H01L27/10885 , H01L21/76838 , H01L21/76889 , H01L27/10814 , H01L27/10888
摘要： The invention includes buried bit line memory circuitry, methods of forming buried bit line memory circuitry, and semiconductor processing methods of forming conductive lines. In but one implementation, a semiconductor processing method of forming a conductive line includes forming a silicon comprising region over a substrate. A TiNx comprising layer is deposited over the silicon comprising region, where “x” is greater than 0 and less than 1. The TiNx comprising layer is annealed in a nitrogen containing atmosphere effective to transform at least an outermost portion of the TiNx layer over the silicon comprising region to TiN. After the annealing, an elemental tungsten comprising layer is deposited on the TiN and at least the elemental tungsten comprising layer, the TiN, and any remaining TiNx layer is patterned into conductive line. In one implementation, a method such as the above is utilized in the fabrication of buried bit line memory circuitry. In one implementation, the invention comprises buried bit line memory circuitry fabricated by the above and other methods.

9. 发明授权

US06423620B1 SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY DRAM CIRCUITRY 有权
公开(公告)号：US06423620B1
公开(公告)日：2002-07-23
申请号：US09935474
申请日：2001-08-21
申请人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
发明人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L2144
摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.

10. 发明授权

US06362086B1 Forming a conductive structure in a semiconductor device 有权
公开(公告)号：US06362086B1
公开(公告)日：2002-03-26
申请号：US09397763
申请日：1999-09-15
申请人： Ronald A. Weimer , Yongjun Jeff Hu , Pai Hung Pan , Deepa Ratakonda , James Beck , Randhir P. S. Thakur
发明人： Ronald A. Weimer , Yongjun Jeff Hu , Pai Hung Pan , Deepa Ratakonda , James Beck , Randhir P. S. Thakur
IPC分类号： H01L214763
摘要： A conductive structure for use in a semiconductor device includes a multilayer structure. A first layer includes a material containing silicon, e.g., polysilicon and silicon germanide. A barrier layer is formed over the first layer, with the barrier layer including metal silicide or metal silicide nitride. A top conductive layer is formed over the barrier layer. The top conductive layer can include metal or metal suicide. Selective oxidation can be performed to reduce the amount of oxidation of selected materials in a structure containing multiple layers, such as the multilayer conductive structure. The selective oxidation is performed in a single-wafer rapid thermal processing system, in which a selected ambient, including hydrogen, is used to ensure low oxidation of a selected material, such as tungsten or a metal nitride.

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