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1. 发明授权

US08237229B2 Method and apparatus for buried-channel semiconductor device 有权
标题翻译：埋沟通半导体器件的方法和装置
公开(公告)号：US08237229B2
公开(公告)日：2012-08-07
申请号：US12125852
申请日：2008-05-22
申请人： Prasanna Khare
发明人： Prasanna Khare
IPC分类号： H01L27/06
CPC分类号： H01L21/8249 , H01L27/0623
摘要： Methods and apparatus of integrating a buried-channel PMOS into a BiCMOS process. The apparatus comprises at least one bipolar transistor and at least one MOS device coupled to the at least one bipolar transistor, such that a gate of the at least one MOS device may be coupled to an emitter of the at least one bipolar transistor. The MOS device comprises a buried channel having mobility means, such as strained silicon for promoting hole mobility in the buried channel, and confinement means, such as a cap layer disposed proximate to the buried channel for limiting leakage of holes from the buried channel. The apparatus may be formed by exposing a substrate in a PMOS, forming a SiGe layer on the substrate, forming an oxide layer on the SiGe layer, masking the PMOS, and removing at least some of the oxide and at least some of the SiGe layer.
摘要翻译：将掩埋沟道PMOS集成到BiCMOS工艺中的方法和装置。该装置包括至少一个双极晶体管和耦合到至少一个双极晶体管的至少一个MOS器件，使得至少一个MOS器件的栅极可以耦合到至少一个双极晶体管的发射极。 MOS器件包括具有移动性装置的掩埋沟道，例如用于促进掩埋沟道中的空穴迁移率的应变硅，以及限制装置，例如靠近掩埋沟道布置的盖层，用于限制孔从掩埋沟道泄漏。该装置可以通过在PMOS中暴露衬底而形成，在衬底上形成SiGe层，在SiGe层上形成氧化物层，掩蔽PMOS，以及除去至少一些氧化物和至少一些SiGe层。

2. 发明申请

US20090289279A1 METHOD AND APPARATUS FOR BURIED-CHANNEL SEMICONDUCTOR DEVICE 有权
标题翻译： BURIED-CHANNEL SEMICONDUCTOR DEVICE的方法和装置
公开(公告)号：US20090289279A1
公开(公告)日：2009-11-26
申请号：US12125852
申请日：2008-05-22
申请人： Prasanna Khare
发明人： Prasanna Khare
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L21/8249 , H01L27/0623
摘要： Methods and apparatus of integrating a buried-channel PMOS into a BiCMOS process. The apparatus comprises at least one bipolar transistor and at least one MOS device coupled to the at least one bipolar transistor, such that a gate of the at least one MOS device may be coupled to an emitter of the at least one bipolar transistor. The MOS device comprises a buried channel having mobility means, such as strained silicon for promoting hole mobility in the buried channel, and confinement means, such as a cap layer disposed proximate to the buried channel for limiting leakage of holes from the buried channel. The apparatus may be formed by exposing a substrate in a PMOS, forming a SiGe layer on the substrate, forming an oxide layer on the SiGe layer, masking the PMOS, and removing at least some of the oxide and at least some of the SiGe layer.
摘要翻译：将掩埋沟道PMOS集成到BiCMOS工艺中的方法和装置。该装置包括至少一个双极晶体管和耦合到至少一个双极晶体管的至少一个MOS器件，使得至少一个MOS器件的栅极可以耦合到至少一个双极晶体管的发射极。 MOS器件包括具有移动性装置的掩埋沟道，例如用于促进掩埋沟道中的空穴迁移率的应变硅，以及限制装置，例如靠近掩埋沟道布置的盖层，用于限制孔从掩埋沟道泄漏。该装置可以通过在PMOS中暴露衬底而形成，在衬底上形成SiGe层，在SiGe层上形成氧化物层，掩蔽PMOS，以及除去至少一些氧化物和至少一些SiGe层。

3. 发明授权

US09012999B2 Semiconductor device with an inclined source/drain and associated methods 有权
标题翻译：具有倾斜源极/漏极和相关方法的半导体器件
公开(公告)号：US09012999B2
公开(公告)日：2015-04-21
申请号：US13590548
申请日：2012-08-21
申请人： Qing Liu , Prasanna Khare , Nicolas Loubet
发明人： Qing Liu , Prasanna Khare , Nicolas Loubet
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/70 , H01L21/8234
CPC分类号： H01L21/823814 , H01L21/76816 , H01L21/823425 , H01L21/823864 , H01L29/41766 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A semiconductor device includes a semiconductor substrate having a channel region therein, a gate structure above the channel region, and source and drain regions on opposite sides of the gate structure. A respective contact is on each of the source and drain regions. At least one of the source and drain regions has an inclined upper contact surface with the respective contact. The inclined upper contact surface has at least a 50% greater area than would a corresponding flat contact surface.
摘要翻译：半导体器件包括其中具有沟道区域的半导体衬底，沟道区域上方的栅极结构以及栅极结构的相对侧上的源极和漏极区域。每个源极和漏极区域上都有一个相应的触点。源极和漏极区域中的至少一个具有与相应触点的倾斜上接触表面。倾斜的上接触表面具有比相应的平坦接触表面至少大50％的面积。

4. 发明授权

US09000555B2 Electronic device including shallow trench isolation (STI) regions with bottom nitride liner and upper oxide liner and related methods 有权
标题翻译：电子器件包括具有底部氮化物衬垫和上部氧化物衬垫的浅沟槽隔离（STI）区域及相关方法
公开(公告)号：US09000555B2
公开(公告)日：2015-04-07
申请号：US13590703
申请日：2012-08-21
申请人： Qing Liu , Nicolas Loubet , Prasanna Khare
发明人： Qing Liu , Nicolas Loubet , Prasanna Khare
IPC分类号： H01L21/70 , H01L21/762
CPC分类号： H01L21/76283 , H01L21/762 , H01L21/76202 , H01L21/76224 , H01L21/76264
摘要： An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one STI region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include a nitride layer lining a bottom portion of the sidewall surface, an oxide layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.
摘要翻译：电子器件可以包括衬底，覆盖衬底的掩埋氧化物（BOX）层，覆盖BOX层的至少一个半导体器件，以及衬底中的至少一个STI区域，并与该至少一个半导体器件相邻。所述至少一个STI区域限定与所述衬底的侧壁表面，并且可以包括衬在所述侧壁表面的底部部分的氮化物层，在所述底部部分的上方衬着所述侧壁表面的顶部的氧化物层以及所述侧壁表面内的绝缘材料氮化物和氧化物层。

5. 发明申请

US20140054715A1 SEMICONDUCTOR DEVICE WITH AN INCLINED SOURCE/DRAIN AND ASSOCIATED METHODS 有权
标题翻译：具有封闭源/漏极和相关方法的半导体器件
公开(公告)号：US20140054715A1
公开(公告)日：2014-02-27
申请号：US13590548
申请日：2012-08-21
申请人： QING LIU , PRASANNA KHARE , NICOLAS LOUBET
发明人： QING LIU , PRASANNA KHARE , NICOLAS LOUBET
IPC分类号： H01L29/78 , H01L21/336 , H01L27/092
CPC分类号： H01L21/823814 , H01L21/76816 , H01L21/823425 , H01L21/823864 , H01L29/41766 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A semiconductor device includes a semiconductor substrate having a channel region therein, a gate structure above the channel region, and source and drain regions on opposite sides of the gate structure. A respective contact is on each of the source and drain regions. At least one of the source and drain regions has an inclined upper contact surface with the respective contact. The inclined upper contact surface has at least a 50% greater area than would a corresponding flat contact surface.
摘要翻译：半导体器件包括其中具有沟道区域的半导体衬底，沟道区域上方的栅极结构以及栅极结构的相对侧上的源极和漏极区域。每个源极和漏极区域上都有一个相应的触点。源极和漏极区域中的至少一个具有与相应触点的倾斜上接触表面。倾斜的上接触表面具有比相应的平坦接触表面至少大50％的面积。

6. 发明申请

US20130334651A1 DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS 有权
标题翻译：用于防止电气短路的双层防爆隔离衬套
公开(公告)号：US20130334651A1
公开(公告)日：2013-12-19
申请号：US13525642
申请日：2012-06-18
申请人： Bruce B. Doris , Shom Ponoth , Prasanna Khare , Qing Liu , Nicolas Loubet , Maud Vinet
发明人： Bruce B. Doris , Shom Ponoth , Prasanna Khare , Qing Liu , Nicolas Loubet , Maud Vinet
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76879 , H01L21/0217 , H01L21/76224 , H01L21/76283 , H01L21/76802 , H01L21/76877 , H01L21/76897 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/41783 , H01L29/66545 , H01L29/6656 , H01L29/66568 , H01L29/66628 , H01L29/78609
摘要： A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.
摘要翻译：形成浅沟槽以延伸到绝缘体上半导体（SOI）层的处理衬底中。在浅沟槽中形成介质金属氧化物层和氮化硅层的电介质衬垫层，随后沉积浅沟槽隔离填充部分。介电衬垫堆叠从顶部半导体部分的顶表面上方移除，随后除去介电金属氧化物层的氮化硅衬垫层和上部垂直部分。横向围绕顶部半导体部分和掩埋绝缘体部分的堆叠的边角填充有氮化硅部分。随后形成栅极结构和源极/漏极结构。氮化硅部分或电介质金属氧化物层在形成源极/漏极接触通孔期间用作停止层，从而防止源极/漏极接触通孔结构和处理衬底之间的电短路。

7. 发明申请

US20120267720A1 METHOD AND APPARATUS FOR BURIED-CHANNEL SEMICONDUCTOR DEVICE 审中-公开
标题翻译： BURIED-CHANNEL SEMICONDUCTOR DEVICE的方法和装置
公开(公告)号：US20120267720A1
公开(公告)日：2012-10-25
申请号：US13540416
申请日：2012-07-02
申请人： Prasanna Khare
发明人： Prasanna Khare
IPC分类号： H01L27/06 , H01L21/20
CPC分类号： H01L21/8249 , H01L27/0623
摘要： Methods and apparatus of integrating a buried-channel PMOS into a BiCMOS process. The apparatus comprises at least one bipolar transistor and at least one MOS device coupled to the at least one bipolar transistor, such that a gate of the at least one MOS device may be coupled to an emitter of the at least one bipolar transistor. The MOS device comprises a buried channel having mobility means, such as strained silicon for promoting hole mobility in the buried channel, and confinement means, such as a cap layer disposed proximate to the buried channel for limiting leakage of holes from the buried channel. The apparatus may be formed by exposing a substrate in a PMOS, forming a SiGe layer on the substrate, forming an oxide layer on the SiGe layer, masking the PMOS, and removing at least some of the oxide and at least some of the SiGe layer.
摘要翻译：将掩埋沟道PMOS集成到BiCMOS工艺中的方法和装置。该装置包括至少一个双极晶体管和耦合到至少一个双极晶体管的至少一个MOS器件，使得至少一个MOS器件的栅极可以耦合到至少一个双极晶体管的发射极。 MOS器件包括具有移动性装置的掩埋沟道，例如用于促进掩埋沟道中的空穴迁移率的应变硅，以及限制装置，例如靠近掩埋沟道布置的盖层，用于限制孔从掩埋沟道泄漏。该装置可以通过在PMOS中暴露衬底而形成，在衬底上形成SiGe层，在SiGe层上形成氧化物层，掩蔽PMOS，以及除去至少一些氧化物和至少一些SiGe层。

8. 发明申请

US20120156847A1 LAYER FORMATION WITH REDUCED CHANNEL LOSS 有权
标题翻译：具有减少通道损失的层形成
公开(公告)号：US20120156847A1
公开(公告)日：2012-06-21
申请号：US12971054
申请日：2010-12-17
申请人： Nicolas Loubet , Qing Liu , Prasanna Khare
发明人： Nicolas Loubet , Qing Liu , Prasanna Khare
IPC分类号： H01L21/336 , H01L21/302
CPC分类号： H01L29/1033 , H01L29/04 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/66772 , H01L29/78
摘要： Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.
摘要翻译：可以在半导体器件区域上形成绝缘层，并以基本上减少或防止下面的沟道区域的蚀刻量的方式进行蚀刻。可以在栅极区域和半导体器件区域上形成第一绝缘层。可以在第一绝缘层上形成第二绝缘层。可以在第二绝缘层上形成第三绝缘层。可以使用第一蚀刻工艺蚀刻第三绝缘层的一部分。可以使用与第一蚀刻工艺不同的至少第二蚀刻工艺来蚀刻第三绝缘层的蚀刻部分下方的第一绝缘层和第二绝缘层的一部分。

9. 发明授权

US08187975B1 Hydrochloric acid etch and low temperature epitaxy in a single chamber for raised source-drain fabrication 有权
标题翻译：在单个腔室中进行盐酸蚀刻和低温外延，用于提高源极 - 漏极制造
公开(公告)号：US08187975B1
公开(公告)日：2012-05-29
申请号：US12960736
申请日：2010-12-06
申请人： Prasanna Khare , Nicolas Loubet , Qing Liu
发明人： Prasanna Khare , Nicolas Loubet , Qing Liu
IPC分类号： H01L21/20 , H01L21/302 , H01L21/311 , H01L21/461 , H01L21/36
CPC分类号： H01L21/02661 , H01L21/02639 , H01L29/66628 , H01L29/66636
摘要： A raised source-drain structure is formed using a process wherein a semiconductor structure is received in a process chamber that is adapted to support both an etching process and an epitaxial growth process. This semiconductor structure includes a source region and a drain region, wherein the source and drain regions each include a damaged surface layer. The process chamber is controlled to set a desired atmosphere and set a desired temperature. At the desired atmosphere and temperature, the etching process of process chamber is used to remove the damaged surface layers from the source and drain regions and expose an interface surface. Without releasing the desired atmosphere and while maintaining the desired temperature, the epitaxial growth process of the process chamber is used to grow, from the exposed interface surface, a raised region above each of the source and drain regions.
摘要翻译：使用其中半导体结构被接收在适于支持蚀刻工艺和外延生长工艺两者的处理室中的工艺来形成凸起的源极 - 漏极结构。该半导体结构包括源极区和漏极区，其中源区和漏区各自包括受损的表面层。控制处理室以设定所需的气氛并设定所需的温度。在所需的气氛和温度下，处理室的蚀刻过程用于从源极和漏极区域去除损坏的表面层并暴露界面。在不释放期望的气氛的同时保持期望的温度，处理室的外延生长过程用于从暴露的界面表面生长在源极和漏极区之上的凸起区域。

10. 发明授权

US09768055B2 Isolation regions for SOI devices 有权
公开(公告)号：US09768055B2
公开(公告)日：2017-09-19
申请号：US13590836
申请日：2012-08-21
申请人： Qing Liu , Nicolas Loubet , Prasanna Khare , Shom Ponoth , Maud Vinet , Bruce Doris
发明人： Qing Liu , Nicolas Loubet , Prasanna Khare , Shom Ponoth , Maud Vinet , Bruce Doris
IPC分类号： H01L21/76 , H01L21/762 , H01L29/66 , H01L29/786
CPC分类号： H01L21/76232 , H01L29/66772 , H01L29/78654
摘要： An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.

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