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1. 发明授权

US08710626B2 Semiconductor device having trapezoidal shaped trenches 有权
标题翻译：具有梯形沟槽的半导体器件
公开(公告)号：US08710626B2
公开(公告)日：2014-04-29
申请号：US13552172
申请日：2012-07-18
申请人： Ayako Inoue , Naoto Saitoh
发明人： Ayako Inoue , Naoto Saitoh
IPC分类号： H01L21/02
CPC分类号： H01L29/945 , H01L29/66181
摘要： Provided is a semiconductor capacitor including: a capacitor device forming region having a trapezoidal trench which is formed on a surface of a first conductivity type semiconductor substrate; a second conductivity type lower electrode layer provided along the trapezoidal trenches of the capacitor device forming region; a capacitor insulating film formed at least on a surface of the second conductivity type lower electrode layer; and a second conductivity type upper electrode formed on a surface of the capacitor insulating film.
摘要翻译：提供一种半导体电容器，包括：形成在第一导电型半导体衬底的表面上的具有梯形沟槽的电容器器件形成区域; 沿着电容器器件形成区域的梯形沟槽设置的第二导电型下电极层; 至少形成在所述第二导电型下电极层的表面上的电容器绝缘膜; 以及形成在电容器绝缘膜的表面上的第二导电型上电极。

2. 发明授权

US08237222B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08237222B2
公开(公告)日：2012-08-07
申请号：US12658825
申请日：2010-02-16
申请人： Ayako Inoue , Naoto Saitoh
发明人： Ayako Inoue , Naoto Saitoh
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/0649 , H01L29/1045 , H01L29/105 , H01L29/66568 , H01L29/7834
摘要： In a method of manufacturing a high withstanding voltage MOSFET, a region to be doped with impurities and a region to be doped with no impurity are provided when ion implantation of the impurities is performed in the channel forming region, for controlling a threshold voltage. The region to be doped with no impurity is suitably patterned so that impurity concentration of the channel forming region near boundaries between a well region and a source region and between the well region and a drain region having the same conductivity type as the well region may be increased, to thereby induce a reverse short channel effect. By canceling a short channel effect with the reverse short channel effect induced by the above-mentioned method, the short channel effect of the high withstanding voltage MOSFET may be suppressed.
摘要翻译：在制造耐高压MOSFET的方法中，当在沟道形成区域中进行杂质的离子注入时，提供要掺杂有杂质的区域和不掺杂的区域，用于控制阈值电压。掺杂没有杂质的区域被适当地图案化，使得在阱区域和源极区域之间以及阱区域和与阱区域具有相同导电类型的漏极区域之间的边界附近的沟道形成区域的杂质浓度可以是增加，从而引起反向短通道效应。通过利用由上述方法引起的反向短通道效应消除短通道效应，可以抑制高耐压电压MOSFET的短沟道效应。

3. 发明申请

US20120074490A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20120074490A1
公开(公告)日：2012-03-29
申请号：US13225840
申请日：2011-09-06
申请人： Naoto Saitoh
发明人： Naoto Saitoh
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/66734
摘要： To realize forming a trench MOSFET in which a depth of a P-body is changed on the same surface as a CMOS by employing steps with good controllability and without greatly increasing the number of manufacturing steps, provided is a trench MOSFET including an extended body region (10), which is a part of a P-body region (4) and is provided in a vicinity of a deep trench (5) with a distance, the extended body region (10) being diffused deeper than the P-body region (4).
摘要翻译：为了实现通过采用具有良好可控性的步骤并且不大大增加制造步骤的数量来形成其中P体的深度在与CMOS相同的表面上变化的沟槽MOSFET，提供了包括延伸体区域（10），其是P体区域（4）的一部分，并且设置在深沟槽（5）附近一定距离处，所述延伸体区域（10）比所述P体区域（4）。

4. 发明申请

US20070085137A1 Semiconductor integrated circuit device and a manufacturing method for the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20070085137A1
公开(公告)日：2007-04-19
申请号：US11582911
申请日：2006-10-18
申请人： Naoto Saitoh , Yuichiro Kitajima
发明人： Naoto Saitoh , Yuichiro Kitajima
IPC分类号： H01L29/76
CPC分类号： H01L29/405 , H01L29/402 , H01L29/41725 , H01L29/41775 , H01L29/4983 , H01L29/7834 , H01L29/7835
摘要： Provided is a manufacturing method for a power management semiconductor device or an analog semiconductor device both including a CMOS. According to the method, a substance having high thermal conductivity is additionally provided above a semiconductor region constituting a low impurity concentration drain region so as to expand the drain region, which contributes to a promotion of thermal conductivity (or thermal emission) in the drain region during a surge input and leads to suppression of local temperature increase, to thereby prevent thermal destruction. Therefore, it is possible to manufacture a power management semiconductor device or an analog semiconductor device with the extended possibility of transistor design.
摘要翻译：提供了一种用于包括CMOS的功率管理半导体器件或模拟半导体器件的制造方法。根据该方法，在构成低杂质浓度漏极区域的半导体区域的上方附加设置具有高导热性的物质，以扩大漏极区域，有助于提高漏极区域（或发热）并且导致局部温度升高的抑制，从而防止热破坏。因此，可以制造具有扩大晶体管设计可能性的功率管理半导体器件或模拟半导体器件。

5. 发明授权

US5905291A MISFET semiconductor integrated circuit device 失效
标题翻译： MISFET半导体集成电路器件
公开(公告)号：US5905291A
公开(公告)日：1999-05-18
申请号：US503828
申请日：1995-07-18
申请人： Fumiyasu Utsunomiya , Yutaka Saitoh , Naoto Saitoh , Jun Osanai , Haruo Konishi , Masanori Miyagi
发明人： Fumiyasu Utsunomiya , Yutaka Saitoh , Naoto Saitoh , Jun Osanai , Haruo Konishi , Masanori Miyagi
IPC分类号： H01L21/8247 , H01L21/822 , H01L21/8234 , H01L27/02 , H01L27/04 , H01L27/06 , H01L27/088 , H01L27/10 , H01L29/788 , H01L29/792 , H01L29/772
CPC分类号： H01L27/0214 , H01L27/0629
摘要： A semiconductor integrated circuit device comprises at least two MISFETs formed on a semiconductor substrate and connected in series in a diode connection. Each of the MISFETs has a source, a drain, a channel extending between the source and the drain, and a gate disposed over the channel through a gate insulating film. One of the MISFETs has a first threshold voltage, and the other of the MISFETs has a second threshold voltage lower than the first threshold voltage. A portion of the channel of the semiconductor substrate of each of the MISFETs has an impurity concentration equal to or less than 6.times.10.sup.14 atoms/cc.
摘要翻译：半导体集成电路器件包括形成在半导体衬底上并以二极管连接串联连接的至少两个MISFET。每个MISFET具有源极，漏极，在源极和漏极之间延伸的沟道，以及通过栅极绝缘膜设置在沟道上方的栅极。一个MISFET具有第一阈值电压，另一个MISFET具有低于第一阈值电压的第二阈值电压。每个MISFET的半导体衬底的沟道的一部分具有等于或小于6×10 14原子/ cc的杂质浓度。

6. 发明申请

US20120280359A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120280359A1
公开(公告)日：2012-11-08
申请号：US13552172
申请日：2012-07-18
申请人： Ayako INOUE , Naoto SAITOH
发明人： Ayako INOUE , Naoto SAITOH
IPC分类号： H01L29/92
CPC分类号： H01L29/945 , H01L29/66181
摘要： Provided is a semiconductor capacitor including: a capacitor device forming region having a trapezoidal trench which is formed on a surface of a first conductivity type semiconductor substrate; a second conductivity type lower electrode layer provided along the trapezoidal trenches of the capacitor device forming region; a capacitor insulating film formed at least on a surface of the second conductivity type lower electrode layer; and a second conductivity type upper electrode formed on a surface of the capacitor insulating film.
摘要翻译：提供一种半导体电容器，包括：形成在第一导电型半导体衬底的表面上的具有梯形沟槽的电容器器件形成区域; 沿着电容器器件形成区域的梯形沟槽设置的第二导电型下电极层; 至少形成在所述第二导电型下电极层的表面上的电容器绝缘膜; 以及形成在电容器绝缘膜的表面上的第二导电型上电极。

7. 发明授权

US08247303B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08247303B2
公开(公告)日：2012-08-21
申请号：US13070267
申请日：2011-03-23
申请人： Ayako Inoue , Naoto Saitoh
发明人： Ayako Inoue , Naoto Saitoh
IPC分类号： H01L21/20
CPC分类号： H01L29/945 , H01L29/66181
摘要： Provided is a semiconductor capacitor including: a capacitor device forming region having a trapezoidal trench which is formed on a surface of a first conductivity type semiconductor substrate; a second conductivity type lower electrode layer provided along the trapezoidal trenches of the capacitor device forming region; a capacitor insulating film formed at least on a surface of the second conductivity type lower electrode layer; and a second conductivity type upper electrode formed on a surface of the capacitor insulating film.
摘要翻译：提供一种半导体电容器，包括：形成在第一导电型半导体衬底的表面上的具有梯形沟槽的电容器器件形成区域; 沿着电容器器件形成区域的梯形沟槽设置的第二导电型下电极层; 至少形成在所述第二导电型下电极层的表面上的电容器绝缘膜; 以及形成在电容器绝缘膜的表面上的第二导电型上电极。

8. 发明申请

US20110233724A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110233724A1
公开(公告)日：2011-09-29
申请号：US13070267
申请日：2011-03-23
申请人： Ayako Inoue , Naoto Saitoh
发明人： Ayako Inoue , Naoto Saitoh
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L29/945 , H01L29/66181
摘要： Provided is a semiconductor capacitor including: a capacitor device forming region having a trapezoidal trench which is formed on a surface of a first conductivity type semiconductor substrate; a second conductivity type lower electrode layer provided along the trapezoidal trenches of the capacitor device forming region; a capacitor insulating film formed at least on a surface of the second conductivity type lower electrode layer; and a second conductivity type upper electrode formed on a surface of the capacitor insulating film.
摘要翻译：提供一种半导体电容器，包括：形成在第一导电型半导体衬底的表面上的具有梯形沟槽的电容器器件形成区域; 沿着电容器器件形成区域的梯形沟槽设置的第二导电型下电极层; 至少形成在所述第二导电型下电极层的表面上的电容器绝缘膜; 以及形成在电容器绝缘膜的表面上的第二导电型上电极。

9. 发明申请

US20100219472A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100219472A1
公开(公告)日：2010-09-02
申请号：US12658825
申请日：2010-02-16
申请人： Ayako Inoue , Naoto Saitoh
发明人： Ayako Inoue , Naoto Saitoh
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/0649 , H01L29/1045 , H01L29/105 , H01L29/66568 , H01L29/7834
摘要： In a method of manufacturing a high withstanding voltage MOSFET, a region to be doped with impurities and a region to be doped with no impurity are provided when ion implantation of the impurities is performed in the channel forming region, for controlling a threshold voltage. The region to be doped with no impurity is suitably patterned so that impurity concentration of the channel forming region near boundaries between a well region and a source region and between the well region and a drain region having the same conductivity type as the well region may be increased, to thereby induce a reverse short channel effect. By canceling a short channel effect with the reverse short channel effect induced by the above-mentioned method, the short channel effect of the high withstanding voltage MOSFET may be suppressed.
摘要翻译：在制造耐高压MOSFET的方法中，当在沟道形成区域中进行杂质的离子注入时，提供要掺杂有杂质的区域和不掺杂的区域，用于控制阈值电压。掺杂没有杂质的区域被适当地图案化，使得在阱区域和源极区域之间以及阱区域和与阱区域具有相同导电类型的漏极区域之间的边界附近的沟道形成区域的杂质浓度可以是增加，从而引起反向短通道效应。通过利用由上述方法引起的反向短通道效应消除短通道效应，可以抑制高耐压电压MOSFET的短沟道效应。

10. 发明授权

US07880235B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07880235B2
公开(公告)日：2011-02-01
申请号：US11637553
申请日：2006-12-12
申请人： Naoto Saitoh
发明人： Naoto Saitoh
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/823878 , H01L27/0266 , H01L27/0629 , H01L29/4238
摘要： A semiconductor integrated circuit device has an SOI substrate comprising an insulating film laminated on a semiconductor support substrate and a semiconductor thin film laminated on the insulating film. A first N-channel MOS transistor, a first P-channel MOS transistor, and a resistor are each disposed on the semiconductor thin film. A second N-channel MOS transistor serving as an electrostatic discharge (ESD) protection element is disposed on a surface of the semiconductor support substrate that is exposed by removing a part of the semiconductor thin film and a part of the insulating film. The second N-channel MOS transistor has a gate electrode, a source region and a drain region surrounding the source region through the gate electrode to maintain a constant distance between the drain region and the source region.
摘要翻译：半导体集成电路器件具有SOI衬底，该SOI衬底包括层叠在半导体支撑衬底上的绝缘膜和层压在绝缘膜上的半导体薄膜。第一N沟道MOS晶体管，第一P沟道MOS晶体管和电阻均设置在半导体薄膜上。用作静电放电（ESD）保护元件的第二N沟道MOS晶体管设置在通过去除半导体薄膜的一部分和绝缘膜的一部分而被暴露的半导体支撑基板的表面上。第二N沟道MOS晶体管具有通过栅电极围绕源极区域的栅极电极，源极区域和漏极区域，以在漏极区域和源极区域之间保持恒定的距离。

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