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1. 发明授权

US5905291A MISFET semiconductor integrated circuit device 失效
标题翻译： MISFET半导体集成电路器件
公开(公告)号：US5905291A
公开(公告)日：1999-05-18
申请号：US503828
申请日：1995-07-18
申请人： Fumiyasu Utsunomiya , Yutaka Saitoh , Naoto Saitoh , Jun Osanai , Haruo Konishi , Masanori Miyagi
发明人： Fumiyasu Utsunomiya , Yutaka Saitoh , Naoto Saitoh , Jun Osanai , Haruo Konishi , Masanori Miyagi
IPC分类号： H01L21/8247 , H01L21/822 , H01L21/8234 , H01L27/02 , H01L27/04 , H01L27/06 , H01L27/088 , H01L27/10 , H01L29/788 , H01L29/792 , H01L29/772
CPC分类号： H01L27/0214 , H01L27/0629
摘要： A semiconductor integrated circuit device comprises at least two MISFETs formed on a semiconductor substrate and connected in series in a diode connection. Each of the MISFETs has a source, a drain, a channel extending between the source and the drain, and a gate disposed over the channel through a gate insulating film. One of the MISFETs has a first threshold voltage, and the other of the MISFETs has a second threshold voltage lower than the first threshold voltage. A portion of the channel of the semiconductor substrate of each of the MISFETs has an impurity concentration equal to or less than 6.times.10.sup.14 atoms/cc.
摘要翻译：半导体集成电路器件包括形成在半导体衬底上并以二极管连接串联连接的至少两个MISFET。每个MISFET具有源极，漏极，在源极和漏极之间延伸的沟道，以及通过栅极绝缘膜设置在沟道上方的栅极。一个MISFET具有第一阈值电压，另一个MISFET具有低于第一阈值电压的第二阈值电压。每个MISFET的半导体衬底的沟道的一部分具有等于或小于6×10 14原子/ cc的杂质浓度。

2. 发明授权

US5977688A Electronic apparatus for being switched using piezoelectric element 失效
标题翻译：使用压电元件切换的电子设备
公开(公告)号：US5977688A
公开(公告)日：1999-11-02
申请号：US825353
申请日：1997-03-28
申请人： Fumiyasu Utsunomiya , Yutaka Saitoh , Yoshifumi Yoshida , Kouei Ozaki , Toshiaki Narukawa
发明人： Fumiyasu Utsunomiya , Yutaka Saitoh , Yoshifumi Yoshida , Kouei Ozaki , Toshiaki Narukawa
IPC分类号： H01L41/107 , H01L41/08
CPC分类号： H01L41/107
摘要： An electronic apparatus that performs switching with the use of a piezoelectric element comprises a piezoelectric element 11, a first monitor electrode 15, and a second monitor electrode 16, the latter two being provided thereon and intended to output electric shock signals that are generated when a shock has been applied to the piezoelectric element 11 to thereby distort it. Whereby, a shock is applied to the electronic apparatus that contains the piezoelectric element 11 and a shock is applied to the built-in piezoelectric element 11. This makes it possible to output for the purpose of controlling the operation of the respective functions an electronic shock signal that is generated when the piezoelectric element 11 is distorted. As a result, it is possible to reduce the number of switch parts for, and hence the size of, the electronic apparatus and reduce the amount of time and labor for performing the switching operation by utilizing the piezoelectric effect of the piezoelectric element.
摘要翻译：使用压电元件执行切换的电子设备包括压电元件11，第一监视电极15和第二监视电极16，后者两个被设置在其上并用于输出当a 对压电元件11施加了冲击，从而使其变形。由此，对包含压电元件11的电子设备施加冲击并对内置的压电元件11施加冲击。这使得可以输出用于控制各个功能的操作的电子冲击当压电元件11失真时产生的信号。结果，可以通过利用压电元件的压电效应来减少电子设备的开关部件的数量和尺寸，并减少进行开关操作的时间和人力。

3. 发明授权

US08791686B2 Constant output reference voltage circuit 有权
标题翻译：恒定输出参考电压电路
公开(公告)号：US08791686B2
公开(公告)日：2014-07-29
申请号：US13609944
申请日：2012-09-11
申请人： Taro Yamasaki , Fumiyasu Utsunomiya
发明人： Taro Yamasaki , Fumiyasu Utsunomiya
IPC分类号： G05F1/10 , G05F3/02 , G05F3/16 , G05F3/20
CPC分类号： G05F3/262
摘要： The voltage reference circuit includes: a first MOS transistor; a second MOS transistor including a gate terminal connected to a gate terminal of the first MOS transistor and having an absolute value of a threshold value and a K value higher than an absolute value of a threshold value and a K value of the first MOS transistor; a current mirror circuit flowing a current based on a difference between the absolute values of the threshold values of the first MOS transistor and the second MOS transistor; a third MOS transistor flowing the current; and a fourth MOS transistor having an absolute value of a threshold value and a K value higher than an absolute value of a threshold value of the third MOS transistor and flowing the current.
摘要翻译：所述电压基准电路包括：第一MOS晶体管; 第二MOS晶体管，包括连接到第一MOS晶体管的栅极端子并具有阈值的绝对值和高于阈值的绝对值和第一MOS晶体管的K值的K值的栅极端子; 基于第一MOS晶体管和第二MOS晶体管的阈值的绝对值之间的差异流动电流的电流镜像电路; 流过电流的第三MOS晶体管; 以及第四MOS晶体管，其绝对值为阈值，K值高于第三MOS晶体管的阈值的绝对值并使电流流动。

4. 发明授权

US07961035B2 Boosting circuit 有权
标题翻译：升压电路
公开(公告)号：US07961035B2
公开(公告)日：2011-06-14
申请号：US12695464
申请日：2010-01-28
申请人： Makoto Mitani , Fumiyasu Utsunomiya
发明人： Makoto Mitani , Fumiyasu Utsunomiya
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： Provided is a boosting circuit having a small circuit scale. When a node (Vg) is reset by a reset transistor (M3) after a boosting operation has been finished, the reset transistor (M3) is controlled based on a power supply voltage to reset the node (Vg). Therefore, another boosted voltage is not required for the reset, and hence an additional boosting circuit required for the another boosted voltage is unnecessary as well. As a result, the circuit scale of the boosting circuit is reduced correspondingly to the additional boosting circuit.
摘要翻译：提供具有小电路规模的升压电路。当升压操作结束后，当一个节点（Vg）被复位晶体管（M3）复位时，基于电源电压来控制复位晶体管（M3）以复位节点（Vg）。因此，复位不需要另一升压电压，因此也不需要另外的升压电压所需的另外的升压电路。结果，升压电路的电路规模相应于附加的升压电路而减小。

5. 发明授权

US07907453B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07907453B2
公开(公告)日：2011-03-15
申请号：US12389738
申请日：2009-02-20
申请人： Fumiyasu Utsunomiya
发明人： Fumiyasu Utsunomiya
IPC分类号： G11C16/06
CPC分类号： G11C7/12 , G11C7/067 , G11C16/26
摘要： Provided is a nonvolatile semiconductor memory device which reads out a memory cell at high speed. A minute current source (105) is connected to a clamp NMOS transistor (103) for clamping a drain voltage of a memory cell (101), and a minute current is caused to flow through the clamp NMOS transistor (103). When the current does not flow through the memory cell (101), by causing the minute current to flow through the clamp NMOS transistor (103), the drain voltage of the memory cell (101) is prevented from rising. A bias voltage (BIAS) to be input to the clamp NMOS transistor (103) can be set high and the drain voltage of the memory cell (101) can also be high, and hence a current value of the memory cell (101) becomes larger and speed of sensing a current of a sense amplifier circuit (104) is improved.
摘要翻译：提供了一种以高速读出存储单元的非易失性半导体存储器件。微电流源（105）连接到用于钳位存储单元（101）的漏极电压的钳位NMOS晶体管（103），使微小电流流过钳位NMOS晶体管（103）。当电流不流过存储单元（101）时，通过使微小电流流过钳位NMOS晶体管（103），可以防止存储单元（101）的漏极电压上升。可以将要输入到钳位NMOS晶体管（103）的偏置电压（BIAS）设置为高，并且存储单元（101）的漏极电压也可以高，因此存储单元（101）的当前值变为提高感测放大器电路（104）的电流的较大和速度。

6. 发明申请

US20100258706A1 PHOTODETECTOR CIRCUIT AND ELECTRONIC DEVICE 有权
标题翻译：光电设备电路和电子设备
公开(公告)号：US20100258706A1
公开(公告)日：2010-10-14
申请号：US12756441
申请日：2010-04-08
申请人： Fumiyasu Utsunomiya
发明人： Fumiyasu Utsunomiya
IPC分类号： G01J1/42 , H01L31/09
CPC分类号： G01J1/44
摘要： Provided is a photodetector circuit having significantly low current consumption. The photodetector circuit includes two opposing P-channel metal oxide semiconductor (MOS) transistors each including a gate connected to a drain of the opposing P-channel MOS transistor. The drain of one of the P-channel MOS transistors is discharged with an ON-state current of an N-channel MOS transistor which is turned ON with a voltage generated in a photoelectric element. The drain of the other of the P-channel MOS transistors is discharged with an ON-state current of a depletion type N-channel MOS transistor including a gate to which a voltage of a reference power supply terminal is input, and a source to which the voltage generated in the photoelectric element is input.
摘要翻译：提供了具有显着低的电流消耗的光电检测器电路。光电检测器电路包括两个相对的P沟道金属氧化物半导体（MOS）晶体管，每个晶体管包括连接到相对的P沟道MOS晶体管的漏极的栅极。一个P沟道MOS晶体管的漏极以通过在光电元件中产生的电压导通的N沟道MOS晶体管的导通状态电流放电。另一方的P沟道MOS晶体管的漏极以包括输入基准电源端子的电压的栅极的耗尽型N沟道MOS晶体管的导通状态电流被放电，源极输入光电元件中产生的电压。

7. 发明申请

US20100188137A1 BOOSTING CIRCUIT 有权
标题翻译：升压电路
公开(公告)号：US20100188137A1
公开(公告)日：2010-07-29
申请号：US12695464
申请日：2010-01-28
申请人： Makoto Mitani , Fumiyasu Utsunomiya
发明人： Makoto Mitani , Fumiyasu Utsunomiya
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： Provided is a boosting circuit having a small circuit scale. When a node (Vg) is reset by a reset transistor (M3) after a boosting operation has been finished, the reset transistor (M3) is controlled based on a power supply voltage to reset the node (Vg). Therefore, another boosted voltage is not required for the reset, and hence an additional boosting circuit required for the another boosted voltage is unnecessary as well. As a result, the circuit scale of the boosting circuit is reduced correspondingly to the additional boosting circuit.
摘要翻译：提供具有小电路规模的升压电路。当升压操作结束后，当一个节点（Vg）被复位晶体管（M3）复位时，基于电源电压来控制复位晶体管（M3）以复位节点（Vg）。因此，复位不需要另一升压电压，因此也不需要另外的升压电压所需的另外的升压电路。结果，升压电路的电路规模相应于附加的升压电路而减小。

8. 发明申请

US20080180079A1 Voltage regulator 审中-公开
标题翻译：电压调节器
公开(公告)号：US20080180079A1
公开(公告)日：2008-07-31
申请号：US11998386
申请日：2007-11-29
申请人： Tadashi Kurozo , Kiyoshi Yoshikawa , Fumiyasu Utsunomiya
发明人： Tadashi Kurozo , Kiyoshi Yoshikawa , Fumiyasu Utsunomiya
IPC分类号： G05F1/08 , G05F1/20 , G05F1/46
CPC分类号： G05F1/575
摘要： A voltage regulator according to the present invention is operated stably. Regardless of a condition of a load (25), a variation in drain voltage of a PMOS transistor (34) is made equal to a variation in output voltage (Vout) at an output terminal of the voltage regulator. Then, a variation in voltage which is equal to the variation in output voltage (Vout) at the output terminal which is caused by a change of the condition of the load (25) is fed back to an error amplifier (70), so a gain of a signal for phase compensation which is fed back to the error amplifier (70) is determined based on the output voltage (Vout). Therefore, even when the condition of the load (25) changes, the behavior of phase compensation is correct.
摘要翻译：根据本发明的电压调节器稳定地工作。不管负载条件（25）如何，使PMOS晶体管（34）的漏极电压的变化等于电压调节器的输出端的输出电压（Vout）的变化。然后，由负载（25）的状态的变化引起的等于输出端子的输出电压（Vout）的变化的电压变化被反馈到误差放大器（70），因此，基于输出电压（Vout）来确定反馈到误差放大器（70）的相位补偿信号的增益。因此，即使负载（25）的状态发生变化，相位补偿的动作也是正确的。

9. 发明授权

US06879502B2 Power source inverter circuit 有权
标题翻译：电源逆变电路
公开(公告)号：US06879502B2
公开(公告)日：2005-04-12
申请号：US10460618
申请日：2003-06-12
申请人： Yoshifumi Yoshida , Fumiyasu Utsunomiya
发明人： Yoshifumi Yoshida , Fumiyasu Utsunomiya
IPC分类号： H02M3/07 , H02M3/156
CPC分类号： H02M3/07 , H02M3/156
摘要： A power source inverter circuit is provided which, when a feeding unit generates enough electric power, puts a load circuit into operation while storing electric power in a storage unit and, when the power feeding unit stops generating power, efficiently uses up the electric power stored in the storage unit. The power source inverter circuit is composed of: a variable DC—DC converter for raising or dropping a voltage of electric power that is supplied from the power feeding unit; the storage unit; MOSFET switches for connecting the power feeding unit and the storage unit to an input of the variable DC—DC converter and for connecting an output of the variable DC—DC converter to the storage unit and the load circuit; a control circuit for controlling gates of the MOSFET switches; and a voltage detector for monitoring output of the power feeding unit, the voltage of the storage unit, the input voltage of the load circuit, and for outputting voltage information to the variable DC—DC converter as well as to the control circuit.
摘要翻译：提供了一种电源逆变器电路，当馈电单元产生足够的电力时，在将电力存储在存储单元中的同时将负载电路放入运行中，并且当供电单元停止发电时，有效地利用存储的电力在存储单元中。电源逆变电路由以下部分组成：可变DC-DC转换器，用于升高或降低从供电单元提供的电力电压; 存储单元; 用于将馈电单元和存储单元连接到可变DC-DC转换器的输入端并用于将可变DC-DC转换器的输出连接到存储单元和负载电路的MOSFET开关; 用于控制MOSFET开关的栅极的控制电路; 以及电压检测器，用于监视馈电单元的输出，存储单元的电压，负载电路的输入电压，以及用于将电压信息输出到可变DC-DC转换器以及控制电路。

10. 发明授权

US06359841B1 Timepiece and portable electronic device having thermoelectric generator unit 失效
标题翻译：具有热电发电机单元的钟表和便携式电子装置
公开(公告)号：US06359841B1
公开(公告)日：2002-03-19
申请号：US09319629
申请日：1999-06-08
申请人： Susumu Kotanagi , Akihiro Matoge , Yoshifumi Yoshida , Fumiyasu Utsunomiya , Matsuo Kishi
发明人： Susumu Kotanagi , Akihiro Matoge , Yoshifumi Yoshida , Fumiyasu Utsunomiya , Matsuo Kishi
IPC分类号： G04B100
CPC分类号： G04G19/02 , G04C10/00 , H02J7/00 , H02M3/07
摘要： A portable electronic device has a casing has an upper case body and a rear case cover both made of a thermally conductive material. A heat insulating member thermally insulates the rear case cover from the upper case body of the casing. A thermoelectric generator unit is disposed in the casing for generating an electromotive force based on the Seebeck effect. The thermoelectric generator unit has a heat radiating plate for transferring heat to the upper case body and a heat absorbing plate. A heat conductive spacer is made of a thermally conductive and elastically deformable sheet of material and has opposed main surfaces. One of the main surface is disposed in contact with the heat absorbing plate of the thermoelectric generator unit and the other main surface is disposed in contact with an inner side surface of the rear case cover for conducting heat from the rear case cover to the thermoelectric generator unit. A timepiece driving circuit is disposed in the casing and is driven by the electromotive force generated by the thermoelectric generator unit. At least one display member displays information in accordance with a signal output from the timepiece driving circuit.
摘要翻译：便携式电子设备具有壳体，其具有由导热材料制成的上壳体和后壳盖。绝热构件将后壳体盖与壳体的上壳体主体热绝缘。热电发电机单元设置在壳体中，用于基于塞贝克效应产生电动势。热电发电机单元具有用于将热量传递到上壳体和散热板的散热板。导热间隔件由导热且可弹性变形的材料片制成并且具有相对的主表面。主表面之一设置成与热电发电机单元的吸热板接触，另一个主表面设置成与后壳盖的内侧表面接触，用于将热量从后壳盖传导到热电发电机单元。钟表驱动电路设置在壳体中并由热电发电机单元产生的电动势驱动。至少一个显示构件根据从钟表驱动电路输出的信号显示信息。

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