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1. 发明授权

US5905291A MISFET semiconductor integrated circuit device 失效
标题翻译： MISFET半导体集成电路器件
公开(公告)号：US5905291A
公开(公告)日：1999-05-18
申请号：US503828
申请日：1995-07-18
申请人： Fumiyasu Utsunomiya , Yutaka Saitoh , Naoto Saitoh , Jun Osanai , Haruo Konishi , Masanori Miyagi
发明人： Fumiyasu Utsunomiya , Yutaka Saitoh , Naoto Saitoh , Jun Osanai , Haruo Konishi , Masanori Miyagi
IPC分类号： H01L21/8247 , H01L21/822 , H01L21/8234 , H01L27/02 , H01L27/04 , H01L27/06 , H01L27/088 , H01L27/10 , H01L29/788 , H01L29/792 , H01L29/772
CPC分类号： H01L27/0214 , H01L27/0629
摘要： A semiconductor integrated circuit device comprises at least two MISFETs formed on a semiconductor substrate and connected in series in a diode connection. Each of the MISFETs has a source, a drain, a channel extending between the source and the drain, and a gate disposed over the channel through a gate insulating film. One of the MISFETs has a first threshold voltage, and the other of the MISFETs has a second threshold voltage lower than the first threshold voltage. A portion of the channel of the semiconductor substrate of each of the MISFETs has an impurity concentration equal to or less than 6.times.10.sup.14 atoms/cc.
摘要翻译：半导体集成电路器件包括形成在半导体衬底上并以二极管连接串联连接的至少两个MISFET。每个MISFET具有源极，漏极，在源极和漏极之间延伸的沟道，以及通过栅极绝缘膜设置在沟道上方的栅极。一个MISFET具有第一阈值电压，另一个MISFET具有低于第一阈值电压的第二阈值电压。每个MISFET的半导体衬底的沟道的一部分具有等于或小于6×10 14原子/ cc的杂质浓度。

2. 发明授权

US06498376B1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06498376B1
公开(公告)日：2002-12-24
申请号：US08459831
申请日：1995-06-02
申请人： Masanori Miyagi , Haruo Konishi , Kazuaki Kubo , Yoshikazu Kojima , Toru Shimizu , Yutaka Saitoh , Toru Machida , Tetsuya Kaneko
发明人： Masanori Miyagi , Haruo Konishi , Kazuaki Kubo , Yoshikazu Kojima , Toru Shimizu , Yutaka Saitoh , Toru Machida , Tetsuya Kaneko
IPC分类号： H01L2976
CPC分类号： H01L29/78696 , H01L21/3226 , H01L21/823462 , H01L27/0705 , H01L29/1041 , H01L29/1045 , H01L29/66757
摘要： A MISFET is provided with a segmented channel comprising regions in which the channel is inverted by a first gate voltage and regions in which the channel is inverted by a second gate voltage. The MISFET is formed in a semiconductor substrate having a first conductivity type and the first inversion region of the channel has a first impurity concentration determined by the surface concentration of the substrate. The second inversion region of the channel has a second impurity concentration determined by doping an impurity to the region selected by a photolithographic process. The first and second inversion regions may be divided into a plurality of plane shapes and the threshold voltage of the MISFET is set to a desired value in accordance with the plane area ratio of the first and second inversion regions.
摘要翻译： MISFET设置有分段通道，该分段通道包括其中通道被第一栅极电压反相的区域和通道以第二栅极电压反相的区域。 MISFET形成在具有第一导电类型的半导体衬底中，沟道的第一反相区域具有由衬底的表面浓度确定的第一杂质浓度。通道的第二反转区域具有通过将杂质掺杂到通过光刻工艺选择的区域而确定的第二杂质浓度。第一反转区域和第二反转区域可以被划分成多个平面形状，并且根据第一和第二反转区域的平面面积比将MISFET的阈值电压设置为期望值。

3. 发明授权

US06306709B1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06306709B1
公开(公告)日：2001-10-23
申请号：US09270648
申请日：1999-03-16
申请人： Masanori Miyagi , Haruo Konishi , Kazuaki Kubo , Yoshikazu Kojima , Toru Shimizu , Yutaka Saitoh , Toru Machida , Tetsuya Kaneko
发明人： Masanori Miyagi , Haruo Konishi , Kazuaki Kubo , Yoshikazu Kojima , Toru Shimizu , Yutaka Saitoh , Toru Machida , Tetsuya Kaneko
IPC分类号： H01L21336
CPC分类号： H01L29/78696 , H01L21/3226 , H01L21/823462 , H01L27/0705 , H01L29/1041 , H01L29/1045 , H01L29/66757
摘要： In a MISFET, areas where a channel surface of a channel region is inverted by a first gate voltage and areas where the channel surface is inverted by a second gate voltage are provided in the channel region of the MISFET in plane as components thereof. The channel region 104 having a first impurity concentration determined by a surface concentration of a P-type semiconductor substrate and a channel region 105 having a second impurity concentration determined by doping an impurity to the region selected by a pattern 106 of a mask for doping impurity by ion implantation and others are provided in a channel region of an N-type MOSFET on the P-type semiconductor substrate. The channel region 104 having the first impurity concentration and the channel region 105 having the second impurity concentration are divided into a plurality of plane shapes. The channel region of the same MOSFET may be structured by the plurality of plane shapes having the plurality of impurity concentrations as described above and a threshold voltage of the MOSFET may be readily set to a desired value in response to a plane area ratio of the area having the first impurity concentration and the area having the second impurity concentration, allowing to realize a high performance semiconductor integrated circuit device at low cost.
摘要翻译：在MISFET中，在MISFET的沟道区域中设置沟道区域的沟道表面被第一栅极电压反转的区域和沟道表面由第二栅极电压反转的区域，作为其组成。具有由P型半导体衬底的表面浓度确定的第一杂质浓度的通道区域104和通过掺杂杂质确定的第二杂质浓度的沟道区域105，所述沟道区域105由用于掺杂杂质的掩模的图案106选择的区域通过离子注入等设置在P型半导体衬底上的N型MOSFET的沟道区中。具有第一杂质浓度的沟道区域104和具有第二杂质浓度的沟道区域105被分成多个平面形状。相同MOSFET的沟道区域可以由具有如上所述的多个杂质浓度的多个平面形状构成，并且可以根据区域的平面面积比容易地将MOSFET的阈值电压设置为期望值具有第一杂质浓度和具有第二杂质浓度的面积，从而以低成本实现高性能半导体集成电路器件。

4. 发明授权

US5780904A Semiconductor integrated circuit device for obtaining extremely small constant current and timer circuit using constant current circuit 失效
标题翻译：用于获得极小的恒流和使用恒流电路的定时器电路的半导体集成电路器件
公开(公告)号：US5780904A
公开(公告)日：1998-07-14
申请号：US671941
申请日：1996-06-28
申请人： Haruo Konishi , Masanao Hamaguchi , Masanori Miyagi
发明人： Haruo Konishi , Masanao Hamaguchi , Masanori Miyagi
IPC分类号： G05F3/24 , G05F3/26 , G11C11/406 , H03F3/343 , H03F3/347 , H01L27/06
CPC分类号： G05F3/262
摘要： To obtain an extremely small constant current with high accuracy, a constant current circuit comprises a first constant-current source for producing a first constant current, a second constant-current source connected to the first constant-current source for producing a second constant current having a different value from that of the first current, and an output terminal from which a third constant current equal to the difference between the first and second constant currents is output, such that the third constant current having an extremely small value may be produced without the use of a constant current source capable of producing an extremely small constant current value. The first and second constant current sources may be connected in series with the output terminal connected therebetween, or in parallel through a current mirror circuit. In addition, the constant current circuit can be provided in a timer circuit to produce a very long constant time signal with great stability. In one embodiment, such a timer circuit further includes a capacitor connected to the output terminal for receiving the third constant current and accumulating charge, a reference voltage generator for producing a reference voltage, and a voltage comparator for comparing the voltage of the capacitor with the reference voltage.
摘要翻译：为了以高精度获得极小的恒定电流，恒流电路包括用于产生第一恒定电流的第一恒流源，连接到第一恒流源的第二恒流源，用于产生具有第二恒定电流的第二恒定电流，与第一电流不同的值以及输出等于第一和第二恒定电流之间的差的第三恒定电流的输出端子，使得可以产生具有极小值的第三恒定电流，而不需要使用能够产生非常小的恒定电流值的恒定电流源。第一和第二恒流源可以与连接在它们之间的输出端子串联连接，或者通过电流镜电路并联连接。此外，恒定电流电路可以提供在定时器电路中以产生非常长的恒定时间信号，具有很大的稳定性。在一个实施例中，这种定时器电路还包括连接到输出端子的电容器，用于接收第三恒定电流并累积电荷，用于产生参考电压的参考电压发生器和用于将电容器的电压与参考电压。

5. 发明授权

US4828657A Method for production of tin-cobalt, tin-nickel, or tin-lead binary alloy electroplating bath and electroplating bath produced thereby 失效
标题翻译：用于生产锡钴，锡镍或锡铅二元合金电镀浴的电镀方法和由此生产的电镀浴
公开(公告)号：US4828657A
公开(公告)日：1989-05-09
申请号：US200723
申请日：1988-05-31
申请人： Kazuhiro Fukuoka , Haruo Konishi
发明人： Kazuhiro Fukuoka , Haruo Konishi
IPC分类号： C25D3/56 , C25D3/60
CPC分类号： C25D3/60
摘要： An electroplating bath for the formation of a tin-cobalt, tin-nickel, or tin-lead binary alloy coating is produced by mixing (a) as alloy coating-forming agent a tin salt and one member selected from the group consisting of a cobalt salt, a nickel salt, and a lead salt, (b) 1-hydroxyethane-1,1-diphosphoric acid and/or a salt thereof, (c) methanesulfonic acid and/or an alkali salt thereof, and (d) an electroconductive salt. A coating formed by electroplating using the bath is stable and excellent in gloss.

6. 发明授权

US5153855A Semiconductor nonvolatile memory device integrated with booster 失效
标题翻译：与激光器集成的半导体非易失性存储器件
公开(公告)号：US5153855A
公开(公告)日：1992-10-06
申请号：US553778
申请日：1990-07-13
申请人： Haruo Konishi
发明人： Haruo Konishi
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/30
CPC分类号： G11C5/143 , G11C16/30
摘要： The nonvolatile memory includes a voltage booster and a supply voltage detection circuit, which is powered only when the voltage booster is operated so as to limit current consumption of the supply voltage detection circuit to substantially only leakage current during a non-operation period of the booster.

7. 发明授权

US5610428A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5610428A
公开(公告)日：1997-03-11
申请号：US476221
申请日：1995-06-07
申请人： Yukio Suzuki , Haruo Konishi , Yoshikazu Kojima
发明人： Yukio Suzuki , Haruo Konishi , Yoshikazu Kojima
IPC分类号： H01L21/8247 , H01L21/76 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/784 , H01L29/78
CPC分类号： H01L29/7883 , H01L27/105
摘要： A semiconductor integrated circuit comprises a semiconductor substrate of a first conductivity type, at least one electrically erasable floating gate type semiconductor non-volatile memory transistor disposed on a surface of the semiconductor substrate, a well region of a second conductivity type formed in the surface of the semiconductor substrate, and a program voltage switching transistor of the first conductivity type disposed in the well region. A field insulation film is disposed on the surface of the semiconductor substrate. A field dope region of the first conductivity type is provided beneath the field insulation film. The field dope region preferably has an impurity concentration higher than an impurity concentration of the semiconductor substrate. By this construction, current leakage is prevented at the time when a high voltage occurs such as, for example, when performing a writing operation with respect to EEPROM.
摘要翻译：半导体集成电路包括第一导电类型的半导体衬底，设置在半导体衬底的表面上的至少一个电可擦除浮栅型半导体非易失性存储晶体管，形成在第二导电类型的表面上的第二导电类型的阱区所述半导体衬底以及设置在所述阱区中的所述第一导电类型的编程电压开关晶体管。在半导体衬底的表面上设置场绝缘膜。第一导电类型的场掺杂区域设置在场绝缘膜的下方。场掺杂区优选具有高于半导体衬底的杂质浓度的杂质浓度。通过这种结构，在诸如例如当对EEPROM执行写入操作时出现高电压时，防止了电流泄漏。

8. 发明授权

US5135574A Electroless Pb-Sn alloy plating bath composition 失效
标题翻译：电镀PB-SN合金镀层组合物
公开(公告)号：US5135574A
公开(公告)日：1992-08-04
申请号：US693576
申请日：1991-04-30
申请人： Haruo Konishi , Kazuhiro Fukuoka , Keiki Kiyohara , Saburo Yonekura , Isao Miyatake
发明人： Haruo Konishi , Kazuhiro Fukuoka , Keiki Kiyohara , Saburo Yonekura , Isao Miyatake
IPC分类号： C23C18/48 , H05K3/18 , H05K3/24 , H05K3/34
CPC分类号： C23C18/48 , H05K3/3473
摘要： An electroless Pb-Sn alloy plating bath composition is obtained by mixing at least one of methane sulfonic acid, 1-hydroxyethane-1, 1-diphosphoric acid and a salt of 1-hydroxyethane-1, 1-diposphoric acid, compounds for forming Pb-Sn alloy and a reducing agent.

9. 发明授权

US5530672A Integrated circuit for operation with plural supply voltages 失效
标题翻译：具有多个电源电压的集成电路
公开(公告)号：US5530672A
公开(公告)日：1996-06-25
申请号：US239604
申请日：1994-05-09
申请人： Haruo Konishi
发明人： Haruo Konishi
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , H01L21/822 , H01L27/04 , H02M3/07 , H03K17/00 , H03K17/693 , G11C8/00 , H03K17/04
CPC分类号： H03K17/693 , G11C5/143 , H03K2217/0036
摘要： A semiconductor integrated circuit which operates with a single power source and has a high-tension circuit for generating a voltage higher than a power voltage and for logically processing is enabled to operate at a low power voltage by reducing the current consumed in the high-tension circuit. The semiconductor integrated circuit of the present invention comprises a block transistor 1, Vcc line circuit 2, Vpp line circuit 3 and gate potential varying circuit 4. Gate potential of the block transistor 1 is controlled by the gate potential varying circuit 4. The gate potential varying circuit 4 outputs a signal for controlling the gate potential of the block transistor 1.
摘要翻译：利用单个电源工作并具有用于产生高于电源电压并用于逻辑处理的电压的高压电路的半导体集成电路能够通过降低在高压下消耗的电流而在低功率电压下工作电路。本发明的半导体集成电路包括块晶体管1，Vcc线电路2，Vpp线电路3和栅极电位变化电路4.块晶体管1的栅极电位由栅极电位变化电路4控制。栅极电位变换电路4输出用于控制块晶体管1的栅极电位的信号。

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