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1. 发明授权

US06714030B2 Semiconductor inspection apparatus 失效
标题翻译：半导体检测仪器
公开(公告)号：US06714030B2
公开(公告)日：2004-03-30
申请号：US10390412
申请日：2003-03-18
申请人： Ryuji Kohno , Hideo Miura , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Hideyuki Aoki , Naoto Ban
发明人： Ryuji Kohno , Hideo Miura , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Hideyuki Aoki , Naoto Ban
IPC分类号： G01R3102
CPC分类号： H01L22/32 , G01R1/06711 , G01R1/06738 , G01R1/07314 , G01R3/00 , H01L23/13 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes. A method of manufacturing the semiconductor inspection apparatus comprises the steps of forming a cover film on a surface of the silicon substrate and forming a plurality of probes of a polygonal cone shape or a circular cone shape through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a beam or a diaphragm for each probe through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a through hole corresponding to the probe through etching after patterning by photolithography, and after the cover film is removed, forming an insulating film on the surface of the silicon substrate, forming a metal film on a surface of the insulating film, and forming a wiring lead through etching after patterning by photolithography.
摘要翻译：可以一次共同地检查多个半导体器件的半导体检查装置，由于探针的精度等，以前难以进行。一种制造半导体检查装置的方法包括以下步骤：在硅衬底的表面上形成覆盖膜，并通过光刻图案化之后通过蚀刻形成多个锥形或圆锥形的多个探针，被去除，再次在硅衬底的表面上形成覆盖膜，并且通过光刻在图案化之后通过蚀刻形成用于每个探针的光束或隔膜，在除去覆盖膜之后，再次在硅表面上形成覆盖膜在通过光刻图案化之后通过蚀刻形成与探针对应的通孔，并且在除去覆盖膜之后，在硅衬底的表面上形成绝缘膜，在绝缘膜的表面上形成金属膜，以及通过光刻在图案化之后通过蚀刻形成布线引线。

2. 发明授权

US06548315B2 Manufacture method for semiconductor inspection apparatus 失效
公开(公告)号：US06548315B2
公开(公告)日：2003-04-15
申请号：US10057921
申请日：2002-01-29
申请人： Ryuji Kohno , Hideo Miura , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Hideyuki Aoki , Naoto Ban
发明人： Ryuji Kohno , Hideo Miura , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Hideyuki Aoki , Naoto Ban
IPC分类号： H01L2166
CPC分类号： H01L22/32 , G01R1/06711 , G01R1/06738 , G01R1/07314 , G01R3/00 , H01L23/13 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes. A method of manufacturing the semiconductor inspection apparatus comprises the steps of forming a cover film on a surface of the silicon substrate and forming a plurality of probes of a polygonal cone shape or a circular cone shape through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a beam or a diaphragm for each probe through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a through hole corresponding to the probe through etching after patterning by photolithography, and after the cover film is removed, forming an insulating film on the surface of the silicon substrate, forming a metal film on a surface of the insulating film, and forming a wiring lead through etching after patterning by photolithography.

3. 发明授权

US06358762B1 Manufacture method for semiconductor inspection apparatus 失效
公开(公告)号：US06358762B1
公开(公告)日：2002-03-19
申请号：US09534302
申请日：2000-03-23
申请人： Ryuji Kohno , Hideo Miura , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Hideyuki Aoki , Naoto Ban
发明人： Ryuji Kohno , Hideo Miura , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Hideyuki Aoki , Naoto Ban
IPC分类号： G01R3126
CPC分类号： H01L22/32 , G01R1/06711 , G01R1/06738 , G01R1/07314 , G01R3/00 , H01L23/13 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes. A method of manufacturing the semiconductor inspection apparatus comprises the steps of forming a cover film on a surface of the silicon substrate and forming a plurality of probes of a polygonal cone shape or a circular cone shape through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a beam or a diaphragm for each probe through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a through hole corresponding to the probe through etching after patterning by photolithography, and after the cover film is removed, forming an insulating film on the surface of the silicon substrate, forming a metal film on a surface of the insulating film, and forming a wiring lead through etching after patterning by photolithography.

4. 发明授权

US06573112B2 Semiconductor device manufacturing method 失效
公开(公告)号：US06573112B2
公开(公告)日：2003-06-03
申请号：US10238690
申请日：2002-09-11
申请人： Ryuji Kono , Akihiko Ariga , Hideyuki Aoki , Hiroyuki Ohta , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Shinji Tanaka , Naoto Ban , Hideo Miura
发明人： Ryuji Kono , Akihiko Ariga , Hideyuki Aoki , Hiroyuki Ohta , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Shinji Tanaka , Naoto Ban , Hideo Miura
IPC分类号： H01L2166
CPC分类号： H01L21/6836 , H01L22/20 , H01L2221/68327 , H01L2924/0002 , H01L2924/014 , H01L2924/00
摘要： Semiconductor device chips manufacturing and inspecting method is disclosed in which a semiconductor wafer is cut into individual LSI chips. The LSI chips are rearranged and integrated into a predetermined number. The cut LSI chips are integrated in a jig having openings with a size commensurate with the dimensions of the LSI chip. At least one part of the jig having such openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chips. The integrated predetermined number of chips are subjected to an inspection process in a subsequent inspection step thereby improving efficiency and reducing cost.

5. 发明授权

US06479305B2 Semiconductor device manufacturing method 失效
标题翻译：半导体器件制造方法
公开(公告)号：US06479305B2
公开(公告)日：2002-11-12
申请号：US09396732
申请日：1999-09-15
申请人： Ryuji Kono , Akihiko Ariga , Hideyuki Aoki , Hiroyuki Ohta , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Shinji Tanaka , Naoto Ban , Hideo Miura
发明人： Ryuji Kono , Akihiko Ariga , Hideyuki Aoki , Hiroyuki Ohta , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Shinji Tanaka , Naoto Ban , Hideo Miura
IPC分类号： H01L2166
CPC分类号： H01L21/6836 , H01L22/20 , H01L2221/68327 , H01L2924/0002 , H01L2924/014 , H01L2924/00
摘要： Semiconductor device chips manufacturing and inspecting method is disclosed in which a semiconductor wafer is cut into individual LSI chips. The LSI chips are rearranged and integrated into a predetermined number. The cut LSI chips are integrated in a jig having openings with a size commensurate with the dimensions of the LSI chip. At least one part of the jig having such openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chips. The integrated predetermined number of chips are subjected to an inspection process in a subsequent inspection step thereby improving efficiency and reducing cost.
摘要翻译：半导体器件芯片制造和检查方法被公开，其中将半导体晶片切割成单独的LSI芯片。 LSI芯片重新排列并集成为预定数量。切割的LSI芯片集成在具有与LSI芯片的尺寸相当的尺寸的开口的夹具中。具有这种开口的夹具的至少一部分具有与LSI芯片大致相同的热膨胀系数。综合预定数量的芯片在随后的检查步骤中进行检查处理，从而提高效率并降低成本。

6. 发明授权

US06507204B1 Semiconductor testing equipment with probe formed on a cantilever of a substrate 失效
标题翻译：具有探针的半导体测试设备形成在基板的悬臂上
公开(公告)号：US06507204B1
公开(公告)日：2003-01-14
申请号：US09522477
申请日：2000-03-09
申请人： Masatoshi Kanamaru , Yoshishige Endo , Atsushi Hosogane , Tatsuya Nagata , Ryuji Kohno , Hideyuki Aoki , Akihiko Ariga
发明人： Masatoshi Kanamaru , Yoshishige Endo , Atsushi Hosogane , Tatsuya Nagata , Ryuji Kohno , Hideyuki Aoki , Akihiko Ariga
IPC分类号： G01R3102
CPC分类号： G01R1/06733 , G01R1/06727 , G01R1/06738 , G01R1/06761 , G01R1/06772 , G01R1/07342 , G01R3/00
摘要： The conventional semiconductor element testing equipment is arranged to position each probe accurately and need a burdensome operation for fixing, and includes only a limited number of electrode pads and chips to be tested at a batch. An equipment for testing a semiconductor element is arranged to keep each of electrode pads formed on a semiconductor element to be tested in direct contact with each of probes formed on a first substrate composed of silicon, one of electric connecting substrates disposed in the equipment. On the first substrate, each probe is formed on a cantilever and a wire is routed from a tip of each probe along a tip of the cantilever to the electrode pad formed on an opposite surface to the probe forming surface through an insulating layer.
摘要翻译：常规的半导体元件测试设备被布置成准确地定位每个探针，并且需要用于固定的繁重的操作，并且仅包括有限数量的待批测试的电极焊盘和芯片。布置了用于测试半导体元件的设备，以使每个形成在要测试的半导体元件上的电极焊盘与形成在由设置在设备中的电连接基板之一的硅构成的第一基板上形成的每个探针直接接触。在第一基板上，每个探针形成在悬臂上，并且从每个探针的尖端沿着悬臂的尖端布线到通过绝缘层与探针形成表面相对的表面上形成的电极焊盘。

7. 发明授权

US06531327B2 Method for manufacturing semiconductor device utilizing semiconductor testing equipment 失效
公开(公告)号：US06531327B2
公开(公告)日：2003-03-11
申请号：US10073343
申请日：2002-02-13
申请人： Masatoshi Kanamaru , Yoshishige Endo , Atsushi Hosogane , Tatsuya Nagata , Ryuji Kohno , Hideyuki Aoki , Akihiko Ariga
发明人： Masatoshi Kanamaru , Yoshishige Endo , Atsushi Hosogane , Tatsuya Nagata , Ryuji Kohno , Hideyuki Aoki , Akihiko Ariga
IPC分类号： H01L2166
CPC分类号： G01R1/06733 , G01R1/06727 , G01R1/06738 , G01R1/06761 , G01R1/06772 , G01R1/07342 , G01R3/00
摘要： A method for manufacturing a semiconductor device includes forming an integrated circuit on a surface of a wafer and testing electric characteristic of the integrated circuit. The testing includes positioning each of probes of a semiconductor testing equipment and each of electrodes of a tested semiconductor element with each other, and allowing each of the probes to come into contact with each of the electrodes. The semiconductor testing equipment includes a first substrate having a cantilever, the probes being formed on the cantilever of the first substrate, and wires for electrically connecting the probes to electrode pads which are formed on an opposite side of the first substrate to a side on which the probes are formed. Each of the wires has a region arranged on an insulating layer, which is formed on the cantilever, on the opposite side.

8. 发明授权

US06774654B2 Semiconductor-device inspecting apparatus and a method for manufacturing the same 失效
标题翻译：半导体装置检查装置及其制造方法
公开(公告)号：US06774654B2
公开(公告)日：2004-08-10
申请号：US10316828
申请日：2002-12-12
申请人： Masatoshi Kanamaru , Yoshishige Endo , Takanorr Aono , Ryuji Kohno , Toshio Miyatake , Hideyuki Aoki , Naoto Ban
发明人： Masatoshi Kanamaru , Yoshishige Endo , Takanorr Aono , Ryuji Kohno , Toshio Miyatake , Hideyuki Aoki , Naoto Ban
IPC分类号： G01R3102
CPC分类号： G01R1/07357 , Y10S977/874
摘要： A semiconductor inspecting apparatus having a plurality of electrical connection boards arranged in the inspecting apparatus and a plurality of probes respectively provided on a plurality of beams formed on a first board of said plurality of electrical connection boards, the probes being adapted to be individually brought into contact with a plurality of electrode pads of a semiconductor device for inspection, so as to inspect the semiconductor device while establishing electrical connection therebetween. A one-end supported beam is used as each of the beams, and each of the probes is formed at a portion shifted in a rectangular direction to a center line of a longitudinal direction of the one-end supported beam.
摘要翻译：一种具有布置在检查装置中的多个电连接板和分别设置在形成在所述多个电连接板的第一板上的多个梁上的多个探针的半导体检查装置，所述探针适于单独地进入与用于检查的半导体器件的多个电极焊盘接触，以便在其间建立电连接的同时检查半导体器件。使用一端支撑梁作为每个梁，并且每个探针形成在沿着矩形方向偏移到一端支撑梁的纵向方向的中心线的部分。

9. 发明授权

US06828810B2 Semiconductor device testing apparatus and method for manufacturing the same 失效
标题翻译：半导体器件测试装置及其制造方法
公开(公告)号：US06828810B2
公开(公告)日：2004-12-07
申请号：US10207145
申请日：2002-07-30
申请人： Masatoshi Kanamaru , Yoshishige Endo , Takanori Aono , Ryuji Kohno , Hiroya Shimizu , Naoto Ban , Hideyuki Aoki
发明人： Masatoshi Kanamaru , Yoshishige Endo , Takanori Aono , Ryuji Kohno , Hiroya Shimizu , Naoto Ban , Hideyuki Aoki
IPC分类号： G01R3102
CPC分类号： G01R1/0466
摘要： A semiconductor device testing apparatus is realized, which allows contactors to be positioned throughout the wafer surface highly accurately for uniform contact, testing a large-sized wafer, and cost reduction. A plurality of divided contactor blocks is formed with a positioning groove. The groove is used to position the plurality of contactor blocks with a positioning frame. Because the contactor blocks are divided into plurals, it is less likely that a partial surface distortion affects other portions to impair surface flatness as compared with the case where a plurality of non-divided contactors is formed integrally, and the plurality of contactor blocks can be brought into contact with a wafer to be tested uniformly. Additionally, even though abnormality is generated in a part of the contactor blocks, only the part of the contactor blocks is replaced. Therefore, replacement costs can be reduced as compared with the case where a plurality of non-divided contactors is formed integrally.
摘要翻译：实现半导体器件测试装置，其允许接触器高精度地定位在整个晶片表面，用于均匀接触，测试大尺寸晶片以及降低成本。多个分开的接触器块形成有定位槽。凹槽用于定位具有定位框架的多个接触器块。由于接触器块被分成多个，与多个非分隔接触器形成为一体的情况相比，部分表面变形对其他部分的影响较小可能损害表面平坦度，并且多个接触器块可以与待测试的晶片均匀接触。此外，即使在接触器块的一部分中产生异常，仅更换接触器块的一部分。因此，与多个非分割接触器一体形成的情况相比，可以降低更换成本。

10. 发明授权

US06496023B1 Semiconductor-device inspecting apparatus and a method for manufacturing the same 失效
标题翻译：半导体装置检查装置及其制造方法
公开(公告)号：US06496023B1
公开(公告)日：2002-12-17
申请号：US09722484
申请日：2000-11-28
申请人： Masatoshi Kanamaru , Yoshishige Endo , Takanorr Aono , Ryuji Kohno , Toshio Miyatake , Hideyuki Aoki , Naoto Ban
发明人： Masatoshi Kanamaru , Yoshishige Endo , Takanorr Aono , Ryuji Kohno , Toshio Miyatake , Hideyuki Aoki , Naoto Ban
IPC分类号： G01R3102
CPC分类号： G01R1/07357 , Y10S977/874
摘要： A structure is provided such that a plural cantilevers are formed on a first board formed of silicon, probes are respectively formed on the individual cantilevers at positions each offset perpendicularly to a longitudinal center line of the cantilever, and wiring connected continuously from each probe to a secondary electrode pad portion through an insulating layer. A structure is alternatively adopted such that by using a both-ends supported beam formed of silicon as the beam, each probe is formed at a position offset toward a supported portion side of the both-ends supported beam.
摘要翻译：提供一种结构，使得在由硅形成的第一板上形成多个悬臂，在各个悬臂分别在垂直于悬臂的纵向中心线偏移的位置处形成探针，并且从每个探针连续连接到每个探针次级电极焊盘部分穿过绝缘层。可替代地采用结构，使得通过使用由硅形成的两端支撑梁作为梁，每个探针形成在朝向两端支撑梁的支撑部分侧偏移的位置。

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