专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08397112B2 Test chain testability in a system for testing tri-state functionality 有权
标题翻译：用于测试三态功能的系统中的测试链可测性
公开(公告)号：US08397112B2
公开(公告)日：2013-03-12
申请号：US12969939
申请日：2010-12-16
申请人： Mujibur Rahman , Timothy Anderson , Alan Hales
发明人： Mujibur Rahman , Timothy Anderson , Alan Hales
IPC分类号： G01R31/28
CPC分类号： G01R31/31715
摘要： An embodiment of the invention provides system for detecting faults on a test chain. A circuit provides a test signal to an input of a test chain. The test chain includes a plurality of buffers connected in series. A register receives a logical value representing the output of the test chain. The register sends the logical value representing the output of the test chain to test circuitry where the value is observed.
摘要翻译：本发明的实施例提供了一种用于检测测试链上的故障的系统。电路向测试链的输入端提供测试信号。测试链包括串联连接的多个缓冲器。寄存器接收表示测试链输出的逻辑值。寄存器将表示测试链的输出的逻辑值发送到测量电路，其中观察到该值。

2. 发明申请

US20120036408A1 Test Chain Testability In a System for Testing Tri-State Functionality 有权
标题翻译：用于测试三态功能的系统中的测试链可测试性
公开(公告)号：US20120036408A1
公开(公告)日：2012-02-09
申请号：US12969939
申请日：2010-12-16
申请人： Mujibur Rahman , Timothy Anderson , Alan Hales
发明人： Mujibur Rahman , Timothy Anderson , Alan Hales
IPC分类号： G06F11/27 , G01R31/28
CPC分类号： G01R31/31715
摘要： An embodiment of the invention provides system for detecting faults on a test chain. A circuit provides a test signal to an input of a test chain. The test chain includes a plurality of buffers connected in series. A register receives a logical value representing the output of the test chain. The register sends the logical value representing the output of the test chain to test circuitry where the value is observed.
摘要翻译：本发明的实施例提供了一种用于检测测试链上的故障的系统。电路向测试链的输入端提供测试信号。测试链包括串联连接的多个缓冲器。寄存器接收表示测试链输出的逻辑值。寄存器将表示测试链的输出的逻辑值发送到测量电路，其中观察到该值。

3. 发明申请

US20130169332A1 Family of Multiplexer/Flip-Flops with Enhanced Testability 有权
标题翻译：具有增强可测性的多路复用器/触发器系列
公开(公告)号：US20130169332A1
公开(公告)日：2013-07-04
申请号：US12796949
申请日：2010-06-09
申请人： Mujibur Rahman , Timothy D. Anderson , Alan Hales
发明人： Mujibur Rahman , Timothy D. Anderson , Alan Hales
IPC分类号： H03K3/356
CPC分类号： H03K3/356 , H03K3/356052
摘要： A multibit combined multiplexer and flip-flop circuit has a plurality of bit circuits. Each bit circuit includes and input section, a flip-flop section and a per bit control section. The input sections have inputs for plural of input signals and corresponding input pass gates. The outputs of the input pass gates are connected to the input of the flip-flop section. Each per bit control section includes an inverter for each input terminal. There is a combined control section receiving a clock signal and a control signals for selection of only one of the input signals. The combined control section include a logical AND for each input signal combining the clock signal and the selection signal. The output of each logical AND is connected to the input of a corresponding inverter of each per bit control circuit. The input pass gate are controlled by a corresponding logical AND and said corresponding inverter.
摘要翻译：多位组合多路复用器和触发器电路具有多个位电路。每个位电路包括和输入部分，触发器部分和每位控制部分。输入部分具有用于多个输入信号和相应的输入传递门的输入。输入通过门的输出端连接到触发器部分的输入端。每个位控制部分包括用于每个输入端的反相器。存在组合控制部分，其接收时钟信号和用于仅选择一个输入信号的控制信号。组合控制部分包括组合时钟信号和选择信号的每个输入信号的逻辑“与”。每个逻辑AND的输出连接到每个位每个控制电路的相应反相器的输入端。输入通道门由对应的逻辑与和相应的反相器控制。

4. 发明授权

US08525565B2 Family of multiplexer/flip-flops with enhanced testability 有权
标题翻译：具有增强可测性的多路复用器/触发器系列
公开(公告)号：US08525565B2
公开(公告)日：2013-09-03
申请号：US12796949
申请日：2010-06-09
申请人： Mujibur Rahman , Timothy D. Anderson , Alan Hales
发明人： Mujibur Rahman , Timothy D. Anderson , Alan Hales
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356 , H03K3/356052
摘要： A multibit combined multiplexer and flip-flop circuit has a plurality of bit circuits. Each bit circuit includes and input section, a flip-flop section and a per bit control section. The input sections have inputs for plural of input signals and corresponding input pass gates. The outputs of the input pass gates are connected to the input of the flip-flop section. Each per bit control section includes an inverter for each input terminal. There is a combined control section receiving a clock signal and a control signals for selection of only one of the input signals. The combined control section include a logical AND for each input signal combining the clock signal and the selection signal. The output of each logical AND is connected to the input of a corresponding inverter of each per bit control circuit. The input pass gate are controlled by a corresponding logical AND and said corresponding inverter.
摘要翻译：多位组合多路复用器和触发器电路具有多个位电路。每个位电路包括和输入部分，触发器部分和每位控制部分。输入部分具有用于多个输入信号和相应的输入传递门的输入。输入通过门的输出端连接到触发器部分的输入端。每个位控制部分包括用于每个输入端的反相器。存在组合控制部分，其接收时钟信号和用于仅选择一个输入信号的控制信号。组合控制部分包括组合时钟信号和选择信号的每个输入信号的逻辑“与”。每个逻辑AND的输出连接到每个位每个控制电路的相应反相器的输入端。输入通道门由对应的逻辑与和相应的反相器控制。

5. 发明申请

US20050186726A1 Scan testing system, method and apparatus 有权
标题翻译：扫描测试系统，方法和设备
公开(公告)号：US20050186726A1
公开(公告)日：2005-08-25
申请号：US11103781
申请日：2005-04-11
申请人： Lee Whetsel , Alan Hales
发明人： Lee Whetsel , Alan Hales
IPC分类号： G01R31/3185 , G01R31/26
CPC分类号： G01R31/3177 , G01R1/07342 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318566 , G01R31/318572 , G01R31/31924 , G01R31/31926
摘要： Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
摘要翻译：位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3以上）可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出芯片/ IC输出。除功能测试外，还可以对芯片和IC进行扫描测试。

6. 发明申请

US20110041019A1 SCAN TESTING SYSTEM, METHOD AND APPARATUS 有权
标题翻译：扫描测试系统，方法和设备
公开(公告)号：US20110041019A1
公开(公告)日：2011-02-17
申请号：US12911424
申请日：2010-10-25
申请人： Lee D. Whetsel , Alan Hales
发明人： Lee D. Whetsel , Alan Hales
IPC分类号： G06F11/00
CPC分类号： G01R31/3177 , G01R1/07342 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318566 , G01R31/318572 , G01R31/31924 , G01R31/31926
摘要： Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
摘要翻译：位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3以上）可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出芯片/ IC输出。除功能测试外，还可以对芯片和IC进行扫描测试。

7. 发明授权

US07842949B2 IC with comparator receiving expected and mask data from pads 有权
公开(公告)号：US07842949B2
公开(公告)日：2010-11-30
申请号：US12638441
申请日：2009-12-15
申请人： Lee D. Whetsel , Alan Hales
发明人： Lee D. Whetsel , Alan Hales
IPC分类号： H01L23/58
CPC分类号： G01R31/3177 , G01R1/07342 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318566 , G01R31/318572 , G01R31/31924 , G01R31/31926
摘要： Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

8. 发明授权

US07655946B2 IC with comparator receiving expected and mask data from pads 有权
标题翻译： IC与比较器接收来自焊盘的预期和掩模数据
公开(公告)号：US07655946B2
公开(公告)日：2010-02-02
申请号：US12329957
申请日：2008-12-08
申请人： Lee D. Whetsel , Alan Hales
发明人： Lee D. Whetsel , Alan Hales
IPC分类号： H01L23/58
CPC分类号： G01R31/3177 , G01R1/07342 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318566 , G01R31/318572 , G01R31/31924 , G01R31/31926
摘要： Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
摘要翻译：位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3）都可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出芯片/ IC输出。除功能测试外，还可以对芯片和IC进行扫描测试。

9. 发明申请

US20060259838A1 Scan Sequenced Power-On Initialization 有权
标题翻译：扫描顺序上电初始化
公开(公告)号：US20060259838A1
公开(公告)日：2006-11-16
申请号：US11381624
申请日：2006-05-04
申请人： Lewis Nardini , Alan Hales
发明人： Lewis Nardini , Alan Hales
IPC分类号： G01R31/28
CPC分类号： G01R31/318575
摘要： A scan sequenced initialization technique supplies a predefined power-on state to a device or module without using explicit reset input to the registers. This invention supplies a predefined pattern to parallel scan chains following power-on reset. These parallel scan chains are already required for structural manufacturing test. Once the power-on reset scanning is complete, the power-on reset sequencer indicates completion of state initialization to other circuits. These other circuits are those which interact with the module or device using this invention.
摘要翻译：扫描顺序初始化技术将预定义的开机状态提供给设备或模块，而不使用对寄存器的显式复位输入。本发明在上电复位后将预定义的模式提供给并行扫描链。这些平行扫描链已经是结构制造测试所必需的。一旦上电复位扫描完成，上电复位定序器就会指示完成其他电路的状态初始化。这些其他电路是与使用本发明的模块或装置相互作用的电路。

10. 发明申请

US20050204217A1 Identical core testing using dedicated compare and mask circuitry 审中-公开
标题翻译：使用专用比较和掩码电路的相同核心测试
公开(公告)号：US20050204217A1
公开(公告)日：2005-09-15
申请号：US11051696
申请日：2005-02-04
申请人： Lee Whetsel , Alan Hales
发明人： Lee Whetsel , Alan Hales
IPC分类号： G01R31/28
CPC分类号： G01R31/2884 , G01R31/3193
摘要： Today large system-on-chips (SOC) are designed using predefined circuit functions commonly referred to as cores. In some cases, multiple instances of the same core may be implemented within an SOC to achieve greater functional performance of the SOC. Having multiple cores of the same type in an SOC lends itself to parallel testing of the cores. This disclosure describes an improved core DFT architecture that facilitates parallel testing of same type cores within an SOC.
摘要翻译：今天，大型片上系统（SOC）使用通常称为内核的预定义电路功能进行设计。在一些情况下，可以在SOC内实现相同核心的多个实例以实现SOC的更大的功能性能。在SOC中具有相同类型的多个核可以自己进行核的并行测试。本公开描述了一种改进的核心DFT架构，其有助于SOC内的同类型核的并行测试。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式