专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060068529A1 Self-aligned split-gate NAND flash memory and fabrication process 有权
公开(公告)号：US20060068529A1
公开(公告)日：2006-03-30
申请号：US11281182
申请日：2005-11-16
申请人： Chiou-Feng Chen , Caleb Yu-Sheng Cho , Ming-Jer Chen , Der-Tsyr Fan , Prateep Tuntasood
发明人： Chiou-Feng Chen , Caleb Yu-Sheng Cho , Ming-Jer Chen , Der-Tsyr Fan , Prateep Tuntasood
IPC分类号： H01L21/8232
CPC分类号： G11C16/0483 , G11C2216/04 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

2. 发明授权

US06069050A Cross-coupled capacitors for improved voltage coefficient 失效
标题翻译：交叉耦合电容，提高电压系数
公开(公告)号：US06069050A
公开(公告)日：2000-05-30
申请号：US953530
申请日：1997-10-20
申请人： Chin-Shan Hou , Ming-Jer Chen
发明人： Chin-Shan Hou , Ming-Jer Chen
IPC分类号： H01L27/08 , H01L21/20
CPC分类号： H01L27/0805
摘要： A capacitor having a low voltage coefficient, even though one electrode is a semiconductor and one is a metal, is described. Two parallel plate capacitors are formed side by side and then cross-connected. The bottom plate of one of the capacitors is connected to the top plate of the other capacitor, and vice versa. This arrangement causes the two capacitors to be polarized in opposite directions at all times so that the individual voltage coefficients cancel each other and give the combined structure a value that is about 2 ppm/V. A process for manufacturing this capacitor is also described.
摘要翻译：即使一个电极是半导体，也是一个是金属，具有低电压系数的电容器被描述。两个平行的平板电容器并排形成，然后交叉连接。一个电容器的底板连接到另一个电容器的顶板，反之亦然。这种布置使得两个电容器始终在相反的方向上被极化，使得各个电压系数彼此抵消，并使组合结构的值为约2ppm / V。还描述了用于制造该电容器的工艺。

3. 发明授权

US06992929B2 Self-aligned split-gate NAND flash memory and fabrication process 有权
标题翻译：自对准分闸门NAND闪存和制造工艺
公开(公告)号：US06992929B2
公开(公告)日：2006-01-31
申请号：US10803183
申请日：2004-03-17
申请人： Chiou-Feng Chen , Caleb Yu-Sheng Cho , Ming-Jer Chen , Der-Tsyr Fan , Prateep Tuntasood
发明人： Chiou-Feng Chen , Caleb Yu-Sheng Cho , Ming-Jer Chen , Der-Tsyr Fan , Prateep Tuntasood
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C2216/04 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.
摘要翻译：自对准分裂栅极NAND闪速存储单元阵列及其制造工艺，其中自对准分裂栅极单元行在衬底的有源区域中的位线扩散与公共源极扩散之间形成。每个单元具有彼此堆叠和自对准的控制和浮置栅极，并且擦除和选择与层叠栅极分离并与堆叠栅极自对准的栅极，每行的两端的选择栅极部分地重叠位排列源扩散。擦除栅极下面的沟道区域是重掺杂的，以减小位线和源极扩散之间的沟道电阻，并且浮置栅极以其它栅极包围，从而提供显着增强的与浮栅的高电压耦合其他大门。存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

4. 发明授权

US5594683A SRAM cell using a CMOS compatible high gain gated lateral BJT 失效
标题翻译： SRAM单元采用CMOS兼容的高增益门控侧向BJT
公开(公告)号：US5594683A
公开(公告)日：1997-01-14
申请号：US418485
申请日：1995-04-07
申请人： Ming-Jer Chen , Tzuen-Hsi Huang
发明人： Ming-Jer Chen , Tzuen-Hsi Huang
IPC分类号： G11C11/40 , H01L27/11 , G11C11/34
CPC分类号： G11C11/40 , H01L27/11 , Y10S257/903
摘要： This invention presents a new SRAM cell comprising only two MOSFETs: one is the access device for data transfer; and the other is operated as a high gain gated lateral BJT in the reverse base current mode so as to constitute the role of the storage flip-flop or latch. This invention also requires only one-sided peripheral circuitry for Read/Write function. Thus the chip area is greatly saved. In addition, the invention is fully compatible with the existing low-cost, high-yield standard CMOS process.
摘要翻译：本发明提出了一种仅包括两个MOSFET的新型SRAM单元：一个是用于数据传输的存取设备; 另一个在反向基极电流模式下作为高增益门控横向BJT运行，从而构成存储触发器或锁存器的作用。本发明也仅需要用于读/写功能的单面外围电路。因此，芯片面积大大节省。此外，本发明与现有的低成本，高产量的标准CMOS工艺完全兼容。

5. 发明授权

US07217621B2 Self-aligned split-gate NAND flash memory and fabrication process 有权
标题翻译：自对准分闸门NAND闪存和制造工艺
公开(公告)号：US07217621B2
公开(公告)日：2007-05-15
申请号：US11281182
申请日：2005-11-16
申请人： Chiou-Feng Chen , Caleb Yu-Sheng Cho , Ming-Jer Chen , Der-Tsyr Fan , Prateep Tuntasood
发明人： Chiou-Feng Chen , Caleb Yu-Sheng Cho , Ming-Jer Chen , Der-Tsyr Fan , Prateep Tuntasood
IPC分类号： H01L21/336
CPC分类号： G11C16/0483 , G11C2216/04 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.
摘要翻译：自对准分裂栅极NAND闪速存储单元阵列及其制造工艺，其中自对准分裂栅极单元行在衬底的有源区域中的位线扩散与公共源极扩散之间形成。每个单元具有彼此堆叠和自对准的控制和浮置栅极，并且擦除和选择与层叠栅极分离并与堆叠栅极自对准的栅极，每行的两端的选择栅极部分地重叠位排列源扩散。擦除栅极下面的沟道区域是重掺杂的，以减小位线和源极扩散之间的沟道电阻，并且浮置栅极以其它栅极包围，从而提供显着增强的与浮栅的高电压耦合其他大门。存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

6. 发明授权

US5644266A Dynamic threshold voltage scheme for low voltage CMOS inverter 失效
标题翻译：低压CMOS逆变器的动态阈值电压方案
公开(公告)号：US5644266A
公开(公告)日：1997-07-01
申请号：US559201
申请日：1995-11-13
申请人： Ming-Jer Chen , Chuang-Hen Yang
发明人： Ming-Jer Chen , Chuang-Hen Yang
IPC分类号： H03K19/00 , H03K19/017 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/0027 , H03K19/0013 , H03K19/01707 , H03K2217/0018
摘要： The present invention utilizes a CMOS (complementary metal-oxide-semiconductor) inverter, which includes a PMOS transistor and an NMOS transistor connected in cascade, and back-gate biasing circuits. The back-gate biasing circuit consists of capacitors and loads (active load or passive load). By providing a bias voltage to either one of bulks of the transistors or both of them, the constituted CMOS inverter demonstrates higher operation speed and lower standby current than the conventional one.
摘要翻译：本发明使用包括PMOS串联连接的PMOS晶体管和NMOS晶体管的CMOS（互补金属氧化物半导体）逆变器和背栅极偏置电路。背栅极偏置电路由电容器和负载（有源负载或被动负载）组成。通过向晶体管或其两者的体积中的任一个提供偏置电压，构成的CMOS反相器表现出比常规CMOS反相器更高的操作速度和更低的待机电流。

7. 发明授权

US5479121A Compensating circuit for MOSFET analog switches 失效
标题翻译： MOSFET模拟开关补偿电路
公开(公告)号：US5479121A
公开(公告)日：1995-12-26
申请号：US394771
申请日：1995-02-27
申请人： Wei-Chen Shen , Yen-Bin Gu , Chu-Chang Lin , Ming-Jer Chen , Po-Chin Hsu , Tien-Yu Wu
发明人： Wei-Chen Shen , Yen-Bin Gu , Chu-Chang Lin , Ming-Jer Chen , Po-Chin Hsu , Tien-Yu Wu
IPC分类号： G11C27/02
CPC分类号： G11C27/026
摘要： This invention deals with the problem of an error voltage in a MOSFET analog switch sample and hold circuit caused by the turn off charge in the MOSFET analog switch. The invention provides a compensating circuit which can be adjusted to exactly compensate for the turn off charge which causes the error so that the error can be reduced to zero or nearly zero. The compensating circuit can be used in both open loop and closed loop sample and hold circuits. The compensating circuit can be used in combination with a Miller feedback circuit for eliminating the error voltage.
摘要翻译：本发明涉及由MOSFET模拟开关中的关断电荷引起的MOSFET模拟开关采样和保持电路中的误差电压的问题。本发明提供一种补偿电路，其可被调整以精确地补偿导致误差的关断电荷，使得误差可以降低到零或接近零。补偿电路可用于开环和闭环采样保持电路。补偿电路可以与米勒反馈电路组合使用，以消除误差电压。

8. 发明申请

US20050207225A1 Self-aligned split-gate NAND flash memory and fabrication process 有权
标题翻译：自对准分闸门NAND闪存和制造工艺
公开(公告)号：US20050207225A1
公开(公告)日：2005-09-22
申请号：US10803183
申请日：2004-03-17
申请人： Chiou-Feng Chen , Caleb Cho , Ming-Jer Chen , Der-Tsyr Fan , Prateep Tuntasood
发明人： Chiou-Feng Chen , Caleb Cho , Ming-Jer Chen , Der-Tsyr Fan , Prateep Tuntasood
IPC分类号： G11C16/00 , G11C16/04 , H01L21/8247 , H01L27/105 , H01L27/115
CPC分类号： G11C16/0483 , G11C2216/04 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.
摘要翻译：自对准分裂栅极NAND闪速存储单元阵列及其制造工艺，其中自对准分裂栅极单元行在衬底的有源区域中的位线扩散与公共源极扩散之间形成。每个单元具有彼此堆叠和自对准的控制和浮置栅极，并且擦除和选择与层叠栅极分离并与堆叠栅极自对准的栅极，每行的两端的选择栅极部分地重叠位排列源扩散。擦除栅极下面的沟道区域是重掺杂的，以减小位线和源极扩散之间的沟道电阻，并且浮置栅极以其它栅极包围，从而提供显着增强的与浮栅的高电压耦合其他大门。存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

9. 发明授权

US06222221B1 Cross-coupled capacitors for improved voltage coefficient 有权
标题翻译：交叉耦合电容，提高电压系数
公开(公告)号：US06222221B1
公开(公告)日：2001-04-24
申请号：US09439356
申请日：1999-11-15
申请人： Chin-Shan Hou , Ming-Jer Chen
发明人： Chin-Shan Hou , Ming-Jer Chen
IPC分类号： H01L27108
CPC分类号： H01L27/0805
摘要： A capacitor having a low voltage coefficient, even though one electrode is a semiconductor and one is a metal, is described. Two parallel plate capacitors are formed side by side and then cross-connected. The bottom plate of one of the capacitors is connected to the top plate of the other capacitor, and vice versa. This arrangement causes the two capacitors to be polarized in opposite directions at all times so that the individual voltage coefficients cancel each other and give the combined structure a value that is about 2 ppm V. A process for manufacturing this capacitor is also described.
摘要翻译：即使一个电极是半导体，也是一个是金属，具有低电压系数的电容器被描述。两个平行的平板电容器并排形成，然后交叉连接。一个电容器的底板连接到另一个电容器的顶板，反之亦然。这种布置使得两个电容器总是在相反的方向上被极化，使得各个电压系数相互抵消，并使组合结构的值为大约2ppm V.还描述了制造该电容器的工艺。

10. 发明授权

US6072677A Electrostatic discharge protective circuit formed by use of a silicon controlled rectifier 有权
标题翻译：使用可控硅整流器形成的静电放电保护电路
公开(公告)号：US6072677A
公开(公告)日：2000-06-06
申请号：US184897
申请日：1998-11-03
申请人： Mainn-Gwo Chen , Ming-Jer Chen , Chuan H. Liu
发明人： Mainn-Gwo Chen , Ming-Jer Chen , Chuan H. Liu
IPC分类号： H01L27/02 , H02H9/04
CPC分类号： H01L27/0259 , H01L27/0251
摘要： An electrostatic discharge protective circuit formed by use of a silicon controller rectifier is coupled to an input port and an internal circuit for discharging electrostatic charges on the input port to ground. When the electrostatic charges are applied on the input port, a punch-through effect is created between a first P-type diffusion region and a second N-type diffusion region to turn on a parasitic NPN bipolar junction transistor. At the same time, a voltage is applied on a gate of the MOS transistor via a small-signal equivalent capacitor to turn on itself, thereby discharging the electrostatic charges. Accordingly, the trigger voltage of the silicon controller rectifier can be efficiently lowered to improve the electrostatic discharge protective capability of the silicon control rectifier.
摘要翻译：通过使用硅控制器整流器形成的静电放电保护电路耦合到输入端口和内部电路，用于将输入端口上的静电电荷排放到地。当静电电荷施加到输入端口时，在第一P型扩散区域和第二N型扩散区域之间产生穿透效应，以接通寄生NPN双极结型晶体管。同时，通过小信号等效电容器在MOS晶体管的栅极上施加电压以使其自身导通，从而放电静电电荷。因此，可以有效地降低硅控制整流器的触发电压，以提高硅控整流器的静电放电保护能力。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式