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1. 发明授权

US09899538B1 Non-volatile memory device and operation method thereof 有权
公开(公告)号：US09899538B1
公开(公告)日：2018-02-20
申请号：US15591126
申请日：2017-05-10
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chun-Lung Chang , Tien-Fan Ou
IPC分类号： H01L27/115 , H01L29/788 , H01L27/11521 , H01L29/417 , G11C16/14 , G11C16/10 , G11C16/26 , G11C16/04
CPC分类号： H01L29/7884 , G11C16/0408 , G11C16/0416 , G11C16/10 , G11C16/14 , G11C16/26 , G11C2216/04 , H01L27/115 , H01L27/11521 , H01L29/41775 , H01L29/42328
摘要： The present invention provides a non-volatile memory device, including a source region and a drain region, a channel region, a floating gate, an enhance hot carrier (hole or electron) injection gate and an erasing gate. The floating gate is disposed on the channel region and the source region and a first dielectric layer is disposed therebetween. The enhance hot carrier injection gate is disposed on the floating gate and the substrate wherein the enhance hot carrier injection gate has an L-shape cross-section. A second dielectric layer is disposed between the enhance hot carrier injection gate and the floating gate, and a fourth dielectric layer is disposed between the enhance hot carrier injection gate and the substrate. The erasing gate is disposed on the drain region. A third dielectric layer is disposed between the erasing gate and the substrate.

2. 发明授权

US09401217B2 Flash memory with improved read performance 有权
标题翻译：具有改进的读取性能的闪存
公开(公告)号：US09401217B2
公开(公告)日：2016-07-26
申请号：US14470359
申请日：2014-08-27
申请人： Anirban Roy , Jon S. Choy
发明人： Anirban Roy , Jon S. Choy
IPC分类号： G11C16/26 , G11C29/02 , G11C16/30 , G11C16/34
CPC分类号： G11C16/26 , G11C16/30 , G11C16/3445 , G11C16/3459 , G11C16/349 , G11C29/021 , G11C29/028 , G11C2216/04
摘要： A non-volatile memory device includes an array of memory cells and a plurality of word lines and voltage supply lines. Each memory cell of the array is coupled to one of the word lines. Each of the plurality of voltage supply lines is coupled to a first voltage supply terminal of a subset of memory cells of a plurality of subsets of memory cells of the array. Each subset includes a plurality of memory cells. A voltage switch supplies a respective one of a plurality of aged voltages to each of the plurality of subsets of memory cells in the memory array on respective ones of the voltage supply lines. The aged voltage supplied to a first of the plurality of subsets of memory cells is different than the aged voltage supplied to a second of the plurality of subsets of memory cells.
摘要翻译：非易失性存储器件包括存储器单元阵列和多个字线和电压供应线。阵列的每个存储单元耦合到一行字线。多个电压供给线中的每一个耦合到该阵列的多个存储器单元的子集的存储单元子集的第一电压供应端。每个子集包括多个存储单元。电压开关将多个老化电压中的相应一个向存储器阵列中的各个电压供应线上的多个存储单元子集中的每一个提供。提供给存储器单元的多个子集中的第一个的老化电压与提供给多个存储单元子集中的第二子集的老化电压不同。

3. 发明授权

US08391079B2 EEPROM memory architecture optimized for embedded memories 有权
标题翻译： EEPROM内存架构为嵌入式存储器优化
公开(公告)号：US08391079B2
公开(公告)日：2013-03-05
申请号：US12823901
申请日：2010-06-25
申请人： Francesco La Rosa
发明人： Francesco La Rosa
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0433 , G11C8/12 , G11C16/16 , G11C2216/04
摘要： The present disclosure relates to an electrically erasable and programmable memory comprising rows of memory cells to store words of N bits each, bit lines and word lines, wherein a row of memory cells comprises a first group of memory cells to store collectively erasable words, and at least one second group of memory cells to store one individually erasable word.
摘要翻译：本发明涉及一种电可擦除和可编程存储器，其包括存储单元行，每行存储N位的字，位线和字线，其中一行存储器单元包括第一组存储器单元以存储集体可擦除字，以及至少一个第二组存储器单元，用于存储一个单独的可擦除字。

4. 发明申请

US20050207225A1 Self-aligned split-gate NAND flash memory and fabrication process 有权
标题翻译：自对准分闸门NAND闪存和制造工艺
公开(公告)号：US20050207225A1
公开(公告)日：2005-09-22
申请号：US10803183
申请日：2004-03-17
申请人： Chiou-Feng Chen , Caleb Cho , Ming-Jer Chen , Der-Tsyr Fan , Prateep Tuntasood
发明人： Chiou-Feng Chen , Caleb Cho , Ming-Jer Chen , Der-Tsyr Fan , Prateep Tuntasood
IPC分类号： G11C16/00 , G11C16/04 , H01L21/8247 , H01L27/105 , H01L27/115
CPC分类号： G11C16/0483 , G11C2216/04 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.
摘要翻译：自对准分裂栅极NAND闪速存储单元阵列及其制造工艺，其中自对准分裂栅极单元行在衬底的有源区域中的位线扩散与公共源极扩散之间形成。每个单元具有彼此堆叠和自对准的控制和浮置栅极，并且擦除和选择与层叠栅极分离并与堆叠栅极自对准的栅极，每行的两端的选择栅极部分地重叠位排列源扩散。擦除栅极下面的沟道区域是重掺杂的，以减小位线和源极扩散之间的沟道电阻，并且浮置栅极以其它栅极包围，从而提供显着增强的与浮栅的高电压耦合其他大门。存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

5. 发明申请

US20190206882A1 MEMORIES WITH SOURCE DIFFUSIONS ELECTRICALLY COUPLED TO SOURCE-CONTACTED LAYERS 审中-公开
公开(公告)号：US20190206882A1
公开(公告)日：2019-07-04
申请号：US15859426
申请日：2017-12-30
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： John Howard MacPEAK
IPC分类号： H01L27/11521 , H01L29/08 , H01L29/423 , H01L23/528 , H01L23/522 , H01L29/06 , H01L21/265 , H01L21/768 , H01L21/3213 , H01L29/66 , H01L29/788 , H01L21/28 , H01L29/51 , G11C16/04 , G11C16/26 , G11C16/10 , G11C16/14
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/10 , G11C16/14 , G11C16/26 , G11C2216/04 , H01L21/26513 , H01L21/28273 , H01L21/32133 , H01L21/76802 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L29/0649 , H01L29/0847 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/788
摘要： A memory comprises: a substrate; a dielectric region formed on the substrate; a source-contacted layer formed in the dielectric region; a first source diffusion formed in the substrate; a first drain diffusion formed in the substrate; a first floating gate formed in the dielectric region; a first control gate formed in the dielectric region; a first erase gate formed in the dielectric region; and a first source diffusion via electrically coupling the first source diffusion to the source-contacted layer.

6. 发明申请

US20160240260A1 Flash Memory System Using Complementary Voltage Supplies 有权
标题翻译：使用互补电压源的闪存系统
公开(公告)号：US20160240260A1
公开(公告)日：2016-08-18
申请号：US15135346
申请日：2016-04-21
申请人： Silicon Storage Technology, Inc.
发明人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
IPC分类号： G11C16/14 , G11C16/26 , G11C16/08 , G11C16/10
CPC分类号： G11C16/30 , G11C5/14 , G11C5/145 , G11C5/147 , G11C8/08 , G11C16/0408 , G11C16/0425 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26 , G11C2216/04 , H01L27/11521
摘要： A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.
摘要翻译：非易失性存储器件包括第一导电类型的半导体衬底。非易失性存储单元的阵列位于半导体衬底中并且被布置成多个行和列。每个存储单元包括第二导电类型的半导体衬底的表面上的第一区域和第二导电类型的半导体衬底的表面上的第二区域。沟道区域在第一区域和第二区域之间。字线覆盖在沟道区域的第一部分上，并且与第一区域绝缘，并且与第一区域相邻并且与第一区域几乎没有或没有重叠。浮动栅极覆盖沟道区域的第二部分，与第一部分相邻，并与第二部分绝缘并与第二区域相邻。耦合栅极覆盖浮栅。位线连接到第一区域。在程序，读取或擦除的操作期间，负电压可以被施加到所选择的或未选择的存储单元的字线和/或耦合门。

7. 发明申请

US20160064082A1 SEMICONDUCTOR MEMORY CELL AND DRIVER CIRCUITRY WITH GATE OXIDE FORMED SIMULTANEOUSLY 有权
标题翻译：半导体存储单元和驱动器电路同时形成氧化钇
公开(公告)号：US20160064082A1
公开(公告)日：2016-03-03
申请号：US14470374
申请日：2014-08-27
申请人： CHEONG MIN HONG , Tahmina Akhter , Gilles J. Muller
发明人： CHEONG MIN HONG , Tahmina Akhter , Gilles J. Muller
IPC分类号： G11C16/04 , H01L21/8234 , H01L29/66 , H01L21/265 , G11C16/08 , H01L29/78 , H01L29/423 , H01L21/3213 , G11C16/24 , H01L27/115 , H01L29/788
CPC分类号： G11C16/0433 , G11C16/08 , G11C16/24 , G11C2216/04 , H01L21/26513 , H01L21/823437 , H01L21/823481 , H01L21/823493 , H01L27/11524 , H01L27/11526 , H01L27/11546 , H01L29/42324 , H01L29/42328 , H01L29/66575 , H01L29/66825 , H01L29/7833 , H01L29/788
摘要： The present disclosure provides for semiconductor structures and methods for making semiconductor structures. In one embodiment, isolation regions are formed in a substrate, and wells are formed between the isolation regions. The wells include a first low voltage well and a second low voltage well in a logic region of the substrate, and a memory array well in an NVM region of the substrate. A first layer of oxide is formed over the first low voltage well and the memory array well, and a second layer of oxide is formed over the second low voltage well, the second layer being thinner than the first layer. Gates are formed over the wells, including a first gate over the first low voltage well, a second gate over the second low voltage well, and a memory cell gate over the memory array well. Source/drain extension regions are formed around the gates.
摘要翻译：本公开提供了用于制造半导体结构的半导体结构和方法。在一个实施例中，在衬底中形成隔离区，并且在隔离区之间形成阱。阱包括在衬底的逻辑区域中的第一低电压阱和第二低电压阱以及在衬底的NVM区域中的存储器阵列。在第一低电压阱和存储器阵列上形成第一氧化层，并且在第二低电压阱上形成第二层氧化物，第二层比第一层薄。在井上形成栅极，包括在第一低电压阱上的第一栅极，在第二低电压阱上的第二栅极以及存储器阵列上的存储器单元栅极。在栅极周围形成源极/漏极延伸区域。

8. 发明申请

US20100331045A1 EEPROM MEMORY ARCHITECTURE OPTIMIZED FOR EMBEDDED MEMORIES 有权
标题翻译：用于嵌入式存储器的EEPROM存储器架构优化
公开(公告)号：US20100331045A1
公开(公告)日：2010-12-30
申请号：US12823901
申请日：2010-06-25
申请人： Francesco La Rosa
发明人： Francesco La Rosa
IPC分类号： G11C16/04 , H04W88/02
CPC分类号： G11C16/0433 , G11C8/12 , G11C16/16 , G11C2216/04
摘要： The present disclosure relates to an electrically erasable and programmable memory comprising rows of memory cells to store words of N bits each, bit lines and word lines, wherein a row of memory cells comprises a first group of memory cells to store collectively erasable words, and at least one second group of memory cells to store one individually erasable word.
摘要翻译：本发明涉及一种电可擦除和可编程存储器，其包括存储单元行，每行存储N位的字，位线和字线，其中一行存储器单元包括第一组存储器单元以存储集体可擦除字，以及至少一个第二组存储器单元，用于存储一个单独的可擦除字。

9. 发明申请

US20170098474A1 Fully Depleted Silicon On Insulator Flash Memory Design 有权
公开(公告)号：US20170098474A1
公开(公告)日：2017-04-06
申请号：US14875533
申请日：2015-10-05
申请人： Silicon Storage Technology, Inc.
发明人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
IPC分类号： G11C16/14 , G11C16/26 , G11C16/08
CPC分类号： G11C16/14 , G11C7/065 , G11C8/08 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/28 , G11C2216/04 , H01L27/112 , H01L27/11582 , H01L28/00
摘要： The present invention relates to a flash memory system wherein one or more circuit blocks utilize fully depleted silicon-on-insulator transistor design to minimize leakage

10. 发明授权

US09508443B2 Flash memory system using complementary voltage supplies 有权
标题翻译：闪存系统使用互补电源
公开(公告)号：US09508443B2
公开(公告)日：2016-11-29
申请号：US15135346
申请日：2016-04-21
申请人： Silicon Storage Technology, Inc.
发明人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
IPC分类号： G11C16/06 , G11C16/14 , G11C16/10 , G11C16/26 , G11C16/08
CPC分类号： G11C16/30 , G11C5/14 , G11C5/145 , G11C5/147 , G11C8/08 , G11C16/0408 , G11C16/0425 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26 , G11C2216/04 , H01L27/11521
摘要： A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.
摘要翻译：非易失性存储器件包括第一导电类型的半导体衬底。非易失性存储单元的阵列位于半导体衬底中并且被布置成多个行和列。每个存储单元包括第二导电类型的半导体衬底的表面上的第一区域和第二导电类型的半导体衬底的表面上的第二区域。沟道区域在第一区域和第二区域之间。字线覆盖在沟道区域的第一部分上，并且与第一区域绝缘，并且与第一区域相邻并且与第一区域几乎没有或没有重叠。浮动栅极覆盖沟道区域的第二部分，与第一部分相邻，并与第二部分绝缘并与第二区域相邻。耦合栅极覆盖浮栅。位线连接到第一区域。在程序，读取或擦除的操作期间，负电压可以被施加到所选择的或未选择的存储单元的字线和/或耦合门。

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