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1. 发明授权

US11755899B2 Precise programming method and apparatus for analog neural memory in an artificial neural network 有权
公开(公告)号：US11755899B2
公开(公告)日：2023-09-12
申请号：US16751202
申请日：2020-01-23
申请人： Silicon Storage Technology, Inc.
发明人： Hieu Van Tran , Steven Lemke , Vipin Tiwari , Nhan Do , Mark Reiten
IPC分类号： G11C16/04 , G06N3/065 , G06F17/16 , G11C16/10 , G11C16/34 , G11C16/26 , G11C11/56 , G11C16/14 , G06N3/044
CPC分类号： G06N3/065 , G06F17/16 , G06N3/044 , G11C11/5628 , G11C11/5635 , G11C16/0425 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3459 , G11C2216/04
摘要： Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

2. 发明授权

US11742024B2 Memory device comprising source line coupled to multiple memory cells and method of operation 有权
公开(公告)号：US11742024B2
公开(公告)日：2023-08-29
申请号：US16884137
申请日：2020-05-27
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
发明人： Yu-Der Chih , Cheng-Hsiung Kuo , Chung-Chieh Chen
IPC分类号： G11C16/10 , G11C16/08 , G11C16/26 , G11C16/14
CPC分类号： G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26 , G11C2216/04
摘要： A memory device includes a column of at least three memory cells and a source line coupled to the source terminal of each memory cell. A source line driver is coupled to the source line, a voltage terminal, and a program voltage source and is switchable between a program operation, an erase operation, and a read operation.

3. 发明授权

US09899538B1 Non-volatile memory device and operation method thereof 有权
公开(公告)号：US09899538B1
公开(公告)日：2018-02-20
申请号：US15591126
申请日：2017-05-10
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chun-Lung Chang , Tien-Fan Ou
IPC分类号： H01L27/115 , H01L29/788 , H01L27/11521 , H01L29/417 , G11C16/14 , G11C16/10 , G11C16/26 , G11C16/04
CPC分类号： H01L29/7884 , G11C16/0408 , G11C16/0416 , G11C16/10 , G11C16/14 , G11C16/26 , G11C2216/04 , H01L27/115 , H01L27/11521 , H01L29/41775 , H01L29/42328
摘要： The present invention provides a non-volatile memory device, including a source region and a drain region, a channel region, a floating gate, an enhance hot carrier (hole or electron) injection gate and an erasing gate. The floating gate is disposed on the channel region and the source region and a first dielectric layer is disposed therebetween. The enhance hot carrier injection gate is disposed on the floating gate and the substrate wherein the enhance hot carrier injection gate has an L-shape cross-section. A second dielectric layer is disposed between the enhance hot carrier injection gate and the floating gate, and a fourth dielectric layer is disposed between the enhance hot carrier injection gate and the substrate. The erasing gate is disposed on the drain region. A third dielectric layer is disposed between the erasing gate and the substrate.

4. 发明授权

US09401217B2 Flash memory with improved read performance 有权
标题翻译：具有改进的读取性能的闪存
公开(公告)号：US09401217B2
公开(公告)日：2016-07-26
申请号：US14470359
申请日：2014-08-27
申请人： Anirban Roy , Jon S. Choy
发明人： Anirban Roy , Jon S. Choy
IPC分类号： G11C16/26 , G11C29/02 , G11C16/30 , G11C16/34
CPC分类号： G11C16/26 , G11C16/30 , G11C16/3445 , G11C16/3459 , G11C16/349 , G11C29/021 , G11C29/028 , G11C2216/04
摘要： A non-volatile memory device includes an array of memory cells and a plurality of word lines and voltage supply lines. Each memory cell of the array is coupled to one of the word lines. Each of the plurality of voltage supply lines is coupled to a first voltage supply terminal of a subset of memory cells of a plurality of subsets of memory cells of the array. Each subset includes a plurality of memory cells. A voltage switch supplies a respective one of a plurality of aged voltages to each of the plurality of subsets of memory cells in the memory array on respective ones of the voltage supply lines. The aged voltage supplied to a first of the plurality of subsets of memory cells is different than the aged voltage supplied to a second of the plurality of subsets of memory cells.
摘要翻译：非易失性存储器件包括存储器单元阵列和多个字线和电压供应线。阵列的每个存储单元耦合到一行字线。多个电压供给线中的每一个耦合到该阵列的多个存储器单元的子集的存储单元子集的第一电压供应端。每个子集包括多个存储单元。电压开关将多个老化电压中的相应一个向存储器阵列中的各个电压供应线上的多个存储单元子集中的每一个提供。提供给存储器单元的多个子集中的第一个的老化电压与提供给多个存储单元子集中的第二子集的老化电压不同。

5. 发明授权

US08391079B2 EEPROM memory architecture optimized for embedded memories 有权
标题翻译： EEPROM内存架构为嵌入式存储器优化
公开(公告)号：US08391079B2
公开(公告)日：2013-03-05
申请号：US12823901
申请日：2010-06-25
申请人： Francesco La Rosa
发明人： Francesco La Rosa
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0433 , G11C8/12 , G11C16/16 , G11C2216/04
摘要： The present disclosure relates to an electrically erasable and programmable memory comprising rows of memory cells to store words of N bits each, bit lines and word lines, wherein a row of memory cells comprises a first group of memory cells to store collectively erasable words, and at least one second group of memory cells to store one individually erasable word.
摘要翻译：本发明涉及一种电可擦除和可编程存储器，其包括存储单元行，每行存储N位的字，位线和字线，其中一行存储器单元包括第一组存储器单元以存储集体可擦除字，以及至少一个第二组存储器单元，用于存储一个单独的可擦除字。

6. 发明申请

US20050207225A1 Self-aligned split-gate NAND flash memory and fabrication process 有权
标题翻译：自对准分闸门NAND闪存和制造工艺
公开(公告)号：US20050207225A1
公开(公告)日：2005-09-22
申请号：US10803183
申请日：2004-03-17
申请人： Chiou-Feng Chen , Caleb Cho , Ming-Jer Chen , Der-Tsyr Fan , Prateep Tuntasood
发明人： Chiou-Feng Chen , Caleb Cho , Ming-Jer Chen , Der-Tsyr Fan , Prateep Tuntasood
IPC分类号： G11C16/00 , G11C16/04 , H01L21/8247 , H01L27/105 , H01L27/115
CPC分类号： G11C16/0483 , G11C2216/04 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.
摘要翻译：自对准分裂栅极NAND闪速存储单元阵列及其制造工艺，其中自对准分裂栅极单元行在衬底的有源区域中的位线扩散与公共源极扩散之间形成。每个单元具有彼此堆叠和自对准的控制和浮置栅极，并且擦除和选择与层叠栅极分离并与堆叠栅极自对准的栅极，每行的两端的选择栅极部分地重叠位排列源扩散。擦除栅极下面的沟道区域是重掺杂的，以减小位线和源极扩散之间的沟道电阻，并且浮置栅极以其它栅极包围，从而提供显着增强的与浮栅的高电压耦合其他大门。存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

7. 发明授权

US11875852B2 Adaptive bias decoder to provide a voltage to a control gate line in an analog neural memory array in artificial neural network 有权
公开(公告)号：US11875852B2
公开(公告)日：2024-01-16
申请号：US17140924
申请日：2021-01-04
申请人： Silicon Storage Technology, Inc.
发明人： Hieu Van Tran , Thuan Vu , Stanley Hong , Stephen Trinh , Anh Ly , Nhan Do , Mark Reiten
IPC分类号： G11C7/12 , G11C16/08 , G11C11/54 , G11C16/24
CPC分类号： G11C16/08 , G11C11/54 , G11C16/24 , G11C2216/04
摘要： Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments comprise an adaptive bias decoder for providing additional bias to array input lines to compensate for instances where ground floats above 0V. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation while maintaining accuracy in the operation.

8. 发明授权

US11798619B2 Precision tuning of a page or word of non-volatile memory cells in an analog neural memory system 有权
公开(公告)号：US11798619B2
公开(公告)日：2023-10-24
申请号：US17857113
申请日：2022-07-04
申请人： Silicon Storage Technology, Inc.
发明人： Hieu Van Tran , Thuan Vu , Stephen Trinh , Stanley Hong , Anh Ly , Steven Lemke , Vipin Tiwari , Nhan Do
IPC分类号： G11C11/54 , G11C16/04 , G11C16/08 , G11C16/16 , G11C16/34 , G11C16/10 , G06N3/065
CPC分类号： G11C11/54 , G06N3/065 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/3418 , G11C2216/04
摘要： Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, a method comprises programming a word or page of non-volatile memory cells in an analog neural memory system; and identifying any fast bits in the word or page of non-volatile memory cells.

9. 发明授权

US10878915B1 Memory device and method for programming the same 有权
公开(公告)号：US10878915B1
公开(公告)日：2020-12-29
申请号：US16721785
申请日：2019-12-19
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Kuo-Pin Chang , Hsien-Jung Chen , Chien-Hung Liu , Chih-Wei Hung
IPC分类号： G11C16/12 , G11C16/04 , G11C16/24 , G11C16/08 , G11C16/14 , H01L27/11521
CPC分类号： G11C16/12 , G11C16/0425 , G11C16/08 , G11C16/14 , G11C16/24 , G11C2216/04 , H01L27/11521
摘要： A method for programming a memory device is provided. The memory device includes first to fourth memory cells, in which the first and second memory cells share a first erase gate, and the third and fourth memory cells share a second erase gate. The method includes applying a first voltage to control gates of the first and third memory cell; applying a second voltage to control gates of the second and fourth memory cells, in which the first voltage is higher than the second voltage; applying a third voltage to a select gate of the first memory cell; and applying a fourth voltage to select gates of the second to fourth memory cell, in which the third voltage is higher than the fourth voltage.

10. 发明申请

US20170098474A1 Fully Depleted Silicon On Insulator Flash Memory Design 有权
公开(公告)号：US20170098474A1
公开(公告)日：2017-04-06
申请号：US14875533
申请日：2015-10-05
申请人： Silicon Storage Technology, Inc.
发明人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
IPC分类号： G11C16/14 , G11C16/26 , G11C16/08
CPC分类号： G11C16/14 , G11C7/065 , G11C8/08 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/28 , G11C2216/04 , H01L27/112 , H01L27/11582 , H01L28/00
摘要： The present invention relates to a flash memory system wherein one or more circuit blocks utilize fully depleted silicon-on-insulator transistor design to minimize leakage

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