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1. 发明申请

US20050282720A1 Efficient method for cleaning by using detergent 审中-公开
标题翻译：使用洗涤剂进行清洁的高效方法
公开(公告)号：US20050282720A1
公开(公告)日：2005-12-22
申请号：US11213934
申请日：2005-08-30
申请人： Mikihiko Itoh , Kazuyuki Hamada
发明人： Mikihiko Itoh , Kazuyuki Hamada
IPC分类号： B29C33/72 , C11D1/14 , C11D1/22 , C11D3/00 , C11D3/18 , C11D3/20 , C11D3/30 , C11D7/24 , C11D7/26 , C11D7/50 , C09K3/22
CPC分类号： C11D7/5022 , B29C33/722 , C11D1/143 , C11D1/22 , C11D3/188 , C11D3/2006 , C11D3/2037 , C11D3/2062 , C11D3/2068 , C11D3/30 , C11D7/24 , C11D7/26
摘要： A method for cleaning an article to be cleaned with oily deposits by using a detergent comprising 25˜80% by weight of (A) a terpene-based hydrocarbon and/or hydrocarbon-based solvent having a solubility parameter of 8.0˜9.8 and 75˜20% by weight of (B) an alcohol including one or more hydroxyl groups and having a solubility parameter of 10˜15, wherein said detergent in a state of having a water content of 10% by weight or less is coated onto the article to be cleaned and then causes the oily deposits to release from said article.
摘要翻译：通过使用包含25〜80重量％的（A）溶解度参数为8.0〜9.8和75〜80重量％的萜烯系烃类和/或烃类溶剂的洗涤剂来清洗待清洗物品的方法， 20重量％的（B）包含一个或多个羟基并且溶解度参数为10〜15的醇，其中将含水量为10重量％以下的状态的所述洗涤剂涂覆到制品上清洁，然后使油性沉积物从所述制品中释放出来。

2. 发明授权

US08879335B2 Input circuit 有权
标题翻译：输入电路
公开(公告)号：US08879335B2
公开(公告)日：2014-11-04
申请号：US13424707
申请日：2012-03-20
申请人： Masaru Koyanagi , Mikihiko Itoh
发明人： Masaru Koyanagi , Mikihiko Itoh
IPC分类号： G11C7/10 , H03K19/0175
CPC分类号： H03K19/017527
摘要： The first input circuit detects an input signal to output a first output signal having the same phase as the input signal. The second input circuit is configured to detect a first strobe signal to output a second output signal. The third input circuit is configured to detect a second strobe signal as a reversed signal of the first strobe signal to output a third output signal. A data latch circuit includes a first latch circuit and a second latch circuit. It is configured to latch the first output signal in either one of the first latch circuit or the second latch circuit according to the first output signal, the second output signal and the third output signal. It also allows the other one of the first latch circuit or the second latch circuit to input the first output signal thereto.
摘要翻译：第一输入电路检测输入信号以输出与输入信号具有相同相位的第一输出信号。第二输入电路被配置为检测第一选通信号以输出第二输出信号。第三输入电路被配置为检测第二选通信号作为第一选通信号的反相信号以输出第三输出信号。数据锁存电路包括第一锁存电路和第二锁存电路。其被配置为根据第一输出信号，第二输出信号和第三输出信号将第一输出信号锁存在第一锁存电路或第二锁存电路中的任一个中。也允许第一锁存电路或第二锁存电路中的另一个向其输入第一输出信号。

3. 发明申请

US20110157983A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110157983A1
公开(公告)日：2011-06-30
申请号：US13045227
申请日：2011-03-10
申请人： Mikihiko ITOH
发明人： Mikihiko ITOH
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C7/04 , G11C11/5642 , G11C16/26 , G11C16/30
摘要： A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix, a read unit which reads out data from the memory cells in the memory cell array, a write unit which writes data in the memory cells in the memory cell array, a read voltage generating unit which generates a read voltage and supplies the read voltage to the read unit, and a voltage control unit which controls the read voltage in accordance with temperatures.
摘要翻译：一种半导体存储器件包括存储单元阵列，其中多个存储器单元以矩阵形式排列;读出单元，其从存储单元阵列中的存储单元读出数据;写入单元，用于将数据写入存储单元中存储单元阵列，产生读取电压并将读取电压提供给读取单元的读取电压产生单元，以及根据温度控制读取电压的电压控制单元。

4. 发明申请

US20080128877A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080128877A1
公开(公告)日：2008-06-05
申请号：US11947030
申请日：2007-11-29
申请人： Mikihiko Itoh , Masaru Koyanagi
发明人： Mikihiko Itoh , Masaru Koyanagi
IPC分类号： H01L23/495
CPC分类号： H01L23/4951 , H01L23/49541 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48247 , H01L2224/49171 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/07802 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor device of an aspect of the invention comprises a first internal lead provided in a lead frame, and a semiconductor chip which is mounted on the lead frame and has a plurality of first pads provided along a first side, wherein the first internal lead has a first wiring portion extending in a direction parallel to the first side, the first side is arranged to vertically overlap the first wiring portion, and the first pad is connected with the first wiring portion.
摘要翻译：本发明的一个方面的半导体器件包括设置在引线框架中的第一内部引线和安装在引线框架上的半导体芯片，并且具有沿着第一侧设置的多个第一焊盘，其中第一内部引线具有第一布线部分沿平行于第一侧的方向延伸，第一侧布置成与第一布线部分垂直重叠，并且第一焊盘与第一布线部分连接。

5. 发明授权

US5298078A Cleaning composition for a molding machine and a cleaning method 失效
标题翻译：用于成型机的清洁组合物和清洁方法
公开(公告)号：US5298078A
公开(公告)日：1994-03-29
申请号：US794062
申请日：1991-11-19
申请人： Mikihiko Itoh , Narimichi Murahara
发明人： Mikihiko Itoh , Narimichi Murahara
IPC分类号： C08L25/06 , C08L35/06 , C08L51/06 , C11D3/37 , B08B7/00
CPC分类号： C11D3/3788 , C08L25/06 , C08L35/06 , C08L51/06
摘要： Disclosed is a cleaning composition for use in cleaning the interior of a molding machine having residual molding resin retained therein, comprising (a) a specific graft polymer comprised of a main chain comprising an olefin polymer and having, grafted thereto, a side chain comprising a styrene polymer and (b) a thermoplastic styrene polymer, the graft polymer (a) and the thermoplastic styrene polymer (b) being present in a weight ratio of from 2/100 to 160/100. This cleaning composition exhibits an extremely excellent cleaning effect due to its high capability to scape off a residual resin on a metallic surface. By using this cleaning composition, the cleaning of the interior of a molding machine having a residual molding resin retained therein can be effectively and efficiently performed in a short period of time and at a low cost.
摘要翻译：公开了一种清洁组合物，其用于清洁其中残留有模塑树脂的成型机的内部，其包含（a）由包含烯烃聚合物的主链组成的特定接枝聚合物，并且具有接枝到其上的侧链，苯乙烯聚合物和（b）热塑性苯乙烯聚合物，接枝聚合物（a）和热塑性苯乙烯聚合物（b）以2/100至160/100的重量比存在。这种清洁组合物由于其在金属表面上残留的树脂的高能力而显示出极好的清洁效果。通过使用这种清洁组合物，可以在短时间内以低成本有效地有效地进行清洁其中残留有树脂树脂的成型机的内部。

6. 发明申请

US20120250423A1 INPUT CIRCUIT 有权
标题翻译：输入电路
公开(公告)号：US20120250423A1
公开(公告)日：2012-10-04
申请号：US13424707
申请日：2012-03-20
申请人： Masaru KOYANAGI , Mikihiko ITOH
发明人： Masaru KOYANAGI , Mikihiko ITOH
IPC分类号： G11C7/10
CPC分类号： H03K19/017527
摘要： The first input circuit detects an input signal to output a first output signal having the same phase as the input signal. The second input circuit is configured to detect a first strobe signal to output a second output signal. The third input circuit is configured to detect a second strobe signal as a reversed signal of the first strobe signal to output a third output signal. A data latch circuit includes a first latch circuit and a second latch circuit. It is configured to latch the first output signal in either one of the first latch circuit or the second latch circuit according to the first output signal, the second output signal and the third output signal. It also allows the other one of the first latch circuit or the second latch circuit to input the first output signal thereto.
摘要翻译：第一输入电路检测输入信号以输出与输入信号具有相同相位的第一输出信号。第二输入电路被配置为检测第一选通信号以输出第二输出信号。第三输入电路被配置为检测第二选通信号作为第一选通信号的反相信号以输出第三输出信号。数据锁存电路包括第一锁存电路和第二锁存电路。其被配置为根据第一输出信号，第二输出信号和第三输出信号将第一输出信号锁存在第一锁存电路或第二锁存电路中的任一个中。也允许第一锁存电路或第二锁存电路中的另一个向其输入第一输出信号。

7. 发明授权

US07683491B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07683491B2
公开(公告)日：2010-03-23
申请号：US11943142
申请日：2007-11-20
申请人： Mikihiko Itoh , Masaru Koyanagi
发明人： Mikihiko Itoh , Masaru Koyanagi
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L23/50 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/18 , H01L2224/0401 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48599 , H01L2224/4911 , H01L2224/85399 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/14 , H01L2924/30105 , H01L2924/00
摘要： An aspect of the semiconductor device comprising a package substrate which has a plurality of pads to which a power supply voltage is applied on an upper surface thereof, a first memory chip which is arranged on the package substrate and has a first power supply pad provided on a first side and a second power supply pad provided on a second side perpendicular to the first side, and a second memory chip which is translated in a direction along which the first and second power supply pads of the first memory chip are exposed, arranged on the first memory chip, and has the same structure as the first memory chip, wherein the first and second power supply pads are provided at diagonal corners of the first memory chip, respectively.
摘要翻译：该半导体器件的一个方面包括：封装基板，其具有在其上表面上施加有电源电压的多个焊盘;布置在封装基板上的第一存储芯片，以及设置在第一电源焊盘上的第一电源焊盘设置在垂直于第一侧的第二侧上的第一侧和第二电源焊盘，以及沿着第一存储芯片的第一和第二电源焊盘暴露的方向平移的第二存储芯片，其布置在第一存储器芯片，并且具有与第一存储器芯片相同的结构，其中第一和第二电源焊盘分别设置在第一存储器芯片的对角角。

8. 发明申请

US20080122064A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080122064A1
公开(公告)日：2008-05-29
申请号：US11943142
申请日：2007-11-20
申请人： Mikihiko Itoh , Masaru Koyanagi
发明人： Mikihiko Itoh , Masaru Koyanagi
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L23/50 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/18 , H01L2224/0401 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48599 , H01L2224/4911 , H01L2224/85399 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/14 , H01L2924/30105 , H01L2924/00
摘要： An aspect of the semiconductor device comprising a package substrate which has a plurality of pads to which a power supply voltage is applied on an upper surface thereof, a first memory chip which is arranged on the package substrate and has a first power supply pad provided on a first side and a second power supply pad provided on a second side perpendicular to the first side, and a second memory chip which is translated in a direction along which the first and second power supply pads of the first memory chip are exposed, arranged on the first memory chip, and has the same structure as the first memory chip, wherein the first and second power supply pads are provided at diagonal corners of the first memory chip, respectively.
摘要翻译：该半导体器件的一个方面包括：封装基板，其具有在其上表面上施加有电源电压的多个焊盘;布置在封装基板上的第一存储芯片，以及设置在第一电源焊盘上的第一电源焊盘设置在垂直于第一侧的第二侧上的第一侧和第二电源焊盘，以及沿着第一存储芯片的第一和第二电源焊盘暴露的方向平移的第二存储芯片，其布置在第一存储器芯片，并且具有与第一存储器芯片相同的结构，其中第一和第二电源焊盘分别设置在第一存储器芯片的对角角。

9. 发明授权

US08208333B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08208333B2
公开(公告)日：2012-06-26
申请号：US13045227
申请日：2011-03-10
申请人： Mikihiko Itoh
发明人： Mikihiko Itoh
IPC分类号： G11C7/04
CPC分类号： G11C16/0483 , G11C7/04 , G11C11/5642 , G11C16/26 , G11C16/30
摘要： A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix, a read unit which reads out data from the memory cells in the memory cell array, a write unit which writes data in the memory cells in the memory cell array, a read voltage generating unit which generates a read voltage and supplies the read voltage to the read unit, and a voltage control unit which controls the read voltage in accordance with temperatures.
摘要翻译：一种半导体存储器件包括存储单元阵列，其中多个存储器单元以矩阵形式排列;读出单元，其从存储单元阵列中的存储单元中读出数据;写入单元，用于将数据写入存储单元中存储单元阵列，产生读取电压并将读取电压提供给读取单元的读取电压产生单元，以及根据温度控制读取电压的电压控制单元。

10. 发明申请

US20110182125A1 SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF DATA ERASE IN THE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件，半导体器件和半导体存储器件中的数据擦除方法
公开(公告)号：US20110182125A1
公开(公告)日：2011-07-28
申请号：US12883474
申请日：2010-09-16
申请人： Mikihiko ITOH , Takeshi Nakano , Michio Nakagawa
发明人： Mikihiko ITOH , Takeshi Nakano , Michio Nakagawa
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C5/145 , G11C16/0483 , G11C16/30
摘要： A semiconductor memory device in accordance with an embodiment comprises a memory cell array and an erase voltage generating circuit. The memory cell array is configured as an arrangement of nonvolatile memory cells. The erase voltage generating circuit is configured to generate an erase voltage for performing data erase of the memory cell array. The erase voltage generating circuit is configured to set, in a data erase mode where the erase voltage is applied to a selected region of the memory cell array in a plurality of erase cycles, a rise waveform of the erase voltage in an initial stage of the plurality of erase cycles to be less steep than a rise waveform of the erase voltage in subsequent cycles.
摘要翻译：根据实施例的半导体存储器件包括存储单元阵列和擦除电压产生电路。存储单元阵列被配置为非易失性存储单元的布置。擦除电压产生电路被配置为产生用于执行存储单元阵列的数据擦除的擦除电压。擦除电压产生电路被配置为在擦除电压被施加到多个擦除周期中的存储单元阵列的选定区域的数据擦除模式中，将擦除电压的初始阶段的擦除电压的上升波形多个擦除周期比随后的周期中的擦除电压的上升波形不那么陡。

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