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    • 4. 发明授权
    • Memory controller
    • 内存控制器
    • US08107301B2
    • 2012-01-31
    • US12480441
    • 2009-06-08
    • Hiroshi SukegawaTakeshi Nakano
    • Hiroshi SukegawaTakeshi Nakano
    • G11C11/34
    • G06F13/1668G11C8/08G11C11/5628G11C16/0483G11C16/08G11C2211/5641
    • A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with the state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes the first and second data in the first semiconductor memory. When writing the second data, the arithmetic unit does not select a word line adjacent to a select gate line, and selects a word line not adjacent to the select gate line.
    • 一种用于在包括具有串联电流路径和电荷存储层的多个存储单元的第一半导体存储器中写入数据的存储器控​​制器包括被配置为可接收来自主机设备的第一数据的主机接口,临时的第二半导体存储器 保存第二数据,以及根据第一半导体存储器的状态生成第二数据的运算单元,将第二数据临时保存在第二半导体存储器中,并将第一和第二数据写入第一半导体存储器。 当写入第二数据时,运算单元不选择与选择栅极线相邻的字线,并且选择不与选择栅极线相邻的字线。
    • 5. 发明申请
    • POLYELECTROLYTE FILM, FILM-ELECTRODE ASSEMBLY, AND SOLID-POLYMER-TYPE FUEL CELL
    • 聚电解质膜,膜电极组件和固体聚合物型燃料电池
    • US20100167159A1
    • 2010-07-01
    • US12278794
    • 2007-02-05
    • Tomohiro OnoShinji NakaiHiroyuki OgiTakeshi Nakano
    • Tomohiro OnoShinji NakaiHiroyuki OgiTakeshi Nakano
    • H01M8/10
    • C08F297/00C08F297/02C08J5/2243C08J2353/02C08L53/00C08L53/005C08L53/02C08L53/025H01B1/122H01M8/1011H01M8/1023H01M8/1067H01M2300/0082Y02E60/523C08L2666/02
    • A polymer electrolyte membrane comprising as a main ingredient a block copolymer which comprises, as its constituents, a polymer block (A) having as a main unit an aromatic vinyl compound unit and a polymer block (B) forming a flexible phase, and has ion-conducting groups on the polymer block (A), said aromatic vinyl compound unit being such that the hydrogen atom bonded to the α-carbon atom is non-replaced or replaced with an alkyl group or an aryl group optionally having substituent(s), and at least one of hydrogen atoms directly bonded to the aromatic ring is replaced with an alkyl group; and a membrane electrode assembly and a polymer electrolyte fuel cell both of which uses it. The polymer block (A) can have a restraining phase, and/or can be cross-linked. The electrolyte membrane is mild to the environment, has a high ion conductivity and good bonding properties to electrodes, is excellent in moldability, and is not easily influenced by methanol; and displays excellent performance in polymer electrolyte fuel cells, particularly direct methanol fuel cells.
    • 一种聚合物电解质膜,其包含作为主要成分的嵌段共聚物,该嵌段共聚物作为其成分,包含作为主要单元的芳族乙烯基化合物单元的聚合物嵌段(A)和形成柔性相的聚合物嵌段(B),并且具有离子 在聚合物嵌段(A)上的导电基团,所述芳香族乙烯基化合物单元使得与α-碳原子键合的氢原子不被任选具有取代基的烷基或芳基取代或取代, 直接与芳环键合的氢原子中的至少一个被烷基取代; 以及两者都使用它的膜电极组件和聚合物电解质燃料电池。 聚合物嵌段(A)可具有约束相,和/或可交联。 电解质膜对环境温和,离子电导率高,与电极接合性好,成型性优良,不易受甲醇影响; 并且在聚合物电解质燃料电池,特别是直接甲醇燃料电池中显示出优异的性能。
    • 6. 发明申请
    • MEMORY CONTROLLER
    • 内存控制器
    • US20090241012A1
    • 2009-09-24
    • US12480441
    • 2009-06-08
    • Hiroshi SUKEGAWATakeshi Nakano
    • Hiroshi SUKEGAWATakeshi Nakano
    • G11C16/04G06F12/02H03M13/05G06F11/10G11C16/06
    • G06F13/1668G11C8/08G11C11/5628G11C16/0483G11C16/08G11C2211/5641
    • A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with the state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes the first and second data in the first semiconductor memory. When writing the second data, the arithmetic unit does not select a word line adjacent to a select gate line, and selects a word line not adjacent to the select gate line.
    • 一种用于在包括具有串联电流路径和电荷存储层的多个存储单元的第一半导体存储器中写入数据的存储器控​​制器包括被配置为可接收来自主机设备的第一数据的主机接口,临时的第二半导体存储器 保存第二数据,以及根据第一半导体存储器的状态生成第二数据的运算单元,将第二数据临时保存在第二半导体存储器中,并将第一和第二数据写入第一半导体存储器。 当写入第二数据时,运算单元不选择与选择栅极线相邻的字线,并且选择不与选择栅极线相邻的字线。
    • 7. 发明申请
    • MEMORY CONTROLLER
    • 内存控制器
    • US20080052447A1
    • 2008-02-28
    • US11776037
    • 2007-07-11
    • Hiroshi SUKEGAWATakeshi Nakano
    • Hiroshi SUKEGAWATakeshi Nakano
    • G06F12/00
    • G06F13/1668G11C8/08G11C11/5628G11C16/0483G11C16/08G11C2211/5641
    • A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with the state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes the first and second data in the first semiconductor memory. When writing the second data, the arithmetic unit does not select a word line adjacent to a select gate line, and selects a word line not adjacent to the select gate line.
    • 一种用于在包括具有串联电流路径和电荷存储层的多个存储单元的第一半导体存储器中写入数据的存储器控​​制器包括被配置为可接收来自主机设备的第一数据的主机接口,临时的第二半导体存储器 保存第二数据,以及根据第一半导体存储器的状态生成第二数据的运算单元,将第二数据临时保存在第二半导体存储器中,并将第一和第二数据写入第一半导体存储器。 当写入第二数据时,运算单元不选择与选择栅极线相邻的字线,并且选择不与选择栅极线相邻的字线。