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1. 发明授权

US5537573A Cache system and method for prefetching of data 失效
标题翻译：用于预取数据的缓存系统和方法
公开(公告)号：US5537573A
公开(公告)日：1996-07-16
申请号：US069147
申请日：1993-05-28
申请人： Frederick A. Ware , Michael P. Farmwald , Craig Hampel , Karnamadakala Krishnamohan
发明人： Frederick A. Ware , Michael P. Farmwald , Craig Hampel , Karnamadakala Krishnamohan
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A cache system which includes prefetch pointer fields for identifying lines of memory to prefetch thereby minimizing the occurrence of cache misses. This cache structure and method for implementing the same takes advantage of the previous execution history of the processor and the locality of reference exhibited by the requested addresses. In particular, each cache line contains a prefetch pointer field which contains a pointer to a line in memory to be prefetched and placed in the cache. By prefetching specified lines of data with temporal locality to the lines of data containing the prefetch pointers the number of cache misses is minimized.
摘要翻译：一种缓存系统，其包括用于识别预取存储器行的预取指针字段，从而最小化高速缓存未命中的发生。用于实现该高速缓存结构和方法的优点在于处理器的先前执行历史和所请求地址所呈现的参考位置。特别地，每个高速缓存线包含预取指针字段，其包含指向要预存的存储器中的行的指针并放置在高速缓存中。通过将具有时间局部性的指定数据行预取到包含预取指针的数据行，高速缓存未命中的数量被最小化。

2. 发明授权

US5434817A Dynamic random access memory system 失效
标题翻译：动态随机存取存储系统
公开(公告)号：US5434817A
公开(公告)日：1995-07-18
申请号：US333869
申请日：1994-11-03
申请人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy W. Garrett, Jr. , John G. Atwood, Jr. , Michael P. Farmwald
发明人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy W. Garrett, Jr. , John G. Atwood, Jr. , Michael P. Farmwald
IPC分类号： G06F13/16 , G11C5/06 , G11C11/401 , G11C7/00 , G06F12/06
CPC分类号： G11C5/066
摘要： As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.
摘要翻译：随着与DRAM的接口变得越来越先进和更高的性能，支持接口所需的接口和信号线变得越来越昂贵。因此，为了利用接口中的信号线的高性能，期望使信号线的数量最小化并且使与DRAM接口的信号线的带宽最大化。在本发明的DRAM存储器系统中，地址和控制线被组合并且被多路复用的信息使得DRAM引脚始终具有大致相等的信息速率。

3. 发明授权

US5940340A Method and apparatus for writing to memory components 失效
标题翻译：用于写入存储器组件的方法和装置
公开(公告)号：US5940340A
公开(公告)日：1999-08-17
申请号：US858068
申请日：1997-05-16
申请人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
发明人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
IPC分类号： G11C7/10 , G11C11/401
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/103 , G11C7/1045 , G11C7/1078 , G11C7/1087
摘要： Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.
摘要翻译：提供额外的操作模式以增强存储器系统的功能和性能。在一个实施例中，向每个列访问中使用的写入数据提供唯一的位掩码。在替代实施例中，提供位掩码寄存器和字节掩码寄存器以支持位电平和字节电平掩蔽。位掩码和写数据寄存器被实现为单个寄存器，以提供功能，同时最小化组件空间和成本。在另一个实施例中，提供单独的位掩码和字节掩码。字节掩码在一个周期内加载掩码数据，并在下一个“q”列写入访问期间使用。该结构提供无位掩蔽的操作模式，每行访问提供位掩码，并提供每列访问的位掩码。为了增强诸如二维图形系统的系统的功能，在替代实施例中，存储器系统具有两个寄存器和选择控制线，以从两个寄存器之一中选择数据。在计算机图形系统中，用于在前景和背景颜色之间进行选择。该实施例可以与所描述的其他实施例一起使用以提供增强的功能和性能。

4. 发明授权

US5844855A Method and apparatus for writing to memory components 失效
公开(公告)号：US5844855A
公开(公告)日：1998-12-01
申请号：US858014
申请日：1997-05-16
申请人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
发明人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
IPC分类号： G11C7/10 , G11C11/401
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/103 , G11C7/1045 , G11C7/1078 , G11C7/1087
摘要： Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.

5. 发明授权

US5511024A Dynamic random access memory system 失效
公开(公告)号：US5511024A
公开(公告)日：1996-04-23
申请号：US201981
申请日：1994-02-25
申请人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy W. Garrett, Jr. , John G. Atwood, Jr. , Michael P. Farmwald
发明人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy W. Garrett, Jr. , John G. Atwood, Jr. , Michael P. Farmwald
IPC分类号： G06F13/16 , G11C5/06 , G11C11/401 , G06F1/12
CPC分类号： G11C5/066
摘要： As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.

6. 发明授权

US5446696A Method and apparatus for implementing refresh in a synchronous DRAM system 失效
标题翻译：用于在同步DRAM系统中实现刷新的方法和装置
公开(公告)号：US5446696A
公开(公告)日：1995-08-29
申请号：US347770
申请日：1994-12-02
申请人： Frederick A. Ware , James A. Gasbarro , John B. Dillon , Michael P. Farmwald , Mark A. Horowitz , Matthew M. Griffin
发明人： Frederick A. Ware , James A. Gasbarro , John B. Dillon , Michael P. Farmwald , Mark A. Horowitz , Matthew M. Griffin
IPC分类号： G11C11/407 , G11C11/401 , G11C11/406 , G11G7/00
CPC分类号： G11C11/406
摘要： A synchronous DRAM system with internal refresh is controlled by a refresh signal issued by an oscillator or memory controller coupled to the DRAM. By locating the oscillator on the processor or memory controller better control of the frequency of refresh is achieved, particularly, as the signal can be derived from a crystal which is not sensitive to variations in operating conditions. The oscillator drives a refresh signal on a bus or signal line to the DRAM, such that the refresh address counter is incremented and the row identified by the refresh address counter is refreshed.
摘要翻译：具有内部刷新的同步DRAM系统由耦合到DRAM的振荡器或存储器控制器发出的刷新信号控制。通过将振荡器定位在处理器或存储器控制器上，可以更好地控制刷新频率，特别是可以从对操作条件变化不敏感的晶体导出信号。振荡器将总线或信号线上的刷新信号驱动到DRAM，使得刷新地址计数器递增，刷新地址计数器识别的行被刷新。

7. 发明授权

US5680361A Method and apparatus for writing to memory components 失效
标题翻译：用于写入存储器组件的方法和装置
公开(公告)号：US5680361A
公开(公告)日：1997-10-21
申请号：US389561
申请日：1995-02-14
申请人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
发明人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
IPC分类号： G11C7/10 , G11C11/401
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/103 , G11C7/1045 , G11C7/1078 , G11C7/1087
摘要： Additional modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.
摘要翻译：提供附加模式以增强存储器系统的功能和性能。在一个实施例中，向每个列访问中使用的写入数据提供唯一的位掩码。在替代实施例中，提供位掩码寄存器和字节掩码寄存器以支持位电平和字节电平掩蔽。位掩码和写数据寄存器被实现为单个寄存器，以提供功能，同时最小化组件空间和成本。在另一个实施例中，提供单独的位掩码和字节掩码。字节掩码在一个周期内加载掩码数据，并在下一个“q”列写入访问期间使用。该结构提供无位掩蔽的操作模式，每行访问提供位掩码，并提供每列访问的位掩码。为了增强诸如二维图形系统的系统的功能，在替代实施例中，存储器系统具有两个寄存器和选择控制线，以从两个寄存器之一中选择数据。在计算机图形系统中，用于在前景和背景颜色之间进行选择。该实施例可以与所描述的其他实施例一起使用以提供增强的功能和性能。

8. 发明授权

US5430676A Dynamic random access memory system 失效
公开(公告)号：US5430676A
公开(公告)日：1995-07-04
申请号：US202290
申请日：1994-02-25
申请人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy W. Garrett, Jr. , John G. Atwood, Jr. , Michael P. Farmwald
发明人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy W. Garrett, Jr. , John G. Atwood, Jr. , Michael P. Farmwald
IPC分类号： G06F13/16 , G11C5/06 , G11C11/401 , G06F12/00
CPC分类号： G11C5/066
摘要： As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.

9. 发明授权

US5956284A Method and apparatus for writing to memory components 失效
公开(公告)号：US5956284A
公开(公告)日：1999-09-21
申请号：US167632
申请日：1998-10-06
申请人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
发明人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
IPC分类号： G11C7/10 , G11C11/401
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/103 , G11C7/1045 , G11C7/1078 , G11C7/1087
摘要： Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.

10. 发明授权

US5226133A Two-level translation look-aside buffer using partial addresses for enhanced speed 失效
标题翻译：使用部分地址进行增强速度的两级翻译
公开(公告)号：US5226133A
公开(公告)日：1993-07-06
申请号：US444594
申请日：1989-12-01
申请人： George S. Taylor , Michael P. Farmwald
发明人： George S. Taylor , Michael P. Farmwald
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/1054 , G06F2212/653
摘要： A translation of a portion of a virtual page number to a portion of a physical page number in a "TLB slice." The slice translation is used to index into a physical cache memory which has virtual tags in addition to physical tags and whose addresses are physical. By comparing the virtual tag to the input virtual address page number, it can be determined whether there was a hit or a miss in the combination of the TLB slice and the cache memory. By translating only a few bits of the virtual address to a few bits of a physical address, the speed of the device is greatly enhanced. This increased speed is achieved by making the TLB slice direct-mapped and by taking advantage of its small size to build it with special hardware (either high-speed RAM (random access memory) or with latches and multiplexers). There is no separate comparison at the TLB slice output for determining a TLB slice hit. The subsequent cache tag comparison is used to indicate both whether the translation was correct and whether there was a cache hit. To achieve this dual purpose comparison, however, a virtual tag must be combined with a physical cache to determine whether there is a hit, since the entire virtual address has not been translated and therefore there is no translated physical address to compare with a physical tag.

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