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1. 发明授权

US06975160B2 System including an integrated circuit memory device having an adjustable output voltage setting 失效
公开(公告)号：US06975160B2
公开(公告)日：2005-12-13
申请号：US11011077
申请日：2004-12-14
申请人： Billy Wayne Garrett, Jr. , Nancy David Dillon, legal representative , Michael Tak-Kei Ching , William E. Stonecynher , Andy Peng-Pui Chan , Matthew M. Griffin
发明人： John B. Dillon, deceased
IPC分类号： G06F13/40 , G11C7/10 , H03K19/003 , H03K19/0185 , H04L25/02 , G05F1/10
CPC分类号： H04L25/028 , G06F13/4077 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C29/02 , G11C29/021 , G11C29/028 , H03K19/00384 , H03K19/018585 , H04L25/0266 , H04L25/0272 , H04L25/0282 , H04L25/0298
摘要： A system including an integrated circuit memory device. The integrated circuit device comprises a register to store a value representative of an output voltage setting. A circuit holds a value representative of an adjustment to the output voltage setting. An output driver outputs a drive voltage during a calibration operation, wherein a signal is generated based on a comparison between a signal derived from the drive voltage and a reference voltage. The signal updates the value representative of the adjustment to the output voltage setting.

2. 发明授权

US06975159B2 Method of operation in a system having a memory device having an adjustable output voltage setting 失效
标题翻译：具有具有可调输出电压设置的存储器件的系统中的操作方法
公开(公告)号：US06975159B2
公开(公告)日：2005-12-13
申请号：US10981808
申请日：2004-11-05
申请人： Billy Wayne Garrett, Jr. , Nancy David Dillon, legal representative , Michael Tak-Kei Ching , William F. Stonecynher , Andy Peng-Pui Chan , Matthew M. Griffin
发明人： John B. Dillon, deceased
IPC分类号： G06F13/40 , G11C7/10 , H03K19/003 , H03K19/0185 , H04L25/02 , G05F1/10
CPC分类号： H04L25/028 , G06F13/4077 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C29/02 , G11C29/021 , G11C29/028 , H03K19/00384 , H03K19/018585 , H04L25/0266 , H04L25/0272 , H04L25/0282 , H04L25/0298
摘要： A method of operating a memory system that includes an integrated circuit memory device is provided. A value representing an output voltage setting of an output driver of the memory device is stored in a register. The output driver outputs the drive voltage. A signal derived from the drive voltage is compared to a reference signal to generate a signal that indicates an adjustment to the output voltage setting. The output voltage setting of the output driver is adjusted using a counter that holds a count value representing an update to the output voltage setting. The count value is updated in accordance with a signal that indicates the adjustment to the output voltage setting.
摘要翻译：提供了一种操作包括集成电路存储器件的存储器系统的方法。表示存储器件的输出驱动器的输出电压设置的值被存储在寄存器中。输出驱动器输出驱动电压。将从驱动电压导出的信号与参考信号进行比较，以产生指示对输出电压设置进行调整的信号。输出驱动器的输出电压设置使用一个计数器进行调整，该计数器保存表示输出电压设置更新的计数值。根据指示对输出电压设置的调整的信号来更新计数值。

3. 发明授权

US5337285A Method and apparatus for power control in devices 失效
标题翻译：设备功率控制的方法和装置
公开(公告)号：US5337285A
公开(公告)日：1994-08-09
申请号：US65804
申请日：1993-05-21
申请人： Frederick A. Ware , James A. Gasbarro , John B. Dillon , Matthew M. Griffin , Richard M. Barth , Mark A. Horowitz
发明人： Frederick A. Ware , James A. Gasbarro , John B. Dillon , Matthew M. Griffin , Richard M. Barth , Mark A. Horowitz
IPC分类号： G06F1/32 , G11C5/14 , H03K19/00 , H03K19/0175 , G11C7/00
CPC分类号： G11C5/14
摘要： A power control circuit to minimize power consumption of CMOS circuits by disabling/enabling the clock input to the CMOS circuit. A phase locked loop (PLL) or delay locked loop (DLL) drives a capacitive load of the component and a dummy load comparable to the component load. A standby latch is provided to control the clock input to the component. In a standby state, the clock signal is not provided to the component but the PLL/DLL continues to operate, driving the dummy load. Thus, when it is desirable to power on the circuit, the standby latch is reset and the clock signal is provided to the component, thereby turning on the component with little latency.
摘要翻译：电源控制电路，通过禁止/使能CMOS电路的时钟输入来最小化CMOS电路的功耗。锁相环（PLL）或延迟锁定环（DLL）驱动组件的容性负载和与组件负载相当的虚拟负载。提供备用锁存器来控制对组件的时钟输入。在待机状态下，时钟信号不提供给组件，但PLL / DLL继续运行，驱动虚拟负载。因此，当期望对电路通电时，备用锁存器被复位，并且时钟信号被提供给部件，从而以很小的延迟打开部件。

4. 发明授权

US06870419B1 Memory system including a memory device having a controlled output driver characteristic 有权
标题翻译：存储器系统，包括具有受控输出驱动器特性的存储器件
公开(公告)号：US06870419B1
公开(公告)日：2005-03-22
申请号：US10625264
申请日：2003-07-23
申请人： Billy Wayne Garrett, Jr. , Nancy David Dillon , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
发明人： John B. Dillon
IPC分类号： G06F13/40 , G11C7/10 , H03K19/003 , H03K19/0185 , H04L25/02 , G05F1/10
CPC分类号： H04L25/028 , G06F13/4077 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C29/02 , G11C29/021 , G11C29/028 , H03K19/00384 , H03K19/018585 , H04L25/0266 , H04L25/0272 , H04L25/0282 , H04L25/0298
摘要： An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).
摘要翻译：使用输出驱动电路和电流控制技术，以便于低噪声的高速总线与高速动态RAM（DRAM）接口。该架构包括以下组件：输入隔离块（120），模拟分压器（104），输入比较器（125），采样锁存器（130），电流控制计数器（115）和按位输出驱动器（输出驱动器A107和输出驱动器B111）。

5. 发明授权

US06608507B2 Memory system including a memory device having a controlled output driver characteristic 失效
标题翻译：存储器系统，包括具有受控输出驱动器特性的存储器件
公开(公告)号：US06608507B2
公开(公告)日：2003-08-19
申请号：US10230931
申请日：2002-08-29
申请人： Billy Wayne Garrett, Jr. , John B. Dillon , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
发明人： Billy Wayne Garrett, Jr. , John B. Dillon , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
IPC分类号： H03B100
CPC分类号： G11C7/1057 , G06F13/4077 , G11C7/1051 , G11C7/106 , H03K19/00384 , H03K19/018585 , H04L25/0266 , H04L25/0272 , H04L25/028 , H04L25/0282 , H04L25/0298
摘要： A memory system and method of adjusting an output driver characteristic of a memory device that is included in the memory system. The method includes providing a command to the memory device that specifies a calibration mode and, during the calibration mode, driving a voltage level onto the first signal line using a first output driver. A first voltage level is derived from an amount of voltage swing generated by the first output driver driving the voltage level onto the first signal line. The method also includes: actively coupling a first comparator to the first signal line; when the first comparator is coupled to the first signal line, comparing the first voltage level with a reference voltage using the first comparator; and adjusting the amount of voltage swing to arrive at a calibrated voltage swing level. In addition, the method includes actively isolation the first comparator from the first signal line upon exiting the calibration mode. The memory device is operable in a normal read operation upon exiting the calibration mode. During the normal read operation, the first output driver is operable to output data onto the first signal line in accordance with the calibrated voltage swing level.
摘要翻译：一种存储系统和调整包含在存储器系统中的存储器件的输出驱动器特性的方法。该方法包括向存储器件提供指定校准模式的命令，并且在校准模式期间，使用第一输出驱动器将电压电平驱动到第一信号线上。第一电压电平是从驱动第一信号线上的电压电平的第一输出驱动器产生的电压摆幅的量导出的。该方法还包括：主动地将第一比较器耦合到第一信号线; 当所述第一比较器耦合到所述第一信号线时，使用所述第一比较器将所述第一电压电平与参考电压进行比较; 并且调整电压摆幅的量以达到校准的电压摆幅水平。此外，该方法包括在退出校准模式时将第一比较器与第一信号线主动隔离。存储器件在退出校准模式时可在正常读取操作中操作。在正常读取操作期间，第一输出驱动器可操作以根据校准的电压摆幅电平将数据输出到第一信号线上。

6. 发明授权

US06556052B2 Semiconductor controller device having a controlled output driver characteristic 有权
标题翻译：具有受控输出驱动器特性的半导体控制器装置
公开(公告)号：US06556052B2
公开(公告)日：2003-04-29
申请号：US09954561
申请日：2001-09-12
申请人： Billy Wayne Garrett, Jr. , John B. Dillon , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
发明人： Billy Wayne Garrett, Jr. , John B. Dillon , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
IPC分类号： H03B100
CPC分类号： G11C7/1057 , G06F13/4077 , G11C7/1051 , G11C7/106 , H03K19/00384 , H03K19/018585 , H04L25/0266 , H04L25/0272 , H04L25/028 , H04L25/0282 , H04L25/0298
摘要： A semiconductor controller device to control the operation of a semiconductor memory device. The controller device includes a first output driver coupled to a first output terminal, and a second output driver coupled to a second output terminal. In addition, the controller device includes a voltage divider, coupled between the first and second output terminals, to generate a control voltage based on a voltage level present on the first output terminal and a voltage level present on the second output terminal. In addition, the controller device also includes a comparator, coupled to the voltage divider, to compare the control voltage with a reference voltage, wherein an amount of voltage swing of the first output driver is adjusted based on the comparison between the control voltage and the reference voltage.
摘要翻译：一种用于控制半导体存储器件的操作的半导体控制器装置。控制器装置包括耦合到第一输出端的第一输出驱动器和耦合到第二输出端的第二输出驱动器。此外，控制器装置包括耦合在第一和第二输出端子之间的分压器，以基于存在于第一输出端子上的电压电平和第二输出端子上存在的电压电平产生控制电压。此外，控制器装置还包括耦合到分压器的比较器，用于将控制电压与参考电压进行比较，其中基于控制电压和控制电压之间的比较来调节第一输出驱动器的电压摆幅量参考电压。

7. 发明授权

US07352234B2 Current control technique 失效
标题翻译：电流控制技术
公开(公告)号：US07352234B2
公开(公告)日：2008-04-01
申请号：US11625711
申请日：2007-01-22
申请人： Billy Wayne Garrett, Jr. , Nancy David Dillon, legal representative , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
发明人： John B. Dillon
IPC分类号： G05F1/10
CPC分类号： H04L25/028 , G06F13/4077 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C29/02 , G11C29/021 , G11C29/028 , H03K19/00384 , H03K19/018585 , H04L25/0266 , H04L25/0272 , H04L25/0282 , H04L25/0298
摘要： An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).
摘要翻译：使用输出驱动电路和电流控制技术，以便于低噪声的高速总线与高速动态RAM（DRAM）接口。该架构包括以下组件：输入隔离块（120），模拟分压器（104），输入比较器（125），采样锁存器（130），电流控制计数器（115）和按位输出驱动器（输出驱动器A107和输出驱动器B111）。

8. 发明授权

US06294934B1 Current control technique 失效
标题翻译：电流控制技术
公开(公告)号：US06294934B1
公开(公告)日：2001-09-25
申请号：US09559115
申请日：2000-04-26
申请人： Billy Wayne Garrett, Jr. , John B. Dillon , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
发明人： Billy Wayne Garrett, Jr. , John B. Dillon , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
IPC分类号： H03B100
CPC分类号： G11C7/1057 , G06F13/4077 , G11C7/1051 , G11C7/106 , H03K19/00384 , H03K19/018585 , H04L25/0266 , H04L25/0272 , H04L25/028 , H04L25/0282 , H04L25/0298
摘要： An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).
摘要翻译：使用输出驱动电路和电流控制技术，以便于低噪声的高速总线与高速动态RAM（DRAM）接口。该架构包括以下组件：输入隔离块（120），模拟分压器（104），输入比较器（125），采样锁存器（130），电流控制计数器（115）和按位输出驱动器（输出驱动器A107和输出驱动器B111）。

9. 发明授权

US6094075A Current control technique 有权
标题翻译：电流控制技术
公开(公告)号：US6094075A
公开(公告)日：2000-07-25
申请号：US141675
申请日：1998-08-27
申请人： Billy Wayne Garrett, Jr. , John B. Dillon, deceased , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
发明人： Billy Wayne Garrett, Jr. , John B. Dillon, deceased , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
IPC分类号： G06F13/40 , G11C7/10 , H03K19/003 , H03K19/0185 , H04L25/02 , H03B1/00
CPC分类号： G11C7/1057 , G06F13/4077 , G11C7/1051 , G11C7/106 , H03K19/00384 , H03K19/018585 , H04L25/028 , H04L25/0282 , H04L25/0266 , H04L25/0272 , H04L25/0298
摘要： An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).
摘要翻译：使用输出驱动电路和电流控制技术，以便于低噪声的高速总线与高速动态RAM（DRAM）接口。该架构包括以下组件：输入隔离块（120），模拟分压器（104），输入比较器（125），采样锁存器（130），电流控制计数器（115）和按位输出驱动器（输出驱动器A107和输出驱动器B111）。

10. 发明授权

US5446696A Method and apparatus for implementing refresh in a synchronous DRAM system 失效
标题翻译：用于在同步DRAM系统中实现刷新的方法和装置
公开(公告)号：US5446696A
公开(公告)日：1995-08-29
申请号：US347770
申请日：1994-12-02
申请人： Frederick A. Ware , James A. Gasbarro , John B. Dillon , Michael P. Farmwald , Mark A. Horowitz , Matthew M. Griffin
发明人： Frederick A. Ware , James A. Gasbarro , John B. Dillon , Michael P. Farmwald , Mark A. Horowitz , Matthew M. Griffin
IPC分类号： G11C11/407 , G11C11/401 , G11C11/406 , G11G7/00
CPC分类号： G11C11/406
摘要： A synchronous DRAM system with internal refresh is controlled by a refresh signal issued by an oscillator or memory controller coupled to the DRAM. By locating the oscillator on the processor or memory controller better control of the frequency of refresh is achieved, particularly, as the signal can be derived from a crystal which is not sensitive to variations in operating conditions. The oscillator drives a refresh signal on a bus or signal line to the DRAM, such that the refresh address counter is incremented and the row identified by the refresh address counter is refreshed.
摘要翻译：具有内部刷新的同步DRAM系统由耦合到DRAM的振荡器或存储器控制器发出的刷新信号控制。通过将振荡器定位在处理器或存储器控制器上，可以更好地控制刷新频率，特别是可以从对操作条件变化不敏感的晶体导出信号。振荡器将总线或信号线上的刷新信号驱动到DRAM，使得刷新地址计数器递增，刷新地址计数器识别的行被刷新。

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