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    • 1. 发明授权
    • Method and apparatus for setting a current of an output driver for the
high speed bus
    • 用于设定高速总线的输出驱动器的电流的方法和装置
    • US6009487A
    • 1999-12-28
    • US655830
    • 1996-05-31
    • Paul Gregory DavisPradeep BatraJohn B. DillonKarnamadakala KrishnamohanJames A. Gasbarro
    • Paul Gregory DavisPradeep BatraJohn B. DillonKarnamadakala KrishnamohanJames A. Gasbarro
    • G06F13/40G06F13/42
    • G06F13/4072
    • In a system comprising a current controlling device and a plurality of signal lines coupled to the current controlling device, wherein the current controlling device has an output driver including a register, an improved method for setting a current of the output driver for at least one of the plurality of signal lines. The improved method determines a reference register-setting for the register of the current controlling device. The reference register-setting corresponds to a reference voltage for at least one of the plurality of signal lines. A target register-setting is then determined for the register based on the reference register-setting. The target register-setting corresponds to a target voltage for at least one of the plurality of signal lines, wherein the target voltage produces an appropriate swing about the reference voltage. An operational register-setting is then determined for the register based on the target register-setting. The current of the output driver for at least one of the plurality of signal lines is then set based on the operational register-setting so that a swing about the reference voltage is optimal.
    • 在包括电流控制装置和耦合到电流控制装置的多条信号线的系统中,其中电流控制装置具有包括寄存器的输出驱动器,用于设置输出驱动器的电流的改进方法, 多条信号线。 改进的方法确定当前控制装置的寄存器的参考寄存器设置。 参考寄存器设置对应于多个信号线中的至少一个信号线的参考电压。 然后根据参考寄存器设置为寄存器确定目标寄存器设置。 目标寄存器设置对应于多个信号线中的至少一个的目标电压,其中目标电压产生关于参考电压的适当的摆幅。 然后根据目标寄存器设置为寄存器确定一个可操作的寄存器设置。 然后基于操作寄存器设置来设置多个信号线中的至少一个的输出驱动器的电流,使得关于参考电压的摆幅是最佳的。
    • 5. 发明授权
    • Prefetching into a cache to minimize main memory access time and cache
size in a computer system
    • 预取到缓存中以最小化计算机系统中的主存储器访问时间和缓存大小
    • US5499355A
    • 1996-03-12
    • US339920
    • 1994-11-15
    • Karnamadakala KrishnamohanPaul M. FarmwaldFrederick A. Ware
    • Karnamadakala KrishnamohanPaul M. FarmwaldFrederick A. Ware
    • G06F12/02G06F9/38G06F12/08G06F13/00
    • G06F9/3814G06F12/0862G06F9/3802G06F2212/6022G06F2212/6026
    • A cache subsystem for a computer system having a processor and a main memory is described. The cache subsystem includes a prefetch buffer coupled to the processor and the main memory. The prefetch buffer stores a first data prefetched from the main memory in accordance with a predicted address for a next memory fetch by the processor. The predicted address is based upon an address for a last memory fetch from the processor. A main cache is coupled to the processor and the main memory. The main cache is not coupled to the prefetch buffer and does not receive data from the prefetch buffer. The main cache stores a second data fetched from the main memory in accordance with the address for the last memory fetch by the processor only if the address for the last memory fetch is an unpredictable address. The address for the last memory fetch is the unpredictable address if both of the prefetch buffer and the main cache do not contain the address and the second data associated with the address.
    • 描述了具有处理器和主存储器的计算机系统的缓存子系统。 缓存子系统包括耦合到处理器和主存储器的预取缓冲器。 预取缓冲器根据由处理器进行的下一个存储器提取的预测地址存储从主存储器预取的第一数据。 预测地址是基于来自处理器的最后一次内存提取的地址。 主缓存耦合到处理器和主存储器。 主缓存不耦合到预取缓冲区,并且不从预取缓冲区接收数据。 如果最后一次存储器提取的地址是不可预测的地址,则主缓存器存储根据处理器的最后一次存储器提取的地址从主存储器提取的第二数据。 如果预取缓冲区和主缓存都不包含与地址相关联的地址和第二个数据,则最后一次内存提取的地址是不可预测的地址。