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1. 发明授权

US08716789B2 Power semiconductor device 失效
标题翻译：功率半导体器件
公开(公告)号：US08716789B2
公开(公告)日：2014-05-06
申请号：US13610532
申请日：2012-09-11
申请人： Syotaro Ono , Masaru Izumisawa , Hiroshi Ohta , Hiroaki Yamashita
发明人： Syotaro Ono , Masaru Izumisawa , Hiroshi Ohta , Hiroaki Yamashita
IPC分类号： H01L29/66
CPC分类号： H01L29/407 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/66712 , H01L29/7395 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device according to an embodiment includes an element portion in which MOSFET elements are provided and a termination portion provided around the element portion, and has pillar layers provided respectively in parallel to each other in a semiconductor substrate. The device includes a first trench and a first insulation film. The first trench is provided between end portions of the pillar layers, in the semiconductor substrate at the termination portion exposed from a source electrode of the MOSFET elements. The first insulation film is provided on a side surface and a bottom surface of the first trench.
摘要翻译：根据实施例的功率半导体器件包括其中设置MOSFET元件的元件部分和设置在元件部分周围的端接部分，并且在半导体衬底中分别彼此平行地设置有柱层。该装置包括第一沟槽和第一绝缘膜。第一沟槽设置在从MOSFET元件的源电极露出的终端部分的半导体衬底中的柱层的端部之间。第一绝缘膜设置在第一沟槽的侧表面和底表面上。

2. 发明申请

US20130341751A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130341751A1
公开(公告)日：2013-12-26
申请号：US13685019
申请日：2012-11-26
申请人： Syotaro ONO , Masaru Izumisawa , Hiroshi Ohta , Hiroaki Yamashita
发明人： Syotaro ONO , Masaru Izumisawa , Hiroshi Ohta , Hiroaki Yamashita
IPC分类号： H01L23/58
CPC分类号： H01L23/552 , H01L23/58 , H01L23/60 , H01L29/0634 , H01L29/0684 , H01L29/0696 , H01L29/1095 , H01L29/404 , H01L29/405 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a superjunction structure. The influence of external charge on device performance is suppressed using a shield electrode, field plate electrodes, and cover electrodes in various configurations. Optional embodiments include placing an interconnection film between certain electrodes and the upper surface of the superjunction structure. Cover electrodes may also be connected to various potentials to limit the effects of external charge on device performance.
摘要翻译：半导体器件包括超结构结构。使用各种结构的屏蔽电极，场板电极和覆盖电极来抑制外部电荷对器件性能的影响。可选实施例包括将互连膜放置在某些电极和超结构结构的上表面之间。覆盖电极也可以连接到各种电位以限制外部电荷对器件性能的影响。

3. 发明授权

US08030706B2 Power semiconductor device 失效
标题翻译：功率半导体器件
公开(公告)号：US08030706B2
公开(公告)日：2011-10-04
申请号：US12540192
申请日：2009-08-12
申请人： Miho Watanabe , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Wataru Saito , Syotaro Ono , Nana Hatano
发明人： Miho Watanabe , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Wataru Saito , Syotaro Ono , Nana Hatano
IPC分类号： H01L29/66
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/1095 , H01L29/7802
摘要： A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part. The device includes a first semiconductor layer, and second and third semiconductor layers formed on the first semiconductor layer, and alternately arranged along a direction parallel to a surface of the first semiconductor layer, wherein the device part is provided with a first region and a second region, each of which includes at least one of the second semiconductor layers and at least one of the third semiconductor layers, and with regard to a difference value ΔN (=NA−NB) obtained by subtracting an impurity amount NB per unit length of each of the third semiconductor layers from an impurity amount NA per unit length of each of the second semiconductor layers, a difference value ΔNC1 which is the difference value ΔN in the first region of the device part, a difference value ΔNC2 which is the difference value ΔN in the second region of the device part, and a difference value ΔNT which is the difference value ΔN in the terminal part satisfy a relationship of ΔNC1>ΔNT>ΔNC2.
摘要翻译：根据本发明实施例的半导体器件包括器件部分和端子部分。该器件包括第一半导体层，以及形成在第一半导体层上的第二和第三半导体层，并且沿着与第一半导体层的表面平行的方向交替布置，其中器件部分设置有第一区域和第二半导体层区域，其中每一个包括第二半导体层和至少一个第三半导体层中的至少一个，并且关于通过从每单位长度减去杂质量NB获得的差值Dgr; N（= NA-NB）从每个第二半导体层的每单位长度的杂质量NA中的每个第三半导体层的差分值＆Dgr; NC1，其是器件部分的第一区域中的差值＆Dgr; N，差值＆Dgr ;作为装置部分的第二区域中的差值Dgr; N的NC2，作为终端部分中的差值Dgr; N的差值＆Dgr; NT满足关系的＆Dgr; NC1>＆Dgr; NT>＆Dgr; NC2。

4. 发明授权

US07622771B2 Semiconductor apparatus 失效
标题翻译：半导体装置
公开(公告)号：US07622771B2
公开(公告)日：2009-11-24
申请号：US12123072
申请日：2008-05-19
申请人： Syotaro Ono , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Syotaro Ono , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L31/119 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0638 , H01L29/0878 , H01L29/7395 , H01L29/861 , H01L29/868 , H01L29/872
摘要： A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer provided on a major surface of the first semiconductor layer, a third semiconductor layer provided on the major surface and being adjacent to the second semiconductor layer, a termination semiconductor layer provided on the major surface of the first semiconductor layer in a termination region outside the device region, a channel stop layer, and a channel stop electrode. The channel stop layer is provided in contact with the termination semiconductor layer on the major surface of the first semiconductor layer in an outermost peripheral portion outside the termination semiconductor layer and has a higher impurity concentration than the termination semiconductor layer. The channel stop electrode is provided on at least part of a surface of the channel stop layer and projects toward the termination semiconductor layer beyond at least a superficial portion of the channel stop layer.
摘要翻译：半导体装置包括第一半导体层，设置在第一半导体层的主表面上的第二半导体层，设置在主表面上并与第二半导体层相邻的第三半导体层，设置在主体上的端接半导体层在器件区域外的终端区域中的第一半导体层的表面，沟道阻挡层和沟道停止电极。沟道阻挡层设置成与终端半导体层外部的最外周部分中的第一半导体层的主表面上的端接半导体层接触，并且具有比端接半导体层更高的杂质浓度。通道阻挡电极设置在通道阻挡层的表面的至少一部分上，并且朝向端子半导体层突出超过通道阻挡层的至少表面部分。

5. 发明申请

US20090236697A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090236697A1
公开(公告)日：2009-09-24
申请号：US12403881
申请日：2009-03-13
申请人： Syotaro ONO , Wataru SAITO , Nana HATANO , Masaru IZUMISAWA , Yasuto SUMI , Hiroshi OHTA , Wataru SEKINE , Miho WATANABE
发明人： Syotaro ONO , Wataru SAITO , Nana HATANO , Masaru IZUMISAWA , Yasuto SUMI , Hiroshi OHTA , Wataru SEKINE , Miho WATANABE
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L29/66712 , H01L21/266 , H01L29/0615 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/7395 , H01L29/7811
摘要： A semiconductor device includes a super junction region that has a first-conductivity-type first semiconductor pillar region and a second-conductivity-type second semiconductor pillar region alternately provided on the semiconductor substrate. The first semiconductor pillar region and the second semiconductor pillar region in a termination region have a lamination form resulting from alternate lamination of the first semiconductor pillar region and the second semiconductor pillar region on the top surface of the semiconductor substrate. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region exhibit an impurity concentration distribution such that a plurality of impurity concentration peaks appear periodically. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region have an impurity amount such that it becomes smaller as being closer to the circumference of the corner part.
摘要翻译：半导体器件包括具有交替设置在半导体衬底上的第一导电型第一半导体柱区域和第二导电型第二半导体柱区域的超结区域。终端区域中的第一半导体柱区域和第二半导体柱区域具有由半导体衬底的顶表面上的第一半导体柱区域和第二半导体柱区域的交替层叠形成的叠层形式。终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域显示杂质浓度分布，使得多个杂质浓度峰值周期性出现。终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域具有使得随着角部更靠近圆周而变小的杂质量。

6. 发明申请

US20080246079A1 POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件
公开(公告)号：US20080246079A1
公开(公告)日：2008-10-09
申请号：US12050415
申请日：2008-03-18
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yauto Sumi , Masaru Izumisawa , Wataru Sekine , Hiroshi Ohta , Shoichiro Kurushima
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yauto Sumi , Masaru Izumisawa , Wataru Sekine , Hiroshi Ohta , Shoichiro Kurushima
IPC分类号： H01L29/00
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095
摘要： A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the third semiconductor layer; a fifth semiconductor layer selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode; a gate insulating film; a first main electrode provided on a lower surface of the first semiconductor layer; and a second main electrode provided on the fourth and the fifth semiconductor layers. Sum of the amount of impurities in the second semiconductor layer and the amount of impurities in the third semiconductor layer at an end on the second main electrode side of the second semiconductor layer and the third semiconductor layer is smaller than the sum at a center of the second semiconductor layer and the third semiconductor layer in the direction from the first main electrode to the second main electrode.
摘要翻译：功率半导体器件包括：第一半导体层; 第二半导体层和第三半导体层，设置在所述第一半导体层的上部并且交替地平行于所述第一半导体层的上表面布置; 设置在所述第三半导体层上的多个第四半导体层; 选择性地形成在每个第四半导体层的上表面中的第五半导体层; 控制电极; 栅极绝缘膜; 设置在所述第一半导体层的下表面上的第一主电极; 以及设置在第四和第五半导体层上的第二主电极。第二半导体层中的杂质量和第二半导体层的第二主电极侧端部的第三半导体层中的杂质量的和小于第二半导体层的第二主电极侧的和第二半导体层和第三半导体层在从第一主电极到第二主电极的方向上。

7. 发明申请

US20070272977A1 POWER SEMICONDUCTOR DEVICE 失效
标题翻译：功率半导体器件
公开(公告)号：US20070272977A1
公开(公告)日：2007-11-29
申请号：US11680912
申请日：2007-03-01
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/66712 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.
摘要翻译：功率半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层和形成在第一半导体层上的第二导电类型的第三半导体层，并且沿着平行于第一半导体层的表面的至少一个方向交替布置; 第一主电极; 选择性地形成在第二半导体层的表面和第三半导体层的表面上的第二导电类型的第四半导体层; 选择性地形成在第四半导体层的表面中的第一导电类型的第五半导体层; 第二主电极; 和控制电极。第二和第三半导体层中的至少一个具有沿着一个方向的掺杂剂浓度分布，掺杂剂浓度分布在其两端以外的位置处具有局部最小值。

8. 发明授权

US07301202B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07301202B2
公开(公告)日：2007-11-27
申请号：US11151410
申请日：2005-06-14
申请人： Shigeo Kouzuki , Hideki Okumura , Wataru Saito , Masaru Izumisawa , Masahiko Shiomi , Hitoshi Kobayashi , Kenichi Tokano , Satoshi Yanagisawa , Hironori Yoshioka , Manabu Kimura
发明人： Shigeo Kouzuki , Hideki Okumura , Wataru Saito , Masaru Izumisawa , Masahiko Shiomi , Hitoshi Kobayashi , Kenichi Tokano , Satoshi Yanagisawa , Hironori Yoshioka , Manabu Kimura
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/66712 , H01L29/7811
摘要： A semiconductor substrate of a first conduction type is provided for serving as a common drain to a plurality of power MISFET cells. A middle semiconductor layer is formed on the semiconductor substrate and has a lower impurity concentration than that of the semiconductor substrate. Pillar regions are formed on the middle semiconductor layer and include semiconductor regions of the first conduction type having a lower impurity concentration than that of the middle semiconductor layer.
摘要翻译：提供第一导电类型的半导体衬底作为用于多个功率MISFET单元的公共漏极。在半导体衬底上形成中间半导体层，其杂质浓度低于半导体衬底的杂质浓度。柱状区域形成在中间半导体层上，并且包括具有比中间半导体层的杂质浓度低的第一导电类型的半导体区域。

9. 发明授权

US07259426B2 Semiconductor device and its manufacturing method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US07259426B2
公开(公告)日：2007-08-21
申请号：US11094190
申请日：2005-03-31
申请人： Satoshi Aida , Shigeo Kouzuki , Satoshi Yanagisawa , Masaru Izumisawa , Hironori Yoshioka
发明人： Satoshi Aida , Shigeo Kouzuki , Satoshi Yanagisawa , Masaru Izumisawa , Hironori Yoshioka
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7811 , H01L21/26586 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/66712 , H01L29/7802
摘要： There is provided a power MISFET which includes a semiconductor region of a first conductivity, a semiconductor base region of a second conductivity, a pillar region, a first major electrode region of a first conductivity on the base region, a second major electrode region connected with at least the semiconductor region and a part of the pillar region, a control electrode and an electrode pad connected with the control electrode. The pillar region including a first region of a first conductivity type and a second region of a second conductivity type is not formed under the electrode pad. Also, a method for manufacturing a MISFET is provided.
摘要翻译：提供了一种功率MISFET，其包括第一导电性的半导体区域，第二导电性的半导体基极区域，柱状区域，基极区域上的第一导电性的第一主电极区域，与第二导电性区域连接的第二主电极区域至少半导体区域和一部分柱区域，控制电极和与控制电极连接的电极焊盘。包括第一导电类型的第一区域和第二导电类型的第二区域的柱区域不形成在电极焊盘下面。另外，提供了用于制造MISFET的方法。

10. 发明授权

US07253507B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07253507B2
公开(公告)日：2007-08-07
申请号：US10975356
申请日：2004-10-29
申请人： Shigeo Kouzuki , Satoshi Aida , Satoshi Yanagisawa , Masaru Izumisawa , Hironori Yoshioka
发明人： Shigeo Kouzuki , Satoshi Aida , Satoshi Yanagisawa , Masaru Izumisawa , Hironori Yoshioka
IPC分类号： H01L23/045
CPC分类号： H01L29/7802 , H01L23/49524 , H01L23/49562 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/31 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/80 , H01L24/83 , H01L24/85 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/1095 , H01L2224/04042 , H01L2224/05624 , H01L2224/05647 , H01L2224/0603 , H01L2224/37124 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/4103 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48095 , H01L2224/48247 , H01L2224/48472 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/4903 , H01L2224/49051 , H01L2224/49171 , H01L2224/83801 , H01L2224/84205 , H01L2224/85205 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/3512 , H01L2224/83205 , H01L2924/00012
摘要： A semiconductor device comprises a semiconductor element and a conductive member. The semiconductor element has a semiconductor substrate having first and second major surfaces; a semiconductor layer formed on the first major surface of the semiconductor substrate; a plurality of trenches formed on the semiconductor layer, the trenches being parallel to each other and extending to a first direction; filling material filling the trenches; a first electrode pad provided on the semiconductor layer and connected electrically to a first major electrode; a second major electrode provided on the second major surface; and a gate electrode pad provided on the semiconductor layer and connected to a gate electrode which controls conduction between the first major electrode and the second major electrode. The conductive member is connected to at least one of the first electrode pad and the gate electrode pad via a first contact area. A leading-out direction of the conductive member is substantially parallel to the first direction.
摘要翻译：半导体器件包括半导体元件和导电元件。半导体元件具有具有第一和第二主表面的半导体衬底; 形成在半导体衬底的第一主表面上的半导体层; 形成在所述半导体层上的多个沟槽，所述沟槽彼此平行并延伸到第一方向; 填充沟槽的填充材料; 设置在所述半导体层上并与第一主电极电连接的第一电极焊盘; 设置在第二主表面上的第二主电极; 以及设置在所述半导体层上并与控制所述第一主电极和所述第二主电极之间的导通的栅电极连接的栅电极焊盘。导电构件经由第一接触区域连接到第一电极焊盘和栅电极焊盘中的至少一个。导电构件的导出方向基本上平行于第一方向。

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