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1. 发明申请

US20080246079A1 POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件
公开(公告)号：US20080246079A1
公开(公告)日：2008-10-09
申请号：US12050415
申请日：2008-03-18
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yauto Sumi , Masaru Izumisawa , Wataru Sekine , Hiroshi Ohta , Shoichiro Kurushima
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yauto Sumi , Masaru Izumisawa , Wataru Sekine , Hiroshi Ohta , Shoichiro Kurushima
IPC分类号： H01L29/00
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095
摘要： A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the third semiconductor layer; a fifth semiconductor layer selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode; a gate insulating film; a first main electrode provided on a lower surface of the first semiconductor layer; and a second main electrode provided on the fourth and the fifth semiconductor layers. Sum of the amount of impurities in the second semiconductor layer and the amount of impurities in the third semiconductor layer at an end on the second main electrode side of the second semiconductor layer and the third semiconductor layer is smaller than the sum at a center of the second semiconductor layer and the third semiconductor layer in the direction from the first main electrode to the second main electrode.
摘要翻译：功率半导体器件包括：第一半导体层; 第二半导体层和第三半导体层，设置在所述第一半导体层的上部并且交替地平行于所述第一半导体层的上表面布置; 设置在所述第三半导体层上的多个第四半导体层; 选择性地形成在每个第四半导体层的上表面中的第五半导体层; 控制电极; 栅极绝缘膜; 设置在所述第一半导体层的下表面上的第一主电极; 以及设置在第四和第五半导体层上的第二主电极。第二半导体层中的杂质量和第二半导体层的第二主电极侧端部的第三半导体层中的杂质量的和小于第二半导体层的第二主电极侧的和第二半导体层和第三半导体层在从第一主电极到第二主电极的方向上。

2. 发明授权

US08283720B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08283720B2
公开(公告)日：2012-10-09
申请号：US12050415
申请日：2008-03-18
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yauto Sumi , Masaru Izumisawa , Wataru Sekine , Hiroshi Ohta , Shoichiro Kurushima
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yauto Sumi , Masaru Izumisawa , Wataru Sekine , Hiroshi Ohta , Shoichiro Kurushima
IPC分类号： H01L29/00 , H01L29/66
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095
摘要： A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the third semiconductor layer; a fifth semiconductor layer selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode; a gate insulating film; a first main electrode provided on a lower surface of the first semiconductor layer; and a second main electrode provided on the fourth and the fifth semiconductor layers. Sum of the amount of impurities in the second semiconductor layer and the amount of impurities in the third semiconductor layer at an end on the second main electrode side of the second semiconductor layer and the third semiconductor layer is smaller than the sum at a center of the second semiconductor layer and the third semiconductor layer in the direction from the first main electrode to the second main electrode.
摘要翻译：功率半导体器件包括：第一半导体层; 第二半导体层和第三半导体层，设置在所述第一半导体层的上部并且交替地平行于所述第一半导体层的上表面布置; 设置在所述第三半导体层上的多个第四半导体层; 选择性地形成在每个第四半导体层的上表面中的第五半导体层; 控制电极; 栅极绝缘膜; 设置在所述第一半导体层的下表面上的第一主电极; 以及设置在第四和第五半导体层上的第二主电极。第二半导体层中的杂质量和第二半导体层的第二主电极侧端部的第三半导体层中的杂质量的和小于第二半导体层的第二主电极侧的和第二半导体层和第三半导体层在从第一主电极到第二主电极的方向上。

3. 发明授权

US07737469B2 Semiconductor device having superjunction structure formed of p-type and n-type pillar regions 失效
标题翻译：具有由p型和n型柱状区域形成的超结构结构的半导体装置
公开(公告)号：US07737469B2
公开(公告)日：2010-06-15
申请号：US11748869
申请日：2007-05-15
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L29/74
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/41741 , H01L29/7395 , H01L29/7397 , H01L29/7722 , H01L29/7806 , H01L29/7811 , H01L29/8611
摘要： A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.
摘要翻译：半导体器件包括：第一导电类型的半导体层; 设置在半导体层的主表面上的第一导电类型的第一半导体柱区域; 第二导电类型的第二半导体柱区域，与半导体层的主表面上的第一半导体柱区域相邻设置，第二半导体柱区域形成基本上平行于半导体层的主表面的周期性排列结构以及第一半导体柱区域; 第一主电极; 第二导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 第二主电极; 控制电极; 以及设置在包围第一半导体柱区域和第二半导体柱区域的边缘终端部分的半导体层上的高电阻半导体层。高电阻半导体层的掺杂浓度低于第一半导体柱区域。边界区域设置在设备中心区域和边缘终端部分之间。边界区域中与高电阻半导体层相邻的第一半导体柱区域和第二半导体柱区域具有沿着边缘终止部分逐步减小的深度。

4. 发明申请

US20080290403A1 SEMICONDUCTOR APPARATUS 失效
公开(公告)号：US20080290403A1
公开(公告)日：2008-11-27
申请号：US12123072
申请日：2008-05-19
申请人： Syotaro ONO , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Syotaro ONO , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0638 , H01L29/0878 , H01L29/7395 , H01L29/861 , H01L29/868 , H01L29/872
摘要： A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer provided on a major surface of the first semiconductor layer, a third semiconductor layer provided on the major surface and being adjacent to the second semiconductor layer, a termination semiconductor layer provided on the major surface of the first semiconductor layer in a termination region outside the device region, a channel stop layer, and a channel stop electrode. The channel stop layer is provided in contact with the termination semiconductor layer on the major surface of the first semiconductor layer in an outermost peripheral portion outside the termination semiconductor layer and has a higher impurity concentration than the termination semiconductor layer. The channel stop electrode is provided on at least part of a surface of the channel stop layer and projects toward the termination semiconductor layer beyond at least a superficial portion of the channel stop layer.
摘要翻译：半导体装置包括第一半导体层，设置在第一半导体层的主表面上的第二半导体层，设置在主表面上并与第二半导体层相邻的第三半导体层，设置在主体上的端接半导体层在器件区域外的终端区域中的第一半导体层的表面，沟道阻挡层和沟道停止电极。沟道阻挡层设置成与终端半导体层外部的最外周部分中的第一半导体层的主表面上的端接半导体层接触，并且具有比端接半导体层更高的杂质浓度。通道阻挡电极设置在通道阻挡层的表面的至少一部分上，并且朝向端子半导体层突出超过通道阻挡层的至少表面部分。

5. 发明授权

US07622771B2 Semiconductor apparatus 失效
标题翻译：半导体装置
公开(公告)号：US07622771B2
公开(公告)日：2009-11-24
申请号：US12123072
申请日：2008-05-19
申请人： Syotaro Ono , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Syotaro Ono , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L31/119 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0638 , H01L29/0878 , H01L29/7395 , H01L29/861 , H01L29/868 , H01L29/872
摘要： A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer provided on a major surface of the first semiconductor layer, a third semiconductor layer provided on the major surface and being adjacent to the second semiconductor layer, a termination semiconductor layer provided on the major surface of the first semiconductor layer in a termination region outside the device region, a channel stop layer, and a channel stop electrode. The channel stop layer is provided in contact with the termination semiconductor layer on the major surface of the first semiconductor layer in an outermost peripheral portion outside the termination semiconductor layer and has a higher impurity concentration than the termination semiconductor layer. The channel stop electrode is provided on at least part of a surface of the channel stop layer and projects toward the termination semiconductor layer beyond at least a superficial portion of the channel stop layer.
摘要翻译：半导体装置包括第一半导体层，设置在第一半导体层的主表面上的第二半导体层，设置在主表面上并与第二半导体层相邻的第三半导体层，设置在主体上的端接半导体层在器件区域外的终端区域中的第一半导体层的表面，沟道阻挡层和沟道停止电极。沟道阻挡层设置成与终端半导体层外部的最外周部分中的第一半导体层的主表面上的端接半导体层接触，并且具有比端接半导体层更高的杂质浓度。通道阻挡电极设置在通道阻挡层的表面的至少一部分上，并且朝向端子半导体层突出超过通道阻挡层的至少表面部分。

6. 发明授权

US08013360B2 Semiconductor device having a junction of P type pillar region and N type pillar region 有权
标题翻译：具有P型支柱区域和N型支柱区域的结的半导体器件
公开(公告)号：US08013360B2
公开(公告)日：2011-09-06
申请号：US12764763
申请日：2010-04-21
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L29/66
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/41741 , H01L29/7395 , H01L29/7397 , H01L29/7722 , H01L29/7806 , H01L29/7811 , H01L29/8611
摘要： A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.
摘要翻译：半导体器件包括：第一导电类型的半导体层; 设置在半导体层的主表面上的第一导电类型的第一半导体柱区域; 第二导电类型的第二半导体柱区域，与半导体层的主表面上的第一半导体柱区域相邻设置，第二半导体柱区域形成基本上平行于半导体层的主表面的周期性排列结构以及第一半导体柱区域; 第一主电极; 第二导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 第二主电极; 控制电极; 以及设置在包围第一半导体柱区域和第二半导体柱区域的边缘终端部分的半导体层上的高电阻半导体层。高电阻半导体层的掺杂浓度低于第一半导体柱区域。边界区域设置在设备中心区域和边缘终端部分之间。边界区域中与高电阻半导体层相邻的第一半导体柱区域和第二半导体柱区域具有沿着边缘终止部分逐步减小的深度。

7. 发明申请

US20100200936A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100200936A1
公开(公告)日：2010-08-12
申请号：US12764763
申请日：2010-04-21
申请人： Wataru SAITO , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Wataru SAITO , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L29/78
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/41741 , H01L29/7395 , H01L29/7397 , H01L29/7722 , H01L29/7806 , H01L29/7811 , H01L29/8611
摘要： A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.
摘要翻译：半导体器件包括：第一导电类型的半导体层; 设置在半导体层的主表面上的第一导电类型的第一半导体柱区域; 第二导电类型的第二半导体柱区域，与半导体层的主表面上的第一半导体柱区域相邻设置，第二半导体柱区域形成基本上平行于半导体层的主表面的周期性排列结构以及第一半导体柱区域; 第一主电极; 第二导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 第二主电极; 控制电极; 以及设置在包围第一半导体柱区域和第二半导体柱区域的边缘终端部分的半导体层上的高电阻半导体层。高电阻半导体层的掺杂浓度低于第一半导体柱区域。边界区域设置在设备中心区域和边缘终端部分之间。边界区域中与高电阻半导体层相邻的第一半导体柱区域和第二半导体柱区域具有沿着边缘终止部分逐步减小的深度。

8. 发明申请

US20070272979A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20070272979A1
公开(公告)日：2007-11-29
申请号：US11748869
申请日：2007-05-15
申请人： Wataru SAITO , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Wataru SAITO , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L29/76
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/41741 , H01L29/7395 , H01L29/7397 , H01L29/7722 , H01L29/7806 , H01L29/7811 , H01L29/8611
摘要： A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.
摘要翻译：半导体器件包括：第一导电类型的半导体层; 设置在半导体层的主表面上的第一导电类型的第一半导体柱区域; 第二导电类型的第二半导体柱区域，与半导体层的主表面上的第一半导体柱区域相邻设置，第二半导体柱区域形成基本上平行于半导体层的主表面的周期性排列结构以及第一半导体柱区域; 第一主电极; 第二导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 第二主电极; 控制电极; 以及设置在包围第一半导体柱区域和第二半导体柱区域的边缘终端部分的半导体层上的高电阻半导体层。高电阻半导体层的掺杂浓度低于第一半导体柱区域。边界区域设置在设备中心区域和边缘终端部分之间。边界区域中与高电阻半导体层相邻的第一半导体柱区域和第二半导体柱区域具有沿着边缘终止部分逐步减小的深度。

9. 发明申请

US20070272977A1 POWER SEMICONDUCTOR DEVICE 失效
标题翻译：功率半导体器件
公开(公告)号：US20070272977A1
公开(公告)日：2007-11-29
申请号：US11680912
申请日：2007-03-01
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/66712 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.
摘要翻译：功率半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层和形成在第一半导体层上的第二导电类型的第三半导体层，并且沿着平行于第一半导体层的表面的至少一个方向交替布置; 第一主电极; 选择性地形成在第二半导体层的表面和第三半导体层的表面上的第二导电类型的第四半导体层; 选择性地形成在第四半导体层的表面中的第一导电类型的第五半导体层; 第二主电极; 和控制电极。第二和第三半导体层中的至少一个具有沿着一个方向的掺杂剂浓度分布，掺杂剂浓度分布在其两端以外的位置处具有局部最小值。

10. 发明申请

US20100230750A1 POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件
公开(公告)号：US20100230750A1
公开(公告)日：2010-09-16
申请号：US12789008
申请日：2010-05-27
申请人： Wataru SAITO , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta
发明人： Wataru SAITO , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/66712 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.
摘要翻译：功率半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层和形成在第一半导体层上的第二导电类型的第三半导体层，并且沿着平行于第一半导体层的表面的至少一个方向交替布置; 第一主电极; 选择性地形成在第二半导体层的表面和第三半导体层的表面上的第二导电类型的第四半导体层; 选择性地形成在第四半导体层的表面中的第一导电类型的第五半导体层; 第二主电极; 和控制电极。第二和第三半导体层中的至少一个具有沿着一个方向的掺杂剂浓度分布，掺杂剂浓度分布在其两端以外的位置处具有局部最小值。

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