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1. 发明授权

US07989902B2 Scavenging metal stack for a high-k gate dielectric 有权
标题翻译：用于高k栅极电介质的清除金属堆叠
公开(公告)号：US07989902B2
公开(公告)日：2011-08-02
申请号：US12487248
申请日：2009-06-18
申请人： Takashi Ando , Changhwan Choi , Martin M. Frank , Vijay Narayanan
发明人： Takashi Ando , Changhwan Choi , Martin M. Frank , Vijay Narayanan
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy→2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.
摘要翻译：高k栅极电介质和金属栅极结构的堆叠包括下部金属层，清除金属层和上部金属层。清除金属层满足以下两个标准：1）反应Si + 2 / y MxOy→2x / y M + SiO2的吉布斯自由能变化为正的金属（M）2）具有更负的金属每个氧原子吉布斯自由能用于形成氧化物，而不是下金属层的材料和上金属层的材料。符合这些标准的清除金属层随着氧原子通过栅电极向高k栅极电介质扩散而捕获氧原子。此外，清除金属层远远地降低了高k电介质下面的氧化硅界面层的厚度。结果，即使在CMOS积分期间的高温处理之后，总栅极电介质的等效氧化物厚度（EOT）减小，并且场效应晶体管保持恒定的阈值电压。

2. 发明申请

US20090181505A1 METHOD AND APPARATUS FOR FABRICATING A HIGH-PERFORMANCE BAND-EDGE COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造高性能带边补充金属氧化物半导体器件的方法和装置
公开(公告)号：US20090181505A1
公开(公告)日：2009-07-16
申请号：US12013846
申请日：2008-01-14
申请人： Takashi Ando , Eduard A. Cartier , Changhwan Choi , Elizabeth A. Duch , Bruce B. Doris , Young-Hee Kim , Vijay Narayanan , James Pan , Vamsi K. Paruchuri
发明人： Takashi Ando , Eduard A. Cartier , Changhwan Choi , Elizabeth A. Duch , Bruce B. Doris , Young-Hee Kim , Vijay Narayanan , James Pan , Vamsi K. Paruchuri
IPC分类号： H01L21/8238
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L21/823871 , H01L27/1203 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665
摘要： In one embodiment, the invention is a method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device. One embodiment of a method for fabricating a complementary metal-oxide-semiconductor device includes fabricating an n-type metal-oxide-semiconductor device using a gate first process, and fabricating a p-type metal-oxide-semiconductor device using a gate last process.
摘要翻译：在一个实施例中，本发明是用于制造高性能带边互补金属氧化物半导体器件的方法和装置。用于制造互补金属氧化物半导体器件的方法的一个实施例包括使用栅极第一工艺制造n型金属氧化物半导体器件，以及使用栅极最后工艺制造p型金属氧化物半导体器件。

3. 发明授权

US09059314B2 Structure and method to obtain EOT scaled dielectric stacks 有权
标题翻译：获得EOT缩放电介质叠层的结构和方法
公开(公告)号：US09059314B2
公开(公告)日：2015-06-16
申请号：US13602118
申请日：2012-09-01
申请人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L21/00 , H01L21/8238 , H01L21/28 , H01L29/49 , H01L29/51
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.
摘要翻译：提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠材料掺杂元素。在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

4. 发明申请

US20130032886A1 Low Threshold Voltage And Inversion Oxide Thickness Scaling For A High-K Metal Gate P-Type MOSFET 审中-公开
标题翻译：高K金属栅P型MOSFET的低阈值电压和反转氧化层厚度缩放
公开(公告)号：US20130032886A1
公开(公告)日：2013-02-07
申请号：US13195316
申请日：2011-08-01
申请人： Takashi Ando , Changhwan Choi , Martin M. Frank , Unoh Kwon , Vijay Narayanan
发明人： Takashi Ando , Changhwan Choi , Martin M. Frank , Unoh Kwon , Vijay Narayanan
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/0922 , H01L21/823807 , H01L29/16 , H01L29/161 , H01L29/42364 , H01L29/4966 , H01L29/517
摘要： A structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in Tinv and Vt of the pFET, while scaling Tiny and maintaining Vt for the nFET, resulting in the Vt of the pFET becoming closer to the Vt of a similarly constructed nFET with scaled Tinv values.
摘要翻译：结构具有半导体衬底以及设置在衬底上的nFET和pFET。 pFET具有形成在半导体衬底的表面上或其表面上的半导体SiGe沟道区，以及覆盖沟道区的氧化物层和覆盖氧化物层的高k电介质层的栅极电介质。栅电极覆盖在栅极电介质上，并且具有邻接高k层的下金属层，邻接下金属层的清除金属层和与清除金属层邻接的上金属层。金属层清除了衬底（nFET）中的氧和与氧化物层的SiGe（pFET）界面，导致pFET的Tinv和Vt有效降低，同时缩小Tiny并维持nFET的Vt，导致Vt pFET变得更接近具有缩放Tinv值的类似构造的nFET的Vt。

5. 发明授权

US08343839B2 Scaled equivalent oxide thickness for field effect transistor devices 有权
标题翻译：场效应晶体管器件的等效氧化物厚度变化
公开(公告)号：US08343839B2
公开(公告)日：2013-01-01
申请号：US12788454
申请日：2010-05-27
申请人： Takashi Ando , Changhwan Choi , Unoh Kwon , Vijay Narayanan
发明人： Takashi Ando , Changhwan Choi , Unoh Kwon , Vijay Narayanan
IPC分类号： H01L21/8236
CPC分类号： H01L21/823842 , H01L21/02164 , H01L21/02697 , H01L21/28229 , H01L21/823857 , H01L29/517 , H01L29/518
摘要： A method for forming a field effect transistor device includes forming an oxide layer on a substrate, forming a dielectric layer on the oxide layer, forming a first TiN layer on the dielectric layer, forming a metallic layer on the first layer, forming a second TiN layer on the metallic layer, removing a portion of the first TiN layer, the metallic layer, and the second TiN layer to expose a portion of the dielectric layer, forming a layer of stoichiometric TiN on the exposed portion of the dielectric layer and the second TiN layer, heating the device, and forming a polysilicon layer on the device.
摘要翻译：一种形成场效应晶体管器件的方法包括在衬底上形成氧化物层，在氧化层上形成电介质层，在电介质层上形成第一TiN层，在第一层上形成金属层，形成第二TiN 去除一部分第一TiN层，金属层和第二TiN层以暴露介电层的一部分，在介电层的暴露部分上形成化学计量的TiN层，第二层 TiN层，加热器件，并在器件上形成多晶硅层。

6. 发明授权

US08304836B2 Structure and method to obtain EOT scaled dielectric stacks 有权
标题翻译：获得EOT缩放电介质堆叠的结构和方法
公开(公告)号：US08304836B2
公开(公告)日：2012-11-06
申请号：US12620234
申请日：2009-11-17
申请人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L21/70
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.
摘要翻译：提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠材料掺杂元素。在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

7. 发明申请

US20110115027A1 STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS 有权
标题翻译：结构和方法来获取电子尺寸的电介质堆叠
公开(公告)号：US20110115027A1
公开(公告)日：2011-05-19
申请号：US12620234
申请日：2009-11-17
申请人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L27/092 , H01L29/78 , H01L21/8238 , H01L21/263
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.
摘要翻译：提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠材料掺杂元素。在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

8. 发明申请

US20100320547A1 SCAVANGING METAL STACK FOR A HIGH-K GATE DIELECTRIC 有权
标题翻译：用于高K栅介质的SCAVANGING金属叠层
公开(公告)号：US20100320547A1
公开(公告)日：2010-12-23
申请号：US12487248
申请日：2009-06-18
申请人： Takashi Ando , Changhwan Choi , Martin M. Frank , Vijay Narayanan
发明人： Takashi Ando , Changhwan Choi , Martin M. Frank , Vijay Narayanan
IPC分类号： H01L29/78 , H01L21/314 , H01L21/336
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy→2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.
摘要翻译：高k栅极电介质和金属栅极结构的堆叠包括下部金属层，清除金属层和上部金属层。清除金属层满足以下两个标准：1）反应Si + 2 / y MxOy→2x / y M + SiO2的吉布斯自由能变化为正的金属（M）2）具有更负的金属每个氧原子吉布斯自由能用于形成氧化物，而不是下金属层的材料和上金属层的材料。符合这些标准的清除金属层随着氧原子通过栅电极向高k栅极电介质扩散而捕获氧原子。此外，清除金属层远远地降低了高k电介质下面的氧化硅界面层的厚度。结果，即使在CMOS积分期间的高温处理之后，总栅极电介质的等效氧化物厚度（EOT）减小，并且场效应晶体管保持恒定的阈值电压。

9. 发明申请

US20130154019A1 LOW THRESHOLD VOLTAGE CMOS DEVICE 有权
标题翻译：低电压电压CMOS器件
公开(公告)号：US20130154019A1
公开(公告)日：2013-06-20
申请号：US13327870
申请日：2011-12-16
申请人： Takashi Ando , Changhwan Choi , Kisik Choi , Vijay Narayanan
发明人： Takashi Ando , Changhwan Choi , Kisik Choi , Vijay Narayanan
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/02178 , H01L21/02192 , H01L21/28079 , H01L21/28088 , H01L21/28229 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/161 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A semiconductor device including an NMOS region and a PMOS region; the NMOS region having a gate structure including a first high-k gate dielectric, a first work function setting metal and a gate electrode fill material; the PMOS region having a gate structure comprising a second high-k gate dielectric, a second work function setting metal and a gate electrode fill material; wherein the first gate dielectric is different than the second gate dielectric and the first work function setting metal is different than the second work function setting metal. Also disclosed are methods for fabricating the semiconductor device which include a gate last process.
摘要翻译：一种包括NMOS区和PMOS区的半导体器件; 所述NMOS区域具有包括第一高k栅极电介质，第一功函数设定金属和栅电极填充材料的栅极结构; 所述PMOS区域具有包括第二高k栅极电介质，第二功函数设定金属和栅电极填充材料的栅极结构; 其中所述第一栅极电介质不同于所述第二栅极电介质，并且所述第一功函数设定金属与所述第二功函数设定金属不同。还公开了制造半导体器件的方法，其包括栅极最后工艺。

10. 发明授权

US08367496B2 Scavanging metal stack for a high-k gate dielectric 有权
标题翻译：用于高k栅介质的扫描金属堆叠
公开(公告)号：US08367496B2
公开(公告)日：2013-02-05
申请号：US13099790
申请日：2011-05-03
申请人： Takashi Ando , Changhwan Choi , Martin M. Frank , Vijay Narayanan
发明人： Takashi Ando , Changhwan Choi , Martin M. Frank , Vijay Narayanan
IPC分类号： H01L21/8238
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy→2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.
摘要翻译：高k栅极电介质和金属栅极结构的堆叠包括下部金属层，清除金属层和上部金属层。清除金属层满足以下两个标准：1）反应Si + 2 / y MxOy→2x / y M + SiO2的吉布斯自由能变化为正的金属（M）2）具有更负的金属每个氧原子吉布斯自由能用于形成氧化物，而不是下金属层的材料和上金属层的材料。符合这些标准的清除金属层随着氧原子通过栅电极向高k栅极电介质扩散而捕获氧原子。此外，清除金属层远远地降低了高k电介质下面的氧化硅界面层的厚度。结果，即使在CMOS积分期间的高温处理之后，总栅极电介质的等效氧化物厚度（EOT）减小，并且场效应晶体管保持恒定的阈值电压。

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