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1. 发明授权

US07832649B2 Method of making a plurality of protected devices in communication with a background device 有权
标题翻译：制造与背景设备通信的多个受保护设备的方法
公开(公告)号：US07832649B2
公开(公告)日：2010-11-16
申请号：US11951662
申请日：2007-12-06
申请人： Mark I Gardner , Dayton S. Whites , Dayton E. Whites , James Elliott Walters
发明人： Mark I Gardner , Dayton S. Whites , Dayton E. Whites , James Elliott Walters
IPC分类号： G06K19/06
CPC分类号： G06K19/06112
摘要： This invention includes a device to attach an identifying device to the item of interest. The identify device attached to the item of interest may be referred to as a protected device that can be kept in communication with a background device. A protected device is formed when a an item of interest such as a credit card, drivers license, or medical card has an identifying device attached to the item of interest that converts the item of interest to the protected device which protects an existing object of interest.
摘要翻译：本发明包括将识别装置附接到感兴趣的物品的装置。附加到感兴趣的项目的识别装置可以被称为可以保持与背景设备通信的受保护装置。当感兴趣的项目（例如信用卡，驾驶执照或医疗卡）具有附加到感兴趣的项目的识别装置时，形成受保护的装置，该识别装置将感兴趣的项目转换成保护现有感兴趣的对象的受保护装置。

2. 发明申请

US20090145970A1 Method of Making a Plurality of Protected Devices in Communication with a Background Device 有权
标题翻译：使多个受保护设备与后台设备通信的方法
公开(公告)号：US20090145970A1
公开(公告)日：2009-06-11
申请号：US11951662
申请日：2007-12-06
申请人： Mark I. Gardner , Dayton S. Whites , Dayton E. Whites , James Elliott Walters
发明人： Mark I. Gardner , Dayton S. Whites , Dayton E. Whites , James Elliott Walters
IPC分类号： G06K19/06
CPC分类号： G06K19/06112
摘要： This invention includes a device to attach an identifying device to the item of interest. The identify device attached to the item of interest may be referred to as a protected device that can be kept in communication with a background device. A protected device is formed when a an item of interest such as a credit card, drivers license, or medical card has an identifying device attached to the item of interest that converts the item of interest to the protected device (which protects an existing object of interest).
摘要翻译：本发明包括将识别装置附接到感兴趣的物品的装置。附加到感兴趣的项目的识别装置可以被称为可以保持与背景设备通信的受保护装置。当感兴趣的项目（例如信用卡，驾驶执照或医疗卡）具有附加到感兴趣的项目的识别装置时，形成受保护的装置，所述识别装置将感兴趣的项目转换为受保护的装置（其保护现有的对象利益）。

3. 发明授权

US06911707B2 Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor device performance 有权
标题翻译：具有良好的界面性能的超薄高K栅极电介质，可提高半导体器件的性能
公开(公告)号：US06911707B2
公开(公告)日：2005-06-28
申请号：US09207972
申请日：1998-12-09
申请人： Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford, Jr.
IPC分类号： H01L21/28 , H01L21/314 , H01L29/51 , H01L29/76
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/3144 , H01L29/513 , H01L29/517 , H01L29/518
摘要： An ultrathin gate dielectric having a graded dielectric constant and a method for forming the same are provided. The gate dielectric is believed to allow enhanced performance of semiconductor devices including transistors and dual-gate memory cells. A thin nitrogen-containing oxide, preferably having a thickness of less than about 10 angstroms, is formed on a semiconductor substrate. A silicon nitride layer having a thickness of less than about 30 angstroms may be formed over the nitrogen-containing oxide. The oxide and nitride layers are annealed in ammonia and nitrous oxide ambients, and the nitride layer thickness is reduced using a flowing-gas etch process. The resulting two-layer gate dielectric is believed to provide increased capacitance as compared to a silicon dioxide dielectric while maintaining favorable interface properties with the underlying substrate. In an alternative embodiment, a different high dielectric constant material is substituted for the silicon nitride. Alternatively, both nitride and a different high dielectric constant material may be used so that a three-layer dielectric is formed.
摘要翻译：提供具有渐变介电常数的超薄栅极电介质及其形成方法。认为栅极电介质允许包括晶体管和双栅极存储器单元的半导体器件的增强的性能。在半导体衬底上形成薄的含氮氧化物，优选具有小于约10埃的厚度。可以在含氮氧化物上形成厚度小于约30埃的氮化硅层。氧化物和氮化物层在氨和一氧化二氮环境中退火，并且使用流动气体蚀刻工艺来减少氮化物层的厚度。与二氧化硅电介质相比，所得到的双层栅极电介质被认为提供增加的电容，同时保持与底层衬底的有利的界面性质。在替代实施例中，用不同的高介电常数材料代替氮化硅。或者，可以使用氮化物和不同的高介电常数材料，从而形成三层电介质。

4. 发明授权

US06433400B1 Semiconductor fabrication employing barrier atoms incorporated at the edges of a trench isolation structure 有权
标题翻译：半导体制造采用掺入沟槽隔离结构边缘的势垒原子
公开(公告)号：US06433400B1
公开(公告)日：2002-08-13
申请号：US09153753
申请日：1998-09-15
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L2936
CPC分类号： H01L21/02233 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/31612 , H01L21/76237
摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 Å. The semiconductor topography is then exposed to a barrier-entrained gas and heated so that barrier atoms become incorporated in regions of the active areas in close proximity to the trench isolation structure. The masking layer may prevent the barrier atoms from being incorporated into any other regions of the substrate.
摘要翻译：一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。该方法包括在半导体衬底上形成电介质掩模层。然后通过掩模层形成开口。在开口内的掩模层的侧壁上形成一对电介质隔离物。然后在电介质间隔物之间的半导体衬底中蚀刻沟槽。然后在沟槽的壁和基底上热生长第一介电层。将CVD氧化物沉积到沟槽中并进行处理，使得CVD氧化物的上表面与衬底表面相当。间隔物的一部分也被去除，使得间隔物的厚度在约0至200埃之间。然后将半导体形貌暴露于阻挡夹带气体并加热，使得势垒原子并入到紧邻沟槽隔离结构的有源区域的区域中。掩模层可以防止阻挡原子被结合到衬底的任何其它区域中。

5. 发明授权

US06417539B2 High density memory cell assembly and methods 有权
标题翻译：高密度存储单元组装及方法
公开(公告)号：US06417539B2
公开(公告)日：2002-07-09
申请号：US09128864
申请日：1998-08-04
申请人： Mark I. Gardner , Derick J. Wristers , Jon Cheek
发明人： Mark I. Gardner , Derick J. Wristers , Jon Cheek
IPC分类号： H01L2976
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： A memory cell assembly includes a substrate, a first electrode, and a second electrode layer. The first electrode is disposed over the substrate and the second electrode layer is disposed over the first electrode. The second electrode layer includes two or more second electrodes. Dielectric material separates the first electrode form the second electrodes and also separates the second electrodes. Each second electrode forms an individual memory cell associated with the first electrode. The memory cell assembly can be made by, first, forming a first electrode over a substrate. A second electrode layer is formed over the first electrode. The second electrode layer includes two or more second electrodes. A dielectric material is formed between the first electrode and the second electrodes and between the second electrodes.
摘要翻译：存储单元组件包括衬底，第一电极和第二电极层。第一电极设置在衬底上，并且第二电极层设置在第一电极上。第二电极层包括两个或更多个第二电极。电介质材料将第一电极与第二电极分开，并分离第二电极。每个第二电极形成与第一电极相关联的单个存储单元。存储单元组件可以通过首先在衬底上形成第一电极来制造。在第一电极上形成第二电极层。第二电极层包括两个或更多个第二电极。在第一电极和第二电极之间以及第二电极之间形成电介质材料。

6. 发明授权

US06362510B1 Semiconductor topography having improved active device isolation and reduced dopant migration 有权
标题翻译：半导体形貌具有改进的有源器件隔离和减少掺杂剂迁移
公开(公告)号：US06362510B1
公开(公告)日：2002-03-26
申请号：US09206550
申请日：1998-12-07
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L2976
CPC分类号： H01L21/28202 , H01L21/02381 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02639 , H01L21/2822 , H01L21/762 , H01L29/1083 , H01L29/36 , H01L29/518 , H01L29/6659 , H01L29/66651
摘要： A method for fabricating an integrated circuit is presented wherein a semiconductor substrate is provided having a dielectric layer formed on its upper surface. A groove is formed in the dielectric layer that extends from the upper surface of the semiconductor substrate to the upper surface of the dielectric layer. A silicon epitaxial layer is then grown within the groove. Barrier atoms are incorporated into the silicon epitaxial layer concurrently with the epitaxial growth process.
摘要翻译：提出一种用于制造集成电路的方法，其中提供了在其上表面上形成有电介质层的半导体衬底。在从半导体衬底的上表面延伸到电介质层的上表面的电介质层中形成凹槽。然后在沟槽内生长硅外延层。阻挡原子与外延生长工艺同时并入硅外延层。

7. 发明授权

US06358828B1 Ultra high density series-connected transistors formed on separate elevational levels 失效
标题翻译：超高密度串联晶体管形成在不同的高程
公开(公告)号：US06358828B1
公开(公告)日：2002-03-19
申请号：US09118514
申请日：1998-07-17
申请人： Daniel Kadosh , Mark I. Gardner
发明人： Daniel Kadosh , Mark I. Gardner
IPC分类号： H01L213205
CPC分类号： H01L27/0688
摘要： A three-dimensional integrated circuit and fabrication process is provided for producing active and passive devices on various levels of the integrated circuit. The present process is particularly suited to interconnecting a source of one transistor to a drain of another to form series-connected transistors often employed in core logic units. A junction of an underlying transistor can be connected to a junction of an overlying transistor, with both transistors separated by an interlevel dielectric. The lower transistor junction is connected to the upper level transistor junction using a plug conductor. The plug conductor and, more specifically, the mutually connected junction, is further coupled to a laterally extended interconnect. The interconnect extends from the mutual connection point of the plug conductor to a substrate of the overlying transistor. Accordingly, the source and substrate of the overlying transistor can be connected to a drain of the underlying transistor to not only achieve series-connection but also to connect the source and substrate of an internally configured transistor for the purpose of reducing body effects.
摘要翻译：提供三维集成电路和制造工艺，用于在集成电路的各种级别上产生有源和无源器件。本方法特别适用于将一个晶体管的源极互连到另一个晶体管的漏极，以形成通常用于核心逻辑单元的串联连接的晶体管。底层晶体管的结可以连接到上覆晶体管的结，两个晶体管由层间电介质分隔开。下部晶体管结使用插头导体连接到上层晶体管结。插头导体，更确切地说，相互连接的连接部分进一步耦合到横向延伸的互连。互连从插头导体的相互连接点延伸到上覆晶体管的衬底。因此，覆盖晶体管的源极和衬底可以连接到下面的晶体管的漏极，以便不仅实现串联连接，而且连接内部构造的晶体管的源极和衬底以减少体效应。

8. 发明授权

US06306763B1 Enhanced salicidation technique 失效
标题翻译：增强盐化技术
公开(公告)号：US06306763B1
公开(公告)日：2001-10-23
申请号：US08896397
申请日：1997-07-18
申请人： Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518
摘要： A semiconductor fabrication process in which enhanced salicidation and reliability is achieved by implanting a silicon bearing species and a nitrogen bearing species into the source/drain regions and polysilicon regions of an integrated circuit transistor prior to the silicide formation sequence. A gate dielectric is formed on an upper surface of a semiconductor substrate. The substrate includes an active region that is laterally disposed between a pair of isolation structures. The active region includes a channel region that is laterally disposed between a pair of source/drain regions. A conductive gate structure is formed on the upper surface of the semiconductor substrate aligned over the channel region A silicon bearing species is then implanted or otherwise introduced into the conductive gate structure and into the source/drain regions to form amorphous silicon rich regions proximal to respective upper surfaces of the source/drain regions and the conductive gate structure. A nitrogen bearing species is then implanted into the conductive gate source/drain regions and a source/drain impurity distribution is introduced into the source/drain regions. A self aligned silicide process, in which a refractory metal is deposited upon the substrate upper surface and heated to a reaction temperature to form a silicide compound over exposed silicon regions of the substrate, preferably follows the formation of the source/drain regions
摘要翻译：半导体制造工艺，其中通过在硅化物形成顺序之前将含硅物质和含氮物质注入到集成电路晶体管的源极/漏极区域和多晶硅区域中来实现增强的盐化和可靠性。在半导体衬底的上表面上形成栅电介质。衬底包括侧向设置在一对隔离结构之间的有源区。有源区包括横向设置在一对源/漏区之间的沟道区。在沟道区域A上对准的半导体衬底的上表面上形成导电栅极结构。然后将硅轴承种类注入或以其它方式引入导电栅极结构并进入源极/漏极区，以形成靠近相应的非晶硅富集区源极/漏极区域和导电栅极结构的上表面。然后将氮含量物质注入到导电栅极源极/漏极区域中，并且将源极/漏极杂质分布引入到源极/漏极区域中。一种自对准的硅化物工艺，其中难熔金属沉积在衬底上表面上并被加热至反应温度以在衬底的暴露的硅区域上形成硅化物，优选地遵循形成源极/漏极区域

9. 发明授权

US06300661B1 Mutual implant region used for applying power/ground to a source of a transistor and a well of a substrate 失效
标题翻译：用于将功率/接地施加到晶体管的源极和基底阱的相互注入区域
公开(公告)号：US06300661B1
公开(公告)日：2001-10-09
申请号：US09060509
申请日：1998-04-14
申请人： Daniel Kadosh , Mark I. Gardner , Michael P. Duane
发明人： Daniel Kadosh , Mark I. Gardner , Michael P. Duane
IPC分类号： H01L2976
CPC分类号： H01L21/823425 , H01L21/823493 , H01L27/088 , Y10S257/928
摘要： An integrated circuit fabrication process is provided for forming, a mutual implant region within a well which is shared by a source region of a transistor residing within the well and a well-tie region coupled to the well, thereby providing a single electrical link to the well and the source region. Contacts may be coupled to the mutual implant region, and a conductor may be connected to the contacts. In the instance that the well is a p-type well in which NMOS transistors are formed, a ground voltage may be applied to the conductor to bias both the source region and the well. On the other hand, if the well is an n-type well in which PMOS transistors are formed, a power voltage, VCC, may be applied to the conductor to bias both the source region and the well. Absent the need to form contacts to both the source region and the well-tie region and conductors to such contacts, less space is required to bias the well and the source region. Also, merging a portion of the well-tie region with a portion of the source region affords increased packing density of an integrated circuit. The higher packing density is achieved without resorting to decreasing the dimensions of the well-tie region, and thus without detrimentally increasing the resistance of the well-tie region.
摘要翻译：提供了一种集成电路制造工艺，用于在阱内形成由位于阱内的晶体管的源极区域和耦合到阱的阱区域共享的阱内的相互注入区域，从而提供到该阱的单个电连接井和源区。触点可以耦合到相互植入区域，并且导体可以连接到触点。在阱是其中形成NMOS晶体管的p型阱的情况下，可以将接地电压施加到导体以偏置源极区域和阱。另一方面，如果阱是其中形成有PMOS晶体管的n型阱，则可以将电源电压VCC施加到导体以偏置源极区域和阱。不需要形成与源极区域和连接区域的接触以及与这些触点的导体的接触，所以需要较少的空间来偏置阱和源极区域。而且，将一部分连接区域与源区域的一部分合并，可以提高集成电路的堆积密度。填充密度更高，而不需要减小连接区域的尺寸，从而不会不利地增加连接区域的阻力。

10. 发明授权

US06288432B1 Semiconductor fabrication employing a post-implant anneal within a low temperature, high pressure nitrogen ambient to improve channel and gate oxide reliability 有权
标题翻译：半导体制造采用在低温，高压氮气环境中的植入后退火以改善沟道和栅极氧化物的可靠性
公开(公告)号：US06288432B1
公开(公告)日：2001-09-11
申请号：US09481808
申请日：2000-01-11
申请人： Fred N. Hause , Mark I. Gardner
发明人： Fred N. Hause , Mark I. Gardner
IPC分类号： H01L2976
CPC分类号： H01L29/7833 , H01L21/28176 , H01L21/823418 , H01L29/518 , H01L29/6659
摘要： An integrated circuit is formed with minimal encroachment of lightly doped drain (LDD) implants partially due to barrier atoms incorporated along the migration avenues. Nitrogen is incorporated either during the LDD implant or during an anneal cycle following the LDD implant. Nitrogen helps minimize segregation and diffusion of LDD dopants placed adjacent critical channel and gate dielectric areas. Nitrogen is incorporated within a chamber while under pressure so as to minimize the temperature needed to repair implant damage and activate the LDD dopants. High pressure indoctrination of nitrogen is believed to provide the same amount of lattice repair and activation achieved if anneal temperatures were substantially higher.
摘要翻译：形成集成电路，其部分原因是由于沿着迁移通道并入的屏障原子，轻掺杂漏极（LDD）植入物的侵入最小。在LDD植入期间或在LDD植入物之后的退火循环期间也掺入氮。氮有助于最小化邻近关键通道和栅极电介质区域放置的LDD掺杂物的分离和扩散。氮气在压力下并入室内，以便最小化修复植入物损伤和激活LDD掺杂剂所需的温度。如果退火温度显着较高，则认为氮气的高压灌注可提供相同量的晶格修复和激活。

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