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    • 7. 发明申请
    • METHOD FOR DEFECT REDUCTION FOR MEMORY CELL CAPACITORS
    • 用于存储单元电容器的减少缺陷的方法
    • US20100003794A1
    • 2010-01-07
    • US12259138
    • 2008-10-27
    • Ling JinDah Cheng LinChin Hsing YuMeng Jan CherngHuan Sung Fu
    • Ling JinDah Cheng LinChin Hsing YuMeng Jan CherngHuan Sung Fu
    • H01L21/8242
    • H01L28/91H01L27/10852H01L27/10894
    • A method for forming a cylindrical stack capacitor structure. A semiconductor substrate is provided. Storage node structures are formed in a memory cell region. A dielectric layer is formed overlying the storage node structures. A patterning and a first etching process expose the storage nodes. A polysilicon layer and a rugged polysilicon layer are formed overlying the exposed storage nodes. The memory cell region is masked, exposing a peripheral region. A chemical dry etch process removes the rugged polysilicon and the polysilicon layers in the peripheral region. The rugged polysilicon and the polysilicon layers are planarized followed by a dielectric recess. The resulting cylindrical stack capacitor structures are substantially free of defects from rugged polysilicon remaining in the peripheral region thereby improving device yield and process window.
    • 一种形成圆柱形堆叠电容器结构的方法。 提供半导体衬底。 存储节点结构形成在存储单元区域中。 在存储节点结构上形成介电层。 图案化和第一蚀刻工艺暴露存储节点。 在暴露的存储节点上形成多晶硅层和坚固的多晶硅层。 掩蔽存储单元区域,暴露外围区域。 化学干蚀刻工艺去除了外围区域中的坚固的多晶硅和多晶硅层。 凹凸多晶硅和多晶硅层被平坦化,随后是电介质凹陷。 所得到的圆柱形堆叠电容器结构基本上没有残留在外围区域中的粗糙多晶硅的缺陷,从而提高了器件产量和工艺窗口。