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1. 发明授权

US5346518A Vapor drain system 失效
标题翻译：蒸气排放系统
公开(公告)号：US5346518A
公开(公告)日：1994-09-13
申请号：US35999
申请日：1993-03-23
申请人： Robert J. Baseman , Charles A. Brown , Benjamin N. Eldridge , Laura B. Rothman , Herman R. Wendt , James T. Yeh , Arthur R. Zingher
发明人： Robert J. Baseman , Charles A. Brown , Benjamin N. Eldridge , Laura B. Rothman , Herman R. Wendt , James T. Yeh , Arthur R. Zingher
IPC分类号： B65D85/86 , B65G1/00 , H01L21/673 , H01L21/677 , B65B5/00 , B65D81/26 , B65D85/62 , F17C11/00
CPC分类号： H01L21/67366 , B65G1/00 , H01L21/67393
摘要： During wafer fabrication, a transportable enclosure, such as a Standard Manufacturing InterFace (SMIF) pod encloses a nascent product, such as a semiconductor wafer, to protect the wafer against contamination during manufacture, storage or transportation. However chemical vapors emitted inside the pod can accumulate in the air and degrade wafers during subsequent fabrication. In order to absorb the vapors inside a closed pod, a vapor removal element typically including an activated carbon absorber, covered by a particulate-filtering vapor-permeable barrier, and covered by a guard plate with holes is disposed within the enclosure. A vapor removal element is disposed closely adjacent to each respective wafer. Alternatively, a single vapor removal element is located inside the enclosure. In certain instances, a fan or thermo-buoyant circulation causes any vapors located inside the enclosure to a vapor removal element for removal. Alternatively a porous vapor removal element may be disposed for removing vapors from air entering the enclosure. In another embodiment a vapor removal element is integrated with the back face of each wafer.
摘要翻译：在晶片制造期间，诸如标准制造界面（SMIF）的可移动外壳包围新生产品，例如半导体晶片，以在制造，存储或运输期间保护晶片免受污染。然而，发射在荚内的化学气体可能积聚在空气中，并在随后的制造过程中降解晶片。为了吸收封闭的容器内的蒸气，通常包括活性炭吸收器的蒸气去除元件被覆盖有颗粒过滤蒸气可透过的屏障并被具有孔的保护板覆盖。蒸汽去除元件被设置为紧邻每个相应的晶片。或者，单个蒸气去除元件位于外壳内。在某些情况下，风扇或热浮动循环使得位于外壳内部的任何蒸气成为除去蒸气的元件。或者，可以设置多孔蒸气去除元件以从进入外壳的空气中除去蒸汽。在另一个实施例中，蒸气去除元件与每个晶片的背面一体化。

2. 发明授权

US4447824A Planar multi-level metal process with built-in etch stop 失效
标题翻译：平面多级金属工艺，内置蚀刻停止
公开(公告)号：US4447824A
公开(公告)日：1984-05-08
申请号：US416437
申请日：1982-09-10
申请人： Joseph S. Logan , John L. Mauer, IV , Laura B. Rothman , Geraldine C. Schwartz , Charles L. Standley
发明人： Joseph S. Logan , John L. Mauer, IV , Laura B. Rothman , Geraldine C. Schwartz , Charles L. Standley
IPC分类号： H01L21/48 , H01L21/768 , H01L23/522 , H01L29/34 , H01L29/44 , H01L29/52
CPC分类号： H01L21/7688 , H01L21/4846 , H01L23/5226 , H01L2924/0002 , H01L2924/09701
摘要： Use of a dual composite mask for a lift-off multi-layered structure process in which a base component layer acts as an etch stop for reactive ion etching of overlying layers.
摘要翻译：使用双重复合掩模用于剥离多层结构工艺，其中基底组分层用作用于上覆层的反应离子蚀刻的蚀刻停止层。

3. 发明授权

US4367119A Planar multi-level metal process with built-in etch stop 失效
标题翻译：平面多级金属工艺，内置蚀刻停止
公开(公告)号：US4367119A
公开(公告)日：1983-01-04
申请号：US179145
申请日：1980-08-18
申请人： Joseph S. Logan , John L. Mauer, IV , Laura B. Rothman , Geraldine C. Schwartz , Charles L. Standley
发明人： Joseph S. Logan , John L. Mauer, IV , Laura B. Rothman , Geraldine C. Schwartz , Charles L. Standley
IPC分类号： H01L21/3205 , H01L21/48 , H01L21/768 , H01L23/522 , B44C1/22 , C03C15/00 , C03C25/06 , C23F1/02
CPC分类号： H01L23/5226 , H01L21/4846 , H01L21/7688 , H01L2924/0002 , H01L2924/09701 , Y10S438/951
摘要： Use of a dual composite mask for a lift-off multi-layered structure process in which a base component layer acts as an etch stop for reactive ion etching of overlying layers.
摘要翻译：使用双重复合掩模用于剥离多层结构工艺，其中基底组分层用作用于上覆层的反应离子蚀刻的蚀刻停止层。

4. 发明授权

US4272561A Hybrid process for SBD metallurgies 失效
标题翻译： SBD冶金的混合工艺
公开(公告)号：US4272561A
公开(公告)日：1981-06-09
申请号：US43416
申请日：1979-05-29
申请人： Laura B. Rothman , Paul A. Totta , James F. White
发明人： Laura B. Rothman , Paul A. Totta , James F. White
IPC分类号： H01L21/306 , H01L21/027 , H01L21/28 , H01L21/285 , H01L21/338 , H01L23/485 , H01L21/283 , H01L29/48
CPC分类号： H01L29/66848 , H01L21/0272 , H01L21/28 , H01L21/28512 , H01L23/4855 , H01L2924/0002 , H01L2924/09701 , Y10S438/951
摘要： A method for forming thin film patterns in the fabrication of integrated circuits utilizing a lift-off mask in an inverse vertical relationship with the desired metal film. The method involves the preliminary blanket deposition of the metal in-point, followed by a coating of a patterned lift-off mask over which is blanket coated a dry-etch resistant material with subsequent removal of the lift-off mask, and dry etching of the exposed metal film. In one embodiment the dry-etch mask can comprise a diverse metal layer when a dry-etch ambient is employed which is passive to the diverse metal. In another embodiment, where dry etch ambients are employed which are corrosive to the diverse metal which is desired in the final structure, it can be covered with a blanket layer of any convenient dry-etch resistant material, such as magnesium oxide, prior to removal of the lift-off mask. This method has effective application in the fabrication of Schottky barrier diodes, transistors, and other electronic components or discrete and integrated devices requiring high quality metal to semiconductor junctions or interfaces.
摘要翻译：在利用与期望的金属膜成反向垂直关系的剥离掩模的集成电路的制造中形成薄膜图案的方法。该方法包括金属入点的初步覆盖沉积，随后涂覆图案化剥离掩模，在其上涂覆耐干腐蚀材料，随后除去剥离掩模，并干法蚀刻暴露的金属膜。在一个实施例中，当使用干蚀刻环境时，干蚀刻掩模可以包括不同的金属层，其对于多种金属是被动的。在另一个实施方案中，当采用对最终结构中所需的多种金属具有腐蚀性的干蚀刻环境时，其可以在除去之前用诸如氧化镁的任何方便的耐干蚀刻材料的覆盖层覆盖的剥离面具。该方法在制造肖特基势垒二极管，晶体管和其它电子元件或需要高质量金属至半导体结或接口的离散和集成器件方面具有有效的应用。

5. 发明授权

US4222792A Planar deep oxide isolation process utilizing resin glass and E-beam exposure 失效
标题翻译：采用树脂玻璃和电子束曝光的平面深氧化物隔离工艺
公开(公告)号：US4222792A
公开(公告)日：1980-09-16
申请号：US73593
申请日：1979-09-10
申请人： Reginald F. Lever , John L. Mauer, IV , Alwin E. Michel , Laura B. Rothman
发明人： Reginald F. Lever , John L. Mauer, IV , Alwin E. Michel , Laura B. Rothman
IPC分类号： H01L21/76 , H01L21/31 , H01L21/312 , H01L21/316 , H01L21/762 , H01L21/26
CPC分类号： H01L21/316 , H01L21/3121 , H01L21/76229 , Y10S148/131
摘要： A planar deep oxide isolation process for providing deep wide silicon dioxide filled trenches in the planar surface of a silicon semiconductor substrate, said process comprising the steps:(a) forming deep wide trenches in the planar surface of the silicon substrate;(b) forming a thin layer of silicon dioxide on the planar surface of the silicon substrate and the exposed silicon surfaces of said deep wide trenches;(c) applying resin glass (polysiloxane) to the planar surface of said semiconductor substrate and within said deep wide trenches;(d) spinning off at least a portion of the resin glass on the planar surface of the substrate;(e) baking the substrate at a low temperature;(f) exposing the resin glass contained within the deep wide trenches of substrate to the energy of an E-beam;(g) developing the resin glass contained on said substrate in a solvent;(h) heating said substrate in oxygen to convert said resin glass contained within said deep wide trenches to silicon dioxide;(i) depositing a layer of silicon dioxide to provide a planar silicon dioxide surface on the exposed the surface of said substrate; and(j) planarize exposed silicon dioxide surface to silicon of substrate.A planar deep oxide isolation process for providing deep wide silicon dioxide filled trenches in the planar surface of a silicon semiconductor substrate as recited in the preceding paragraph, wherein the following steps are performed in lieu of step i of claim 1, said steps comprising:(i-1) apply a second thin layer of resin glass; and(i-2) convert said resin glass to silicon dioxide.
摘要翻译：一种用于在硅半导体衬底的平面表面中提供深宽二氧化硅填充沟槽的平面深氧化物隔离工艺，所述方法包括以下步骤：（a）在硅衬底的平面表面中形成深宽沟槽; （b）在硅衬底的平面表面和所述深宽沟槽的暴露的硅表面上形成二氧化硅薄层; （c）将树脂玻璃（聚硅氧烷）施加到所述深宽沟槽的所述半导体衬底的平面上; （d）在所述基板的平面上剥离所述树脂玻璃的至少一部分; （e）在低温下烘烤该基材; （f）将包含在基底的深宽沟槽内的树脂玻璃暴露于电子束的能量; （g）在溶剂中显影所述基板上所含的树脂玻璃; （h）在氧气中加热所述衬底以将包含在所述深宽沟槽内的所述树脂玻璃转化为二氧化硅; （i）沉积二氧化硅层以在所述衬底的暴露的表面上提供平面二氧化硅表面; 和（j）将暴露的二氧化硅表面平坦化到衬底的硅。一种用于在前述段落中提供的硅半导体衬底的平坦表面中提供深宽二氧化硅填充沟槽的平面深氧化物隔离工艺，其中执行以下步骤代替权利要求1的步骤i，所述步骤包括：（ i-1）涂一层树脂玻璃; 和（i-2）将所述树脂玻璃转化为二氧化硅。

6. 发明授权

US4396458A Method for forming planar metal/insulator structures 失效
标题翻译：用于形成平面金属/绝缘体结构的方法
公开(公告)号：US4396458A
公开(公告)日：1983-08-02
申请号：US333196
申请日：1981-12-21
申请人： Valeria Platter , Laura B. Rothman , Paul M. Schaible , Geraldine C. Schwartz
发明人： Valeria Platter , Laura B. Rothman , Paul M. Schaible , Geraldine C. Schwartz
IPC分类号： H01L21/3205 , H01L21/302 , H01L21/3065 , H01L21/3213 , H01L21/48 , H01L21/768 , H01L23/498 , H01L23/532 , H05K3/46 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L23/53223 , H01L21/4846 , H01L21/76801 , H01L21/7688 , H01L21/76886 , H01L23/49866 , H01L2924/0002 , H01L2924/09701 , H05K3/4647 , Y10S438/951
摘要： Formation of planar conductor/insulator semiconductor devices utilizing hafnium coated aluminum based metallization with a magnesium oxide mask for dry etching of the metallization and deposition of planar insulation.The hafnium coating is used to protect the aluminum metallization during mask removal, and as a registration enhancer for subsequent electron-beam processing.
摘要翻译：使用具有氧化镁掩模的铪涂覆的铝基金属化形成平面导体/绝缘体半导体器件，用于干蚀刻金属化和平面绝缘的沉积。铪涂层用于在掩模去除期间保护铝金属化，以及用作随后的电子束加工的配准增强剂。

7. 发明授权

US4933635A In-line process monitors for thin film wiring 失效
标题翻译：用于薄膜接线的在线工艺监控
公开(公告)号：US4933635A
公开(公告)日：1990-06-12
申请号：US288390
申请日：1988-12-22
申请人： Alina Deutsch , Modest M. Oprysko , John J. Ritsko , Laura B. Rothman , Helen L. Yeh , Atilio Zupicich
发明人： Alina Deutsch , Modest M. Oprysko , John J. Ritsko , Laura B. Rothman , Helen L. Yeh , Atilio Zupicich
IPC分类号： H01L21/66 , G01R31/28 , H01L23/544
CPC分类号： H01L22/34 , G01R31/2818 , H01L2224/16 , H01L2924/01014 , H01L2924/01037 , H01L2924/15192 , H01L2924/3011
摘要： A thin film region 14 of a multichip carrier 10 is provided with at least one fabrication process or tooling monitor for monitoring the quality of the fabrication process during the sequential formation of the layers of the region 14. The process monitor is formed with a desired layer or layers of the thin film region, such as by a photolithographic process. A centrally disposed active wiring region 30 of a layer is surrounded by peripherally disposed fabrication monitor sites 32. The sites 32 can be located such that they do not occupy or interfere with the surface area required for the wiring region 30 while still being disposed near enough to the wiring region such that the electrical and physical characteristics of the thin film is substantially the same. Four different types of thin film fabrication process monitors are disclosed, including a line/via monitor, a dielectric monitor, a laser assisted repair monitor and a laser assisted engineering change monitor.

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