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    • 1. 发明授权
    • Display panels
    • 显示面板
    • US07705840B2
    • 2010-04-27
    • US11456596
    • 2006-07-11
    • Chun-Ching WeiHung-Hsiao LinKun-Hong ChenYang-En Wu
    • Chun-Ching WeiHung-Hsiao LinKun-Hong ChenYang-En Wu
    • G06F3/038
    • G09G3/3659G09G2300/0804G09G2300/0814
    • Display panels capable of eliminating reliability issues due to high switching frequency. The display panel comprises a data driver outputting first, second, third and fourth data signals in sequence through a data line, a scan driver outputting first and second scan signals in sequence through first and second scan lines and an auxiliary driver generates first and second auxiliary signals in sequence, and first and second display cells commonly receives the first scan signal through the first scan line and receives the first and the second data signal through the data line, and a first switch is coupled to the data line and the second display cell, turning on and off in sequence according to the first auxiliary signal when the first scan signal is applied thereto such that the second and the first display cells receive the first and the second data signals in sequence.
    • 显示面板能够消除由于高开关频率引起的可靠性问题。 显示面板包括通过数据线依次输出第一,第二,第三和第四数据信号的数据驱动器,扫描驱动器依次通过第一和第二扫描线输出第一和第二扫描信号,辅助驱动器产生第一和第二辅助 信号,第一和第二显示单元通常通过第一扫描线接收第一扫描信号,并通过数据线接收第一和第二数据信号,第一开关耦合到数据线和第二显示单元 ,当施加第一扫描信号时,根据第一辅助信号依次接通和断开,使得第二和第一显示单元依次接收第一和第二数据信号。
    • 2. 发明申请
    • Fan-out wire structure for a display panel
    • 用于显示面板的扇出线结构
    • US20070039706A1
    • 2007-02-22
    • US11438382
    • 2006-05-22
    • Kun-Hong ChenWen-Rei Guo
    • Kun-Hong ChenWen-Rei Guo
    • D21F1/00
    • G02F1/1345
    • A fan-out wire structure is used to connect a driver and a display region of a display panel and has a plurality of first single-layer wires and at least one second single-layer wire. The first ends of the first single-layer wires are connected to the driver, and the second ends of the first single-layer wires are connected to the display area. The first end of the second single-layer wire is connected to the driver, and the second end of the second single-layer wire is connected to the display area. A metal layer of the first single-layer wires is different from a metal layer of the second single-layer wire.
    • 使用扇形线结构来连接显示面板的驱动器和显示区域,并且具有多个第一单层电线和至少一个第二单层电线。 第一单层电线的第一端连接到驱动器,第一单层电线的第二端连接到显示区域。 第二单线的第一端连接到驱动器,第二单线的第二端连接到显示区。 第一单层布线的金属层与第二单层布线的金属层不同。
    • 3. 发明申请
    • ASYMMETRY THIN-FILM TRANSISTOR
    • 不对称薄膜晶体管
    • US20070023835A1
    • 2007-02-01
    • US11470251
    • 2006-09-05
    • Kun-Hong Chen
    • Kun-Hong Chen
    • H01L27/12
    • H01L29/66742H01L29/78666
    • An asymmetry thin-film transistor includes a substrate, a semiconductor layer positioned on the substrate, and a gate positioned on the substrate. The semiconductor layer has a channel region, a single lightly doped region and a first heavily doped region positioned at a side of the channel region, and a second heavily doped region positioned at the other side of the channel region. The semiconductor layer has a central line extending through the semiconductor layer and the substrate, the first heavily doped region and the second heavily doped region have equal lengths and are symmetric with respect to the central line of the semiconductor layer, and the gate is asymmetric with respect to the central line of the semiconductor layer. There is no lightly doped region in between the channel region and the second heavily doped region.
    • 不对称薄膜晶体管包括衬底,位于衬底上的半导体层和位于衬底上的栅极。 半导体层具有沟道区,单个轻掺杂区和位于沟道区一侧的第一重掺杂区,以及位于沟道区另一侧的第二重掺杂区。 半导体层具有延伸穿过半导体层和衬底的中心线,第一重掺杂区域和第二重掺杂区域具有相等的长度并且相对于半导体层的中心线对称,并且栅极是不对称的 相对于半导体层的中心线。 在沟道区和第二重掺杂区之间不存在轻掺杂区。
    • 4. 发明授权
    • Asymmetry thin-film transistor
    • 不对称薄膜晶体管
    • US07132685B2
    • 2006-11-07
    • US10463406
    • 2003-06-18
    • Kun-Hong Chen
    • Kun-Hong Chen
    • H01L29/04
    • H01L29/66742H01L29/78666
    • An asymmetry thin-film transistor includes a substrate, a semiconductor layer and a gate positioned on the substrate. The semiconductor layer includes a first lightly doped region and a first heavily doped region adjacent to a first gate side, and a second lightly doped region together with a second heavily doped region adjacent to a second gate side. A first junction is between the first lightly doped region and the first heavily doped region. A second junction is between the second lightly doped region and the second heavily doped region. A distance between the first junction and the first gate side is unequal to a distance between the second junction and the second gate side.
    • 不对称薄膜晶体管包括衬底,半导体层和位于衬底上的栅极。 半导体层包括与第一栅极侧相邻的第一轻掺杂区域和第一重掺杂区域以及与第二栅极侧邻近的第二重掺杂区域的第二轻掺杂区域。 第一结点在第一轻掺杂区和第一重掺杂区之间。 第二结点在第二轻掺杂区域和第二重掺杂区域之间。 第一结和第一栅极侧之间的距离不等于第二结和第二栅极侧之间的距离。
    • 7. 发明授权
    • Polysilicon thin film transistor and method of forming the same
    • 多晶硅薄膜晶体管及其形成方法
    • US06960809B2
    • 2005-11-01
    • US10907243
    • 2005-03-25
    • Kun-Hong ChenChinwei Hu
    • Kun-Hong ChenChinwei Hu
    • H01L21/336H01L29/786
    • H01L29/66757H01L29/78621H01L29/78675
    • A polysilicon thin film transistor and a method of forming the same is provided. A poly-island layer is formed over a substrate. A gate insulation layer is formed over the poly-island layer. A gate is formed over the gate insulation layer. Using the gate as a mask, an ion implantation of the poly-island layer is carried out to form a source/drain region in the poly-island layer outside the channel region. An oxide layer and a silicon nitride layer, together serving as an inter-layer dielectric layer, are sequentially formed over the substrate. Thickness of the oxide layer is thicker than or the same as (thickness of the nitride layer multiplied by 9000 Å)1/2 and maximum thickness of the nitride layer is smaller than 1000 Å.
    • 提供了多晶硅薄膜晶体管及其形成方法。 在基板上形成多岛层。 在多岛层上形成栅极绝缘层。 栅极形成在栅极绝缘层上。 使用栅极作为掩模,进行多岛层的离子注入,以在沟道区域外的多岛层中形成源极/漏极区域。 一起作为层间电介质层的氧化物层和氮化硅层依次形成在基板上。 氧化物层的厚度比(氮化物层的厚度乘以9000)的厚度大于或相同,并且氮化物层的最大厚度小于1000埃。