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1. 发明授权

US06323560B1 Registration accuracy measurement mark, method of repairing defect of the mark, photomask having the mark, method of manufacturing the photo mask and method of exposure thereof 有权
标题翻译：注册精度测量标记，修理标记缺陷的方法，具有标记的光掩模，制造光掩模的方法及其曝光方法
公开(公告)号：US06323560B1
公开(公告)日：2001-11-27
申请号：US09492750
申请日：2000-01-27
申请人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
发明人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
IPC分类号： H01L2358
CPC分类号： G03F7/706 , G03F7/70633 , Y10T428/24802 , Y10T428/24917
摘要： The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.
摘要翻译：本发明包括形成在第一层中的第一半导体元件形成元件，通过与第一半导体元件形成元件相同的制造步骤形成的第一测量标记，形成在第一层之上的第二层中的第二半导体元件形成元件，以及在与第二半导体元件形成部件相同的制造步骤中形成的用于测量第一和第二半导体元件形成部件之间的配准精度的第二测量标记。第一测量标记具有在照射光时受到与第一半导体元件形成部件相同的像差影响的图案，并且第二测量标记具有受光照射时受到与第二半导体元件形成部件相同的像差影响的图案。因此，可以提供考虑到像差影响的配准精度测量标记。

2. 发明授权

US6068952A Registration accuracy measurement mark, method of repairing defect of the mark, photomask having the mark, method of manufacturing the photomask and method of exposure thereof 有权
标题翻译：注册精度测量标记，修理标记缺陷的方法，具有标记的光掩模，制造光掩模的方法及其曝光方法
公开(公告)号：US6068952A
公开(公告)日：2000-05-30
申请号：US231664
申请日：1999-01-15
申请人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
发明人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
IPC分类号： G03F1/36 , G03F1/42 , G03F7/20 , G03F9/00 , H01L21/027 , H05K1/02
CPC分类号： G03F7/706 , G03F7/70633 , Y10T428/24802 , Y10T428/24917
摘要： The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.
摘要翻译：本发明包括形成在第一层中的第一半导体元件形成元件，通过与第一半导体元件形成元件相同的制造步骤形成的第一测量标记，形成在第一层之上的第二层中的第二半导体元件形成元件，以及在与第二半导体元件形成部件相同的制造步骤中形成的用于测量第一和第二半导体元件形成部件之间的配准精度的第二测量标记。第一测量标记具有在照射光时受到与第一半导体元件形成部件相同的像差影响的图案，并且第二测量标记具有受光照射时受到与第二半导体元件形成部件相同的像差影响的图案。因此，可以提供考虑到像差影响的配准精度测量标记。

3. 发明授权

US08043772B2 Manufacturing method and manufacturing system of semiconductor device 有权
标题翻译：半导体器件的制造方法和制造系统
公开(公告)号：US08043772B2
公开(公告)日：2011-10-25
申请号：US12466695
申请日：2009-05-15
申请人： Toshiharu Miwa , Junko Konishi , Toshihide Kawachi , Shigenori Yamashita , Takeshi Tashiro , Hidekimi Fudo
发明人： Toshiharu Miwa , Junko Konishi , Toshihide Kawachi , Shigenori Yamashita , Takeshi Tashiro , Hidekimi Fudo
IPC分类号： G03F9/00
CPC分类号： G03F7/70641 , G03F7/70625
摘要： In an exposure process forming a predetermined circuit pattern of a semiconductor device on a wafer, a resist dimension of the resist pattern formed on a wafer and a focus position in the exposure process at a past time are measured. A resist dimension and a focus position of a wafer to which the exposure process is secondly performed are estimated by using measurement results of the measured resist dimension and focus position, and a focus offset value is calculated by using estimated values of the estimated resist dimension and focus position. Then, an exposure dose is calculated with considering this focus offset value, and a resist pattern is formed on the wafer to which the exposure process is performed by using the calculated exposure dose and focus offset value.
摘要翻译：在形成晶片上的半导体器件的预定电路图形的曝光工艺中，测量在过去时刻在曝光处理中形成在晶片上的抗蚀剂图案的抗蚀剂尺寸和聚焦位置。通过使用被测量的抗蚀剂尺寸和聚焦位置的测量结果来估计第二次进行曝光处理的晶片的抗蚀剂尺寸和聚焦位置，并且通过使用估计的抗蚀剂尺寸的估计值来计算聚焦偏移值，焦点位置。然后，考虑该聚焦偏移值计算曝光剂量，并且通过使用计算出的曝光剂量和聚焦偏移值，在进行了曝光处理的晶片上形成抗蚀剂图案。

4. 发明授权

US5674647A Phase shift mask and manufacturing method thereof and exposure method using phase shift mask 失效
标题翻译：相移掩模及其制造方法以及使用相移掩模的曝光方法
公开(公告)号：US5674647A
公开(公告)日：1997-10-07
申请号：US547520
申请日：1995-10-24
申请人： Akihiko Isao , Ryoichi Kobayashi , Nobuyuki Yoshioka , Yaichiro Watakabe , Junji Miyazaki , Kouichiro Narimatsu , Shigenori Yamashita
发明人： Akihiko Isao , Ryoichi Kobayashi , Nobuyuki Yoshioka , Yaichiro Watakabe , Junji Miyazaki , Kouichiro Narimatsu , Shigenori Yamashita
IPC分类号： G03F1/00 , G03F1/26 , G03F1/32 , G03F1/38 , G03F1/54 , G03F1/80 , G03F9/00
CPC分类号： G03F1/32 , G03F1/26 , G03F1/38 , G03F1/54 , G03F1/80
摘要： A second light transmit portion of a phase shift mask is formed of a molybdenum silicide nitride oxide, or a molybdenum silicide oxide, or a chromium nitride oxide, or a chromium oxide, or a chromium carbide nitride oxide film converting a phase of transmitted exposure light by 180.degree. and having the transmittance of at least 2% and less than 5%. In the manufacturing method of the second light transmit portion, a molybdenum silicide nitride oxide film, or a molybdenum silicide oxide film, or a chromium nitride oxide film, or a chromium oxide film, or a carbide nitride oxide film is formed by a sputtering method. Consequently, with a conventional sputtering apparatus, the second light transmit portion can be formed, and additionally, etching process of the phase shifter portion is required only once, so that probabilities of defects and errors in the manufacturing process can be decreased.
摘要翻译：相移掩模的第二光透射部分由硅化钼化硅氧化物或硅化钼氧化物或氧化铬或氧化铬或碳化铬氮化物氧化物膜形成，其转换透射曝光光的相位 180°，透光率至少为2％且小于5％。在第二光透射部分的制造方法中，通过溅射法形成硅化钼硅化物氧化物膜或硅化钼氧化物膜，或氮氧化铬膜或氧化铬膜，或碳化氮化物氮化物膜。因此，利用传统的溅射装置，可以形成第二光透射部分，另外，仅需要一次移相器部分的蚀刻处理，从而可以减少制造过程中的缺陷概率和误差。

5. 发明授权

US06617080B1 Photomask, semiconductor device, and method for exposing through photomask 失效
标题翻译：光掩模，半导体器件和通过光掩模曝光的方法
公开(公告)号：US06617080B1
公开(公告)日：2003-09-09
申请号：US09563953
申请日：2000-05-02
申请人： Toshihide Kawachi , Takuya Matsushita , Shigenori Yamashita , Yuki Miyamoto , Atsushi Ueno , Shinroku Maejima
发明人： Toshihide Kawachi , Takuya Matsushita , Shigenori Yamashita , Yuki Miyamoto , Atsushi Ueno , Shinroku Maejima
IPC分类号： G03F900
CPC分类号： G03F7/70633
摘要： The present invention provides a photomask, a semiconductor device, and a method for exposing through the photomask. The photomask comprises a photomask substrate, and an on-mask circuit area including an on-mask circuit pattern and an on-mask test mark area including an on-mask test pattern, both formed on the surface of the substrate, wherein the photomask substrate further includes an on-mask photolithography screening mark area including an on-mask comparison pattern and an on-mask screening pattern, the on-mask comparison pattern has substantially the same configuration as at least a part of the on-mask circuit pattern, and the on-mask screening pattern has substantially the same configuration as at least a part of the on-mask test pattern. The present invention allows it to measure the actual displacement generated from an overlaying (i.e. alignment) process for the purpose of eliminating of an the overlay displacement which can take place in a photolithography process.
摘要翻译：本发明提供了一种光掩模，半导体器件和用于曝光光掩模的方法。光掩模包括光掩模基板和包括掩模电路图案的掩模电路区域和包括掩模测试图案的掩模测试标记区域，二者都形成在基板的表面上，其中光掩模基板进一步包括包括掩膜比较图案和掩模屏蔽图案的掩模光刻掩模标记区域，掩模比较图案具有与至少一部分屏蔽电路图案基本相同的配置，以及掩模掩模图案具有与掩模测试图案的至少一部分基本相同的构造。本发明允许它测量从重叠（即对准）过程产生的实际位移，以消除可能在光刻工艺中发生的覆盖位移。

6. 发明授权

US5830607A Phase shift mask and manufacturing method thereof and exposure method using phase shift mask 失效
标题翻译：相移掩模及其制造方法以及使用相移掩模的曝光方法
公开(公告)号：US5830607A
公开(公告)日：1998-11-03
申请号：US864005
申请日：1997-05-27
申请人： Akihiko Isao , Ryoichi Kobayashi , Nobuyuki Yoshioka , Yaichiro Watakabe , Junji Miyazaki , Kouichiro Narimatsu , Shigenori Yamashita
发明人： Akihiko Isao , Ryoichi Kobayashi , Nobuyuki Yoshioka , Yaichiro Watakabe , Junji Miyazaki , Kouichiro Narimatsu , Shigenori Yamashita
IPC分类号： G03F1/00 , G03F1/26 , G03F1/32 , G03F1/38 , G03F1/54 , G03F1/80 , G03F9/00
CPC分类号： G03F1/32 , G03F1/26 , G03F1/38 , G03F1/54 , G03F1/80
摘要： A second light transmit portion of a phase shift mask is formed of a molybdenum silicide nitride oxide, or a molybdenum silicide oxide, or a chromium nitride oxide, or a chromium oxide, or a chromium carbide nitride oxide film converting a phase of transmitted exposure light by 180.degree. and having the transmittance of at least 2% and less than 5%. In the manufacturing method of the second light transmit portion, a molybdenum silicide nitride oxide film, or a molybdenum silicide oxide film, or a chromium nitride oxide film, or a chromium oxide film, or a carbide nitride oxide film is formed by a sputtering method. Consequently, with a conventional sputtering apparatus, the second light transmit portion can be formed, and additionally, etching process of the phase shifter portion is required only once, so that probabilities of defects and errors in the manufacturing process can be decreased.
摘要翻译：相移掩模的第二光透射部分由硅化钼化硅氧化物或硅化钼氧化物或氧化铬或氧化铬或碳化铬氮化物氧化物膜形成，其转换透射曝光光的相位 180°，透光率至少为2％且小于5％。在第二光透射部分的制造方法中，通过溅射法形成硅化钼硅化物氧化物膜或硅化钼氧化物膜，或氮氧化铬膜或氧化铬膜，或碳化氮化物氮化物膜。因此，利用传统的溅射装置，可以形成第二光透射部分，另外，仅需要一次移相器部分的蚀刻处理，从而可以减少制造过程中的缺陷概率和误差。

7. 发明申请

US20090286174A1 MANUFACTURING METHOD AND MANUFACTURING SYSTEM OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的制造方法和制造系统
公开(公告)号：US20090286174A1
公开(公告)日：2009-11-19
申请号：US12466695
申请日：2009-05-15
申请人： Toshiharu MIWA , Junko KONISHI , Toshihide KAWACHI , Shigenori YAMASHITA , Takeshi TASHIRO , Hidekimi FUDO
发明人： Toshiharu MIWA , Junko KONISHI , Toshihide KAWACHI , Shigenori YAMASHITA , Takeshi TASHIRO , Hidekimi FUDO
IPC分类号： G03F7/20 , G06F19/00
CPC分类号： G03F7/70641 , G03F7/70625
摘要： In an exposure process forming a predetermined circuit pattern of a semiconductor device on a wafer, a resist dimension of the resist pattern formed on a wafer and a focus position in the exposure process at past time are measured, a resist dimension and a focus position of a wafer to which the exposure process is secondly performed are estimated by using measurement results of these measured resist dimension and focus position, and a focus offset value is calculated by using estimated values of these estimated resist dimension and focus position, and then, an exposure dose is calculated as considering this focus offset value, and a resist pattern is formed on the wafer to which the exposure process is performed by using these calculated exposure dose and focus offset value.
摘要翻译：在形成晶片上的半导体器件的预定电路图案的曝光工艺中，测量在过去时间在曝光处理中形成在晶片上的抗蚀剂图案的抗蚀剂尺寸和聚焦位置，抗蚀剂尺寸和聚焦位置通过使用这些测量的抗蚀剂尺寸和聚焦位置的测量结果来估计其次要进行曝光处理的晶片，并且通过使用这些估计的抗蚀剂尺寸和聚焦位置的估计值来计算聚焦偏移值，然后曝光考虑该聚焦偏移值计算剂量，并且通过使用这些计算的曝光剂量和聚焦偏移值，在进行曝光处理的晶片上形成抗蚀剂图案。

8. 发明授权

US5892291A Registration accuracy measurement mark 失效
标题翻译：注册精度测量标记
公开(公告)号：US5892291A
公开(公告)日：1999-04-06
申请号：US670313
申请日：1996-06-27
申请人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
发明人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
IPC分类号： G03F1/36 , G03F1/42 , G03F7/20 , G03F9/00 , H01L21/027 , H05K1/02 , H01L23/544
CPC分类号： G03F7/706 , G03F7/70633 , Y10T428/24802 , Y10T428/24917
摘要： The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.
摘要翻译：本发明包括形成在第一层中的第一半导体元件形成元件，通过与第一半导体元件形成元件相同的制造步骤形成的第一测量标记，形成在第一层之上的第二层中的第二半导体元件形成元件，以及在与第二半导体元件形成部件相同的制造步骤中形成的用于测量第一和第二半导体元件形成部件之间的配准精度的第二测量标记。第一测量标记具有在照射光时受到与第一半导体元件形成部件相同的像差影响的图案，并且第二测量标记具有受光照射时受到与第二半导体元件形成部件相同的像差影响的图案。因此，可以提供考虑到像差影响的配准精度测量标记。

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