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1. 发明授权

US07141484B2 Electrostatic discharge protection circuit of non-gated diode and fabrication method thereof 有权
公开(公告)号：US07141484B2
公开(公告)日：2006-11-28
申请号：US10702372
申请日：2003-11-05
申请人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
发明人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
IPC分类号： H01L21/76
CPC分类号： H01L27/08 , H01L21/84 , H01L27/0255 , H01L27/0814 , H01L27/1203
摘要： A non-gated diode structure of a silicon-on-insulator, having a silicon-on-insulator substrate, a pair of isolating structures, a first type doped region and a second type doped region. The silicon-on-insulation substrate has a stack of a substrate, an insulation layer and a silicon layer. The isolating structures are located in the silicon layer to define a well region. The first and second type doped regions are located in the well and are adjacent to the isolating structures. Such a non-gated diode structure can be applied to an electrostatic discharge protection circuit to increase the electrostatic discharge protection voltage or current. In addition, a fabrication method of the non-gated diode is also introduced. This non-gated diode can be also fabricated in the general bulk CMOS process, and used in the on-chip ESD protection circuits.

2. 发明授权

US06933573B2 Electrostatic discharge protection circuit of non-gated diode and fabrication method thereof 有权
标题翻译：非门控二极管的静电放电保护电路及其制造方法
公开(公告)号：US06933573B2
公开(公告)日：2005-08-23
申请号：US10060743
申请日：2002-01-30
申请人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
发明人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
IPC分类号： H01L21/84 , H01L27/02 , H01L27/08 , H01L27/12 , H01L23/62
CPC分类号： H01L27/08 , H01L21/84 , H01L27/0255 , H01L27/0814 , H01L27/1203
摘要： A non-gated diode structure of a silicon-on-insulator, having a silicon-on-insulator substrate, a pair of isolating structures, a first type doped region and a second type doped region. The silicon-on-insulation substrate has a stack of a substrate, an insulation layer and a silicon layer. The isolating structures are located in the silicon layer to define a well region. The first and second type doped regions are located in the well and are adjacent to the isolating structures. Such a non-gated diode structure can be applied to an electrostatic discharge protection circuit to increase the electrostatic discharge protection voltage or current. In addition, a fabrication method of the non-gated diode is also introduced. This non-gated diode can be also fabricated in the general bulk CMOS process, and used in the on-chip ESD protection circuits.
摘要翻译：绝缘体上硅的非门控二极管结构，其具有绝缘体上硅衬底，一对隔离结构，第一类型掺杂区和第二类型掺杂区。硅绝缘基板具有基板，绝缘层和硅层的堆叠。隔离结构位于硅层中以限定阱区。第一和第二类型掺杂区域位于阱中并且与隔离结构相邻。这种非门控二极管结构可以应用于静电放电保护电路以增加静电放电保护电压或电流。此外，还介绍了非门控二极管的制造方法。这种非门控二极管也可以在通常的体CMOS工艺中制造，并且用于片上ESD保护电路。

3. 发明授权

US06861680B2 Silicon-on-insulator diodes and ESD protection circuits 有权
标题翻译：绝缘体上硅二极管和ESD保护电路
公开(公告)号：US06861680B2
公开(公告)日：2005-03-01
申请号：US10315158
申请日：2002-12-10
申请人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
发明人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
IPC分类号： H01L27/02 , H01L29/739 , H01L29/861 , H01L31/072
CPC分类号： H01L29/4991 , H01L27/0251 , H01L29/4983 , H01L29/7391 , H01L29/861
摘要： A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits. The proposed gated diode and non-gated diode can be fully process-compatiable to general partially-depleted or fully-depleted silicon-on-insulator CMOS processes.
摘要翻译：提供了绝缘体上硅（SOI）门控二极管和非门控结二极管。 SOI栅控二极管在栅极下方的中间区域具有PN结，其具有比正常二极管更多的结面积。 SOI非门控结二极管在其中间区域具有PN结，并且还具有比正常二极管更多的结面积。本发明的SOI二极管由于低功率密度和加热而提供了针对电应力（EOS）/静电放电（ESD）的保护等级，以提供比正常功率密度更多的接合面积。包括主二极管，第一多个二极管和第二多个二极管的I / O ESD保护电路全部由本SOI SOI形成，当存在ESD事件时，可以有效地放电。并且包括更多初级二极管的ESD保护电路可以有效地减小寄生输入电容，使得它们可以用在RF电路或HF电路中。所提出的门控二极管和非门控二极管可以完全兼容于一般部分耗尽或完全耗尽的绝缘体上硅CMOS工艺。

4. 发明授权

US06728086B2 Power-rail electrostatic discharge protection circuit with a dual trigger design 有权
标题翻译：电源轨静电放电保护电路采用双触发设计
公开(公告)号：US06728086B2
公开(公告)日：2004-04-27
申请号：US10050018
申请日：2002-01-15
申请人： Kei-Kang Hung , Chien-Hui Chuang
发明人： Kei-Kang Hung , Chien-Hui Chuang
IPC分类号： H02H900
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A power-rail ESD (electrostatic discharge) protection circuit with a dual trigger design is proposed, which is coupled between a first power line and a second power line connected to an IC device for protecting the IC device against ESD on the first power line and the second power line. The proposed power-rail ESD protection circuit comprises a control circuit and at least one MOS device. The control circuit is coupled between the first power line and the second power line, and which is capable of, in the event of ESD in the first power line and the second power line, being triggered by the ESD to output a substrate-triggering voltage and a gate-driving voltage to the MOS device, causing the MOS device to bypass the ESD current from the first power line and the second power line. The circuit configuration of the proposed power-rail ESD protection circuit can help reduce the junction breakdown voltage in a MOS device and increase in ESD robustness.
摘要翻译：提出了具有双触发设计的电力轨道ESD（静电放电）保护电路，其耦合在连接到IC装置的第一电力线和第二电力线之间，用于保护IC装置免受第一电力线上的ESD，第二条电力线。所提出的电源轨ESD保护电路包括控制电路和至少一个MOS器件。控制电路耦合在第一电力线和第二电力线之间，并且其能够在第一电力线和第二电力线中的ESD的情况下被ESD触发以输出基板触发电压以及向MOS器件施加栅极驱动电压，使MOS器件从第一电力线和第二电力线旁路ESD电流。所提出的电力轨道ESD保护电路的电路配置有助于降低MOS器件中的结击穿电压，增加ESD稳定性。

5. 发明授权

US06653670B2 Silicon-on-insulator diodes and ESD protection circuits 有权
公开(公告)号：US06653670B2
公开(公告)日：2003-11-25
申请号：US10315157
申请日：2002-12-10
申请人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
发明人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
IPC分类号： H01L3072
CPC分类号： H01L29/4991 , H01L27/0251 , H01L29/4983 , H01L29/7391 , H01L29/861
摘要： A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and then also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits. The proposed gated diode and non-gated diode can be fully process-compatiable to general partially-depleted or fully-depleted silicon-on-insulator CMOS processes.

6. 发明授权

US06649944B2 Silicon-on-insulator diodes and ESD protection circuits 有权
标题翻译：绝缘体上硅二极管和ESD保护电路
公开(公告)号：US06649944B2
公开(公告)日：2003-11-18
申请号：US10315161
申请日：2002-12-10
申请人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
发明人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
IPC分类号： H01L31072
CPC分类号： H01L29/4991 , H01L27/0251 , H01L29/4983 , H01L29/7391 , H01L29/861
摘要： A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, thus providing more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and thus also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits. The proposed gated diode and non-gated diode can be fully process-compatible to general partially-depleted or fully-depleted silicon-on-insulator CMOS processes.
摘要翻译：提供了绝缘体上硅（SOI）门控二极管和非门控结二极管。 SOI门控二极管在栅极下方的中间区域具有PN结，因此提供比正常二极管更多的接合面积。 SOI非门控结二极管在其中间区域具有PN结，因此也具有比正常二极管更多的结面积。本发明的SOI二极管由于低功率密度和加热而提供了针对电应力（EOS）/静电放电（ESD）的保护等级，以提供比正常功率密度更多的接合面积。包括主二极管，第一多个二极管和第二多个二极管的I / O ESD保护电路全部由本SOI SOI形成，当存在ESD事件时，可以有效地放电。而且，包含更多初级二极管的ESD保护电路可以有效地降低寄生输入电容，从而可以将它们用于RF电路或HF电路。所提出的门控二极管和非门控二极管可以完全兼容于一般部分耗尽或完全耗尽的绝缘体上硅CMOS工艺。

7. 发明授权

US06639772B2 Electrostatic discharge protection circuit for protecting input and output buffer 失效
标题翻译：用于保护输入和输出缓冲器的静电放电保护电路
公开(公告)号：US06639772B2
公开(公告)日：2003-10-28
申请号：US10041237
申请日：2002-01-07
申请人： Chien-Hui Chuang , Kei-Kang Hung
发明人： Chien-Hui Chuang , Kei-Kang Hung
IPC分类号： H02H300
CPC分类号： H01L27/0277
摘要： An electrostatic discharge (ESD) protection circuit for protecting input and output buffers. The ESD protection circuit is driven by a first voltage source and a second voltage source and coupled to a bonding pad. The ESD protection circuit has a first resistor, a first PMOS transistor, a first NMOS transistor, a first diode series, a second PMOS transistor, a second resistor, a third PMOS transistor, a second NMOS transistor, a second diode series and a third NMOS transistor. The electrical devices combine to form different types of ESD protection circuits, each capable of protecting the input buffer or output buffer against the damaging effects of an electrostatic discharge.
摘要翻译：一种用于保护输入和输出缓冲器的静电放电（ESD）保护电路。 ESD保护电路由第一电压源和第二电压源驱动并耦合到接合焊盘。 ESD保护电路具有第一电阻器，第一PMOS晶体管，第一NMOS晶体管，第一二极管系列，第二PMOS晶体管，第二电阻器，第三PMOS晶体管，第二NMOS晶体管，第二二极管串联和第三 NMOS晶体管。电气设备组合形成不同类型的ESD保护电路，每个ESD保护电路能够保护输入缓冲器或输出缓冲器免受静电放电的破坏作用。

8. 发明授权

US06521952B1 Method of forming a silicon controlled rectifier devices in SOI CMOS process for on-chip ESD protection 有权
标题翻译：在SOI CMOS工艺中形成用于片上ESD保护的可控硅整流器件的方法
公开(公告)号：US06521952B1
公开(公告)日：2003-02-18
申请号：US09682811
申请日：2001-10-22
申请人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
发明人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
IPC分类号： H01L2362
CPC分类号： H01L27/0262
摘要： An NMOS-trigger silicon controlled rectifier in silicon-on-insulator (SOI-NSCR) SOI-NSCR includes a P-type well and an N-type well. A first P+ doping region and a first N+ doping region are in the N-type well and form the anode of the SOI-NSCR. A second P+ doping region and a second N+ doping region are in the P-type well and form the cathode of the SOI-NSCR. The first P+ doping region, the N-type well, the P-type well and the second N+ doping region form a lateral SCR. A third N+ doping region is across the N-type well and the P-type well. A gate is in the P-type well, and the third N+ doping region, the gate and the second N+ doping region form an NMOS. A dummy gate is in the N-type well for isolating the first P+ doping region and the third N+ doping region. When a voltage is applied to the gate of the NMOS that turns on the NMOS, a forward bias is created from the N-type well to the P-type well that turns on the SOI-NSCR. When a voltage is applied to the third N+ doping region, a trigger current is generated that causes the lateral SCR to enter a latch state and so the SOI-NSCR is quickly turned on. Utilizing similar and related designs, the present invention discloses a PMOS-trigger silicon controlled rectifier in silicon-on-insulator (SOI-PSCR), and ESD protection circuitry utilizing the SOI-NSCR and the SOI-PSCR.
摘要翻译：绝缘体上硅（SOI-NSCR）SOI-NSCR中的NMOS触发可控硅整流器包括P型阱和N型阱。第一P +掺杂区和第一N +掺杂区位于N型阱中并形成SOI-NSCR的阳极。第二P +掺杂区和第二N +掺杂区位于P型阱中并形成SOI-NSCR的阴极。第一P +掺杂区，N型阱，P型阱和第二N +掺杂区形成横向SCR。第三个N +掺杂区跨越N型阱和P型阱。栅极位于P型阱中，第三N +掺杂区，栅极和第二N +掺杂区形成NMOS。 N型阱中的伪栅极用于隔离第一P +掺杂区和第三N +掺杂区。当电压施加到导通NMOS的NMOS的栅极时，产生从N型阱到引导SOI-NSCR的P型阱的正向偏压。当向第三N +掺杂区域施加电压时，产生触发电流，使得横向SCR进入锁存状态，因此SOI-NSCR快速导通。利用相似和相关的设计，本发明公开了一种在绝缘体上硅（SOI-PSCR）中的PMOS触发可控硅整流器，以及利用SOI-NSCR和SOI-PSCR的ESD保护电路。

9. 发明授权

US07777277B2 Dual triggered silicon controlled rectifier 有权
标题翻译：双触发可控硅整流器
公开(公告)号：US07777277B2
公开(公告)日：2010-08-17
申请号：US12146456
申请日：2008-06-26
申请人： Kei-Kang Hung
发明人： Kei-Kang Hung
IPC分类号： H01L23/62
CPC分类号： H01L29/7436 , H01L29/7455
摘要： The present invention provides a dual triggered silicon controlled rectifier (DTSCR) including: a semiconductor substrate, an N-well, a P-well, a first N+ diffusion region and a first P+ diffusion region, a second N+ diffusion region and a second P+ diffusion region; a third P+ diffusion region, positioned in one side of the DTSCR and across the N-well and the P-well; a third N+ diffusion region, positioned in another side of the DTSCR and across the N-well and the P-well; a first gate, positioned above the N-well between the second and the third P+ diffusion regions, utilized as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the P-well between the first and the third N+ diffusion regions, utilized as an N-type trigger node to receive a second trigger current or a second trigger voltage.
摘要翻译：本发明提供一种双触发可控硅整流器（DTSCR），包括：半导体衬底，N阱，P阱，第一N +扩散区和第一P +扩散区，第二N +扩散区和第二P + 扩散区; 位于DTSCR的一侧并穿过N阱和P阱的第三P +扩散区; 位于DTSCR的另一侧并跨过N阱和P阱的第三N +扩散区; 位于第二和第三P +扩散区之间的N阱之上的第一栅极，用作P型触发器节点以接收第一触发电流或第一触发电压; 以及位于第一和第三N +扩散区之间的P阱的上方的第二栅极，用作N型触发器节点以接收第二触发电流或第二触发电压。

10. 发明申请

US20090189183A1 DUAL TRIGGERED SILICON CONTROLLED RECTIFIER 有权
标题翻译：双触发硅控制整流器
公开(公告)号：US20090189183A1
公开(公告)日：2009-07-30
申请号：US12146456
申请日：2008-06-26
申请人： Kei-Kang Hung
发明人： Kei-Kang Hung
IPC分类号： H01L29/00
CPC分类号： H01L29/7436 , H01L29/7455
摘要： The present invention provides a dual triggered silicon controlled rectifier (DTSCR) including: a semiconductor substrate, an N-well, a P-well, a first N+ diffusion region and a first P+ diffusion region, a second N+ diffusion region and a second P+ diffusion region; a third P+ diffusion region, positioned in one side of the DTSCR and across the N-well and the P-well; a third N+ diffusion region, positioned in another side of the DTSCR and across the N-well and the P-well; a first gate, positioned above the N-well between the second and the third P+ diffusion regions, utilized as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the P-well between the first and the third N+ diffusion regions, utilized as an N-type trigger node to receive a second trigger current or a second trigger voltage.
摘要翻译：本发明提供一种双触发可控硅整流器（DTSCR），包括：半导体衬底，N阱，P阱，第一N +扩散区和第一P +扩散区，第二N +扩散区和第二P + 扩散区; 位于DTSCR的一侧并穿过N阱和P阱的第三P +扩散区; 位于DTSCR的另一侧并跨过N阱和P阱的第三N +扩散区; 位于第二和第三P +扩散区之间的N阱之上的第一栅极，用作P型触发器节点以接收第一触发电流或第一触发电压; 以及位于第一和第三N +扩散区之间的P阱的上方的第二栅极，用作N型触发器节点以接收第二触发电流或第二触发电压。

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