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1. 发明授权

US08089127B2 Dual triggered silicon controlled rectifier 有权
标题翻译：双触发可控硅整流器
公开(公告)号：US08089127B2
公开(公告)日：2012-01-03
申请号：US12796672
申请日：2010-06-09
申请人： Kei-Kang Hung
发明人： Kei-Kang Hung
IPC分类号： H01L23/62
CPC分类号： H01L29/7436 , H01L29/7455
摘要： A dual triggered silicon controlled rectifier (DTSCR) comprises: a semiconductor substrate; an N-well, a P-well, a first N+ diffusion region and a first P+ diffusion region, a second N+ diffusion region and a second P+ diffusion region, a third P+ diffusion region, positioned in one side of the DTSCR and across the N-well and the P-well; a third N+ diffusion region, positioned in another side of the DTSCR and across the N-well and the P-well; a first gate, positioned above the N-well between the second P+ diffusion region and the third P+ diffusion region, for use as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the P-well between the first N+ diffusion region and the third N+ diffusion region, for use as an N-type trigger node to receive a second trigger current or a second trigger voltage.
摘要翻译：双触发可控硅整流器（DTSCR）包括：半导体衬底; N阱，P阱，第一N +扩散区和第一P +扩散区，第二N +扩散区和第二P +扩散区，第三P +扩散区，位于DTSCR的一侧并横跨 N井和P井; 位于DTSCR的另一侧并跨过N阱和P阱的第三个N +扩散区; 位于第二P +扩散区和第三P +扩散区之间的N阱之上的第一栅极，用作P型触发节点以接收第一触发电流或第一触发电压; 以及位于第一N +扩散区和第三N +扩散区之间的P阱之上的第二栅极，用作N型触发节点以接收第二触发电流或第二触发电压。

2. 发明授权

US06768619B2 Low-voltage-triggered SOI-SCR device and associated ESD protection circuit 有权
标题翻译：低电压触发SOI-SCR器件和相关的ESD保护电路
公开(公告)号：US06768619B2
公开(公告)日：2004-07-27
申请号：US10367502
申请日：2003-02-13
申请人： Ming-Dou Ker , Kei-Kang Hung , Shao-Chang Huang
发明人： Ming-Dou Ker , Kei-Kang Hung , Shao-Chang Huang
IPC分类号： H02H900
CPC分类号： H01L27/0262
摘要： A silicon-on-insulator low-voltage-triggered silicon controlled rectifier device structure that is built upon a substrate and an insulation layer. The insulation layer has a plurality of isolation structures thereon to define a device region. A first-type well and a second-type well are formed over the insulation layer. The first-type and second-type wells are connected. A first gate and a second gate are formed over the first-type well and the second-type well, respectively. The first-type well further includes a first second-type doped region and a first first-type doped region formed between the first second-type doped region and the isolation structure adjacent to the first second-type doped region. The first second-type doped region and the first first-type doped region together form a cathode of the SOI-SCR device. A second first-type doped region is formed within the first-type well between the first second-type doped region and the first gate structure adjacent to the first second-type doped region. A third first-type doped region is formed within the first and the second-type well around their junction between the first and second-type well. The second-type well further includes a second second-type doped region and a fourth first-type doped region within the second-type well between the second second-type doped region and the second gate adjacent to the second second-type doped region. The second second-type doped region and the fourth first-type doped region together form an anode of the SOI-SCR device.
摘要翻译：一种绝缘体上的绝缘体上的低电压触发的可控硅整流器件结构，其构造在衬底和绝缘层上。绝缘层在其上具有多个隔离结构以限定器件区域。在绝缘层上形成第一型阱和第二型阱。第一类和第二类型井连接。分别在第一型阱和第二型阱上形成第一栅极和第二栅极。第一类阱还包括形成在与第一第二类型掺杂区相邻的第一第二掺杂区和隔离结构之间的第一第二掺杂区和第一第一掺杂区。第一第二掺杂区域和第一第一掺杂区域一起形成SOI-SCR器件的阴极。在第一第二类型掺杂区域和与第一第二掺杂区域相邻的第一栅极结构之间的第一类型阱内形成第二第一类型掺杂区域。在第一和第二类型阱内围绕第一和第二类型阱的连接点形成第三第一类型掺杂区域。第二类阱还包括在第二第二类型掺杂区域和与第二第二类型掺杂区域相邻的第二栅极之间的第二类型阱内的第二第二类型掺杂区域和第四第一类型掺杂区域。第二二次掺杂区域和第四第一掺杂区域一起形成SOI-SCR器件的阳极。

3. 发明授权

US06690561B2 Effective gate-driven or gate-coupled ESD protection circuit 有权
标题翻译：有效的栅极驱动或栅极耦合ESD保护电路
公开(公告)号：US06690561B2
公开(公告)日：2004-02-10
申请号：US09990453
申请日：2001-11-20
申请人： Kei-Kang Hung , Chien-Hui Chuang , Hung-Yi Chang
发明人： Kei-Kang Hung , Chien-Hui Chuang , Hung-Yi Chang
IPC分类号： H02H322
CPC分类号： H02H9/046 , H02H3/006
摘要： An ESD protection circuit, arranged between a first and second potential terminals, has a RC branch, a voltage adjuster circuit, and an ESD discharge transistor. The RC branch includes a resistor and a capacitor series connected from the first to the second potential terminal. The voltage adjuster circuit has a plurality of inputs connected to the RC branch, and the first and second potential terminals, and an output connected to a gate of the ESD discharge transistor to adjust the gate voltage thereof for obtaining a uniform turn on and optimal ESD robustness. The voltage adjuster circuit mainly includes a plurality of transistors that enable to effectively adjust the gate voltage with respect to high level of ESD stress.
摘要翻译：布置在第一和第二电位端子之间的ESD保护电路具有RC分支，电压调节器电路和ESD放电晶体管。 RC分支包括从第一到第二电位端子连接的电阻器和电容器串联。电压调节器电路具有连接到RC分支以及第一和第二电位端子的多个输入端以及连接到ESD放电晶体管的栅极的输出端，以调整其栅极电压以获得均匀的导通和最佳的ESD 健壮性电压调节器电路主要包括多个晶体管，其能够相对于高水平的ESD应力有效地调节栅极电压。

4. 发明授权

US06671147B2 Double-triggered electrostatic discharge protection circuit 有权
公开(公告)号：US06671147B2
公开(公告)日：2003-12-30
申请号：US09872180
申请日：2001-06-01
申请人： Ming-Dou Ker , Kei-Kang Hung , Shao-Chang Huang
发明人： Ming-Dou Ker , Kei-Kang Hung , Shao-Chang Huang
IPC分类号： H02H900
CPC分类号： H01L27/0274 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A double-triggered electrostatic discharge (ESD) protection circuit for coupling with a first voltage source and a second voltage source. The circuit includes a diode series and a transistor. The diode series comprises a plurality of serially connected diodes with the cathode of one diode connected to the anode of a subsequent diode. The positive terminal of the first diode in the diode series connects with the first voltage source. The gate terminal of the transistor connects with the anode of the last diode in the diode series. The substrate of the transistor connects with the cathode of the last diode in the diode series. The source terminal and the drain terminal of the transistor connect with the first voltage source and the second voltage source, respectively. By using double-triggered design, the ESD clamp device can be quickly triggered on to bypass ESD current. Therefore, the ESD protection circuit has a better protection capability to protect the IC in deep-submicron CMOS technologies against ESD damage.

5. 发明授权

US07777277B2 Dual triggered silicon controlled rectifier 有权
标题翻译：双触发可控硅整流器
公开(公告)号：US07777277B2
公开(公告)日：2010-08-17
申请号：US12146456
申请日：2008-06-26
申请人： Kei-Kang Hung
发明人： Kei-Kang Hung
IPC分类号： H01L23/62
CPC分类号： H01L29/7436 , H01L29/7455
摘要： The present invention provides a dual triggered silicon controlled rectifier (DTSCR) including: a semiconductor substrate, an N-well, a P-well, a first N+ diffusion region and a first P+ diffusion region, a second N+ diffusion region and a second P+ diffusion region; a third P+ diffusion region, positioned in one side of the DTSCR and across the N-well and the P-well; a third N+ diffusion region, positioned in another side of the DTSCR and across the N-well and the P-well; a first gate, positioned above the N-well between the second and the third P+ diffusion regions, utilized as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the P-well between the first and the third N+ diffusion regions, utilized as an N-type trigger node to receive a second trigger current or a second trigger voltage.
摘要翻译：本发明提供一种双触发可控硅整流器（DTSCR），包括：半导体衬底，N阱，P阱，第一N +扩散区和第一P +扩散区，第二N +扩散区和第二P + 扩散区; 位于DTSCR的一侧并穿过N阱和P阱的第三P +扩散区; 位于DTSCR的另一侧并跨过N阱和P阱的第三N +扩散区; 位于第二和第三P +扩散区之间的N阱之上的第一栅极，用作P型触发器节点以接收第一触发电流或第一触发电压; 以及位于第一和第三N +扩散区之间的P阱的上方的第二栅极，用作N型触发器节点以接收第二触发电流或第二触发电压。

6. 发明申请

US20090189183A1 DUAL TRIGGERED SILICON CONTROLLED RECTIFIER 有权
标题翻译：双触发硅控制整流器
公开(公告)号：US20090189183A1
公开(公告)日：2009-07-30
申请号：US12146456
申请日：2008-06-26
申请人： Kei-Kang Hung
发明人： Kei-Kang Hung
IPC分类号： H01L29/00
CPC分类号： H01L29/7436 , H01L29/7455
摘要： The present invention provides a dual triggered silicon controlled rectifier (DTSCR) including: a semiconductor substrate, an N-well, a P-well, a first N+ diffusion region and a first P+ diffusion region, a second N+ diffusion region and a second P+ diffusion region; a third P+ diffusion region, positioned in one side of the DTSCR and across the N-well and the P-well; a third N+ diffusion region, positioned in another side of the DTSCR and across the N-well and the P-well; a first gate, positioned above the N-well between the second and the third P+ diffusion regions, utilized as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the P-well between the first and the third N+ diffusion regions, utilized as an N-type trigger node to receive a second trigger current or a second trigger voltage.
摘要翻译：本发明提供一种双触发可控硅整流器（DTSCR），包括：半导体衬底，N阱，P阱，第一N +扩散区和第一P +扩散区，第二N +扩散区和第二P + 扩散区; 位于DTSCR的一侧并穿过N阱和P阱的第三P +扩散区; 位于DTSCR的另一侧并跨过N阱和P阱的第三N +扩散区; 位于第二和第三P +扩散区之间的N阱之上的第一栅极，用作P型触发器节点以接收第一触发电流或第一触发电压; 以及位于第一和第三N +扩散区之间的P阱的上方的第二栅极，用作N型触发器节点以接收第二触发电流或第二触发电压。

7. 发明授权

US06750515B2 SCR devices in silicon-on-insulator CMOS process for on-chip ESD protection 有权
标题翻译：用于片上ESD保护的硅绝缘体CMOS工艺中的SCR器件
公开(公告)号：US06750515B2
公开(公告)日：2004-06-15
申请号：US10062714
申请日：2002-02-05
申请人： Ming-Dou Ker , Kei-Kang Hung , Chyh-Yih Chang
发明人： Ming-Dou Ker , Kei-Kang Hung , Chyh-Yih Chang
IPC分类号： H01L2776
CPC分类号： H01L27/0262 , H01L27/1203
摘要： A silicon-on-isolator CMOS integrated circuit device includes a semiconductor substrate, an isolation layer formed over the semiconductor substrate, an n-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer, and a p-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer and contiguous with the n-type MOS transistor, wherein the n-type MOS transistor and the p-type MOS transistor form a silicon controlled rectifier to provide electrostatic discharge protection.
摘要翻译：硅隔离器CMOS集成电路器件包括半导体衬底，形成在半导体衬底上的隔离层，具有形成在隔离层上的栅极，漏极区域和源极区域的n型MOS晶体管，以及 p型MOS晶体管，其具有形成在隔离层上并与n型MOS晶体管邻接的栅极，漏极区域和源极区域，其中n型MOS晶体管和p型MOS晶体管形成硅控制整流器提供静电放电保护。

8. 发明授权

US06639283B1 Semiconductor device with substrate-triggered ESD protection 有权
标题翻译：具有基板触发ESD保护的半导体器件
公开(公告)号：US06639283B1
公开(公告)日：2003-10-28
申请号：US10117147
申请日：2002-04-04
申请人： Kei-Kang Hung , Ming-Dou Ker
发明人： Kei-Kang Hung , Ming-Dou Ker
IPC分类号： H01L2362
CPC分类号： H01L27/0266
摘要： A semiconductor device with substrate-triggered ESD protection technique includes a guard ring, a first MOS transistor array, a second MOS transistor array and a substrate-triggered portion. The first MOS transistor array, the second MOS transistor array and the substrate-triggered portion are formed in a region surrounded by the guard ring, and the substrate-triggered portion is located between the first MOS transistor array and the second MOS transistor array. Therefore, when the ESD event occurs, the substrate-triggered portion can be used for biasing a base of at least one parasitic BJT in the first MOS transistor array and a base of at least one parasitic BJT in the second MOS transistor array to achieve uniform turn-on among the multiple fingers of MOS transistor array. By using this layout design, the MOS transistor array can have a high ESD robustness.
摘要翻译：具有基板触发ESD保护技术的半导体器件包括保护环，第一MOS晶体管阵列，第二MOS晶体管阵列和基板触发部分。第一MOS晶体管阵列，第二MOS晶体管阵列和基板触发部分形成在由保护环包围的区域中，并且基板触发部分位于第一MOS晶体管阵列和第二MOS晶体管阵列之间。因此，当ESD事件发生时，衬底触发部分可以用于偏置第一MOS晶体管阵列中的至少一个寄生BJT的基极和第二MOS晶体管阵列中的至少一个寄生BJT的基极以实现均匀 MOS晶体管阵列的多个指状物之间导通。通过使用这种布局设计，MOS晶体管阵列可以具有高ESD稳定性。

9. 发明申请

US20100244095A1 DUAL TRIGGERED SILICON CONTROLLED RECTIFIER 有权
标题翻译：双触发硅控制整流器
公开(公告)号：US20100244095A1
公开(公告)日：2010-09-30
申请号：US12796672
申请日：2010-06-09
申请人： Kei-Kang Hung
发明人： Kei-Kang Hung
IPC分类号： H01L29/73
CPC分类号： H01L29/7436 , H01L29/7455
摘要： A dual triggered silicon controlled rectifier (DTSCR) comprises: a semiconductor substrate; an N-well, a P-well, a first N+ diffusion region and a first P+ diffusion region, a second N+ diffusion region and a second P+ diffusion region, a third P+ diffusion region, positioned in one side of the DTSCR and across the N-well and the P-well; a third N+ diffusion region, positioned in another side of the DTSCR and across the N-well and the P-well; a first gate, positioned above the N-well between the second P+ diffusion region and the third P+ diffusion region, for use as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the P-well between the first N+ diffusion region and the third N+ diffusion region, for use as an N-type trigger node to receive a second trigger current or a second trigger voltage.
摘要翻译：双触发可控硅整流器（DTSCR）包括：半导体衬底; N阱，P阱，第一N +扩散区和第一P +扩散区，第二N +扩散区和第二P +扩散区，第三P +扩散区，位于DTSCR的一侧并横跨 N井和P井; 位于DTSCR的另一侧并跨过N阱和P阱的第三N +扩散区; 位于第二P +扩散区和第三P +扩散区之间的N阱之上的第一栅极，用作P型触发节点以接收第一触发电流或第一触发电压; 以及位于第一N +扩散区和第三N +扩散区之间的P阱之上的第二栅极，用作N型触发节点以接收第二触发电流或第二触发电压。

10. 发明授权

US06690557B2 CMOS whole chip low capacitance ESD protection circuit 失效
标题翻译： CMOS全片低电容ESD保护电路
公开(公告)号：US06690557B2
公开(公告)日：2004-02-10
申请号：US10004670
申请日：2001-12-04
申请人： Kei-Kang Hung , Chien-Hui Chuang
发明人： Kei-Kang Hung , Chien-Hui Chuang
IPC分类号： H02H322
CPC分类号： H01L27/0262
摘要： A low capacitance electrostatic discharge circuit (ESD) for a built-in CMOS chip capable of protecting an internal circuit within the chip. A first voltage source and a second voltage source are provided to the electrostatic protection circuit. The ESD circuit is coupled to a bonding pad and the internal circuit. The ESD protection circuit includes a first diode series, a second diode series, a first control circuit, a third diode series, a first silicon-controlled rectifier (SCR), a second control circuit, a fourth diode series and a second SCR. The ESD circuit utilizes the control circuits to initiate substrate triggering so that the triggered voltage of the SCR is lowered and holding voltage of the SCR during conduction in increased. Consequently, the entire chip is protected and input capacitance of the circuit is reduced.
摘要翻译：用于内置CMOS芯片的低电容静电放电电路（ESD），能够保护芯片内部的电路。第一电压源和第二电压源被提供给静电保护电路。 ESD电路耦合到接合焊盘和内部电路。 ESD保护电路包括第一二极管系列，第二二极管系列，第一控制电路，第三二极管系列，第一硅可控整流器（SCR），第二控制电路，第四二极管系列和第二SCR。 ESD电路利用控制电路来启动衬底触发，使得SCR的触发电压降低，并且在传导期间SCR的保持电压增加。因此，整个芯片被保护，电路的输入电容减小。

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