会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 7. 发明申请
    • DRIVER IMPEDANCE CONTROL APPARATUS AND SYSTEM
    • 驱动阻抗控制装置和系统
    • US20070057692A1
    • 2007-03-15
    • US11162531
    • 2005-09-14
    • Chien-Hui ChuangRen-Jeng ChiangIh-Hwa Chang
    • Chien-Hui ChuangRen-Jeng ChiangIh-Hwa Chang
    • H03K19/003
    • H03K19/0005
    • A driver impedance control apparatus and system for determining the impedance of at least one driver are provided. The driver impedance control apparatus includes a first reference impedance, a second reference impedance, a dummy pull-up array, a dummy pull-down array, a pull-up array control unit and a pull-down array control unit. The pull-up array control unit controls the pull-up impedance of the driver by detecting a voltage from a first voltage divide point between the first reference impedance and the dummy pull-up array. The pull-down array control unit controls the pull-down impedance of the driver by detecting a voltage from a second voltage divide point between the second reference impedance and the dummy pull-down array.
    • 提供了用于确定至少一个驱动器的阻抗的驱动器阻抗控制装置和系统。 驱动器阻抗控制装置包括第一参考阻抗,第二参考阻抗,虚拟上拉阵列,虚拟下拉阵列,上拉阵列控制单元和下拉阵列控制单元。 上拉阵列控制单元通过检测来自第一参考阻抗和虚拟上拉阵列之间的第一分压点的电压来控制驱动器的上拉阻抗。 下拉阵列控制单元通过检测来自第二参考阻抗和虚拟下拉阵列之间的第二分压点的电压来控制驱动器的下拉阻抗。
    • 8. 发明授权
    • Power-rail electrostatic discharge protection circuit with a dual trigger design
    • 电源轨静电放电保护电路采用双触发设计
    • US06728086B2
    • 2004-04-27
    • US10050018
    • 2002-01-15
    • Kei-Kang HungChien-Hui Chuang
    • Kei-Kang HungChien-Hui Chuang
    • H02H900
    • H01L27/0266H01L2924/0002H01L2924/00
    • A power-rail ESD (electrostatic discharge) protection circuit with a dual trigger design is proposed, which is coupled between a first power line and a second power line connected to an IC device for protecting the IC device against ESD on the first power line and the second power line. The proposed power-rail ESD protection circuit comprises a control circuit and at least one MOS device. The control circuit is coupled between the first power line and the second power line, and which is capable of, in the event of ESD in the first power line and the second power line, being triggered by the ESD to output a substrate-triggering voltage and a gate-driving voltage to the MOS device, causing the MOS device to bypass the ESD current from the first power line and the second power line. The circuit configuration of the proposed power-rail ESD protection circuit can help reduce the junction breakdown voltage in a MOS device and increase in ESD robustness.
    • 提出了具有双触发设计的电力轨道ESD(静电放电)保护电路,其耦合在连接到IC装置的第一电力线和第二电力线之间,用于保护IC装置免受第一电力线上的ESD, 第二条电力线。 所提出的电源轨ESD保护电路包括控制电路和至少一个MOS器件。 控制电路耦合在第一电力线和第二电力线之间,并且其能够在第一电力线和第二电力线中的ESD的情况下被ESD触发以输出基板触发电压 以及向MOS器件施加栅极驱动电压,使MOS器件从第一电力线和第二电力线旁路ESD电流。 所提出的电力轨道ESD保护电路的电路配置有助于降低MOS器件中的结击穿电压,增加ESD稳定性。
    • 9. 发明授权
    • Electrostatic discharge protection circuit for protecting input and output buffer
    • 用于保护输入和输出缓冲器的静电放电保护电路
    • US06639772B2
    • 2003-10-28
    • US10041237
    • 2002-01-07
    • Chien-Hui ChuangKei-Kang Hung
    • Chien-Hui ChuangKei-Kang Hung
    • H02H300
    • H01L27/0277
    • An electrostatic discharge (ESD) protection circuit for protecting input and output buffers. The ESD protection circuit is driven by a first voltage source and a second voltage source and coupled to a bonding pad. The ESD protection circuit has a first resistor, a first PMOS transistor, a first NMOS transistor, a first diode series, a second PMOS transistor, a second resistor, a third PMOS transistor, a second NMOS transistor, a second diode series and a third NMOS transistor. The electrical devices combine to form different types of ESD protection circuits, each capable of protecting the input buffer or output buffer against the damaging effects of an electrostatic discharge.
    • 一种用于保护输入和输出缓冲器的静电放电(ESD)保护电路。 ESD保护电路由第一电压源和第二电压源驱动并耦合到接合焊盘。 ESD保护电路具有第一电阻器,第一PMOS晶体管,第一NMOS晶体管,第一二极管系列,第二PMOS晶体管,第二电阻器,第三PMOS晶体管,第二NMOS晶体管,第二二极管串联和第三 NMOS晶体管。 电气设备组合形成不同类型的ESD保护电路,每个ESD保护电路能够保护输入缓冲器或输出缓冲器免受静电放电的破坏作用。