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1. 发明授权

US06894324B2 Silicon-on-insulator diodes and ESD protection circuits 有权
标题翻译：绝缘体上硅二极管和ESD保护电路
公开(公告)号：US06894324B2
公开(公告)日：2005-05-17
申请号：US09783870
申请日：2001-02-15
申请人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
发明人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
IPC分类号： H01L27/02 , H01L29/739 , H01L29/861 , H01L31/072
CPC分类号： H01L29/4991 , H01L27/0251 , H01L29/4983 , H01L29/7391 , H01L29/861
摘要： A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and then also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits. The proposed gated diode and non-gated diode can be fully process-compatiable to general partially depleted or fully-depleted silicon-on-insulator CMOS processes.
摘要翻译：提供了绝缘体上硅（SOI）门控二极管和非门控结二极管。 SOI门控二极管在栅极下方的中间区域具有PN结，并且具有比正常二极管更多的结面积。 SOI非门控结二极管在其中间区域具有PN结，然后还具有比正常二极管更多的结面积。本发明的SOI二极管由于低功率密度和加热而提供了针对电应力（EOS）/静电放电（ESD）的保护等级，以提供比正常功率密度更多的接合面积。包括主二极管，第一多个二极管和第二多个二极管的I / O ESD保护电路全部由本SOI SOI形成，当存在ESD事件时，可以有效地放电。而且，包含更多初级二极管的ESD保护电路可以有效地降低寄生输入电容，从而可以将它们用于RF电路或HF电路。所提出的门控二极管和非门控二极管可以完全兼容于一般部分耗尽或完全耗尽的绝缘体上硅CMOS工艺。

2. 发明授权

US07141484B2 Electrostatic discharge protection circuit of non-gated diode and fabrication method thereof 有权
公开(公告)号：US07141484B2
公开(公告)日：2006-11-28
申请号：US10702372
申请日：2003-11-05
申请人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
发明人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
IPC分类号： H01L21/76
CPC分类号： H01L27/08 , H01L21/84 , H01L27/0255 , H01L27/0814 , H01L27/1203
摘要： A non-gated diode structure of a silicon-on-insulator, having a silicon-on-insulator substrate, a pair of isolating structures, a first type doped region and a second type doped region. The silicon-on-insulation substrate has a stack of a substrate, an insulation layer and a silicon layer. The isolating structures are located in the silicon layer to define a well region. The first and second type doped regions are located in the well and are adjacent to the isolating structures. Such a non-gated diode structure can be applied to an electrostatic discharge protection circuit to increase the electrostatic discharge protection voltage or current. In addition, a fabrication method of the non-gated diode is also introduced. This non-gated diode can be also fabricated in the general bulk CMOS process, and used in the on-chip ESD protection circuits.

3. 发明授权

US06933573B2 Electrostatic discharge protection circuit of non-gated diode and fabrication method thereof 有权
标题翻译：非门控二极管的静电放电保护电路及其制造方法
公开(公告)号：US06933573B2
公开(公告)日：2005-08-23
申请号：US10060743
申请日：2002-01-30
申请人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
发明人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
IPC分类号： H01L21/84 , H01L27/02 , H01L27/08 , H01L27/12 , H01L23/62
CPC分类号： H01L27/08 , H01L21/84 , H01L27/0255 , H01L27/0814 , H01L27/1203
摘要： A non-gated diode structure of a silicon-on-insulator, having a silicon-on-insulator substrate, a pair of isolating structures, a first type doped region and a second type doped region. The silicon-on-insulation substrate has a stack of a substrate, an insulation layer and a silicon layer. The isolating structures are located in the silicon layer to define a well region. The first and second type doped regions are located in the well and are adjacent to the isolating structures. Such a non-gated diode structure can be applied to an electrostatic discharge protection circuit to increase the electrostatic discharge protection voltage or current. In addition, a fabrication method of the non-gated diode is also introduced. This non-gated diode can be also fabricated in the general bulk CMOS process, and used in the on-chip ESD protection circuits.
摘要翻译：绝缘体上硅的非门控二极管结构，其具有绝缘体上硅衬底，一对隔离结构，第一类型掺杂区和第二类型掺杂区。硅绝缘基板具有基板，绝缘层和硅层的堆叠。隔离结构位于硅层中以限定阱区。第一和第二类型掺杂区域位于阱中并且与隔离结构相邻。这种非门控二极管结构可以应用于静电放电保护电路以增加静电放电保护电压或电流。此外，还介绍了非门控二极管的制造方法。这种非门控二极管也可以在通常的体CMOS工艺中制造，并且用于片上ESD保护电路。

4. 发明授权

US06861680B2 Silicon-on-insulator diodes and ESD protection circuits 有权
标题翻译：绝缘体上硅二极管和ESD保护电路
公开(公告)号：US06861680B2
公开(公告)日：2005-03-01
申请号：US10315158
申请日：2002-12-10
申请人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
发明人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
IPC分类号： H01L27/02 , H01L29/739 , H01L29/861 , H01L31/072
CPC分类号： H01L29/4991 , H01L27/0251 , H01L29/4983 , H01L29/7391 , H01L29/861
摘要： A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits. The proposed gated diode and non-gated diode can be fully process-compatiable to general partially-depleted or fully-depleted silicon-on-insulator CMOS processes.
摘要翻译：提供了绝缘体上硅（SOI）门控二极管和非门控结二极管。 SOI栅控二极管在栅极下方的中间区域具有PN结，其具有比正常二极管更多的结面积。 SOI非门控结二极管在其中间区域具有PN结，并且还具有比正常二极管更多的结面积。本发明的SOI二极管由于低功率密度和加热而提供了针对电应力（EOS）/静电放电（ESD）的保护等级，以提供比正常功率密度更多的接合面积。包括主二极管，第一多个二极管和第二多个二极管的I / O ESD保护电路全部由本SOI SOI形成，当存在ESD事件时，可以有效地放电。并且包括更多初级二极管的ESD保护电路可以有效地减小寄生输入电容，使得它们可以用在RF电路或HF电路中。所提出的门控二极管和非门控二极管可以完全兼容于一般部分耗尽或完全耗尽的绝缘体上硅CMOS工艺。

5. 发明授权

US06653670B2 Silicon-on-insulator diodes and ESD protection circuits 有权
公开(公告)号：US06653670B2
公开(公告)日：2003-11-25
申请号：US10315157
申请日：2002-12-10
申请人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
发明人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
IPC分类号： H01L3072
CPC分类号： H01L29/4991 , H01L27/0251 , H01L29/4983 , H01L29/7391 , H01L29/861
摘要： A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and then also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits. The proposed gated diode and non-gated diode can be fully process-compatiable to general partially-depleted or fully-depleted silicon-on-insulator CMOS processes.

6. 发明授权

US06649944B2 Silicon-on-insulator diodes and ESD protection circuits 有权
标题翻译：绝缘体上硅二极管和ESD保护电路
公开(公告)号：US06649944B2
公开(公告)日：2003-11-18
申请号：US10315161
申请日：2002-12-10
申请人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
发明人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
IPC分类号： H01L31072
CPC分类号： H01L29/4991 , H01L27/0251 , H01L29/4983 , H01L29/7391 , H01L29/861
摘要： A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, thus providing more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and thus also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits. The proposed gated diode and non-gated diode can be fully process-compatible to general partially-depleted or fully-depleted silicon-on-insulator CMOS processes.
摘要翻译：提供了绝缘体上硅（SOI）门控二极管和非门控结二极管。 SOI门控二极管在栅极下方的中间区域具有PN结，因此提供比正常二极管更多的接合面积。 SOI非门控结二极管在其中间区域具有PN结，因此也具有比正常二极管更多的结面积。本发明的SOI二极管由于低功率密度和加热而提供了针对电应力（EOS）/静电放电（ESD）的保护等级，以提供比正常功率密度更多的接合面积。包括主二极管，第一多个二极管和第二多个二极管的I / O ESD保护电路全部由本SOI SOI形成，当存在ESD事件时，可以有效地放电。而且，包含更多初级二极管的ESD保护电路可以有效地降低寄生输入电容，从而可以将它们用于RF电路或HF电路。所提出的门控二极管和非门控二极管可以完全兼容于一般部分耗尽或完全耗尽的绝缘体上硅CMOS工艺。

7. 发明授权

US06521952B1 Method of forming a silicon controlled rectifier devices in SOI CMOS process for on-chip ESD protection 有权
标题翻译：在SOI CMOS工艺中形成用于片上ESD保护的可控硅整流器件的方法
公开(公告)号：US06521952B1
公开(公告)日：2003-02-18
申请号：US09682811
申请日：2001-10-22
申请人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
发明人： Ming-Dou Ker , Kei-Kang Hung , Tien-Hao Tang
IPC分类号： H01L2362
CPC分类号： H01L27/0262
摘要： An NMOS-trigger silicon controlled rectifier in silicon-on-insulator (SOI-NSCR) SOI-NSCR includes a P-type well and an N-type well. A first P+ doping region and a first N+ doping region are in the N-type well and form the anode of the SOI-NSCR. A second P+ doping region and a second N+ doping region are in the P-type well and form the cathode of the SOI-NSCR. The first P+ doping region, the N-type well, the P-type well and the second N+ doping region form a lateral SCR. A third N+ doping region is across the N-type well and the P-type well. A gate is in the P-type well, and the third N+ doping region, the gate and the second N+ doping region form an NMOS. A dummy gate is in the N-type well for isolating the first P+ doping region and the third N+ doping region. When a voltage is applied to the gate of the NMOS that turns on the NMOS, a forward bias is created from the N-type well to the P-type well that turns on the SOI-NSCR. When a voltage is applied to the third N+ doping region, a trigger current is generated that causes the lateral SCR to enter a latch state and so the SOI-NSCR is quickly turned on. Utilizing similar and related designs, the present invention discloses a PMOS-trigger silicon controlled rectifier in silicon-on-insulator (SOI-PSCR), and ESD protection circuitry utilizing the SOI-NSCR and the SOI-PSCR.
摘要翻译：绝缘体上硅（SOI-NSCR）SOI-NSCR中的NMOS触发可控硅整流器包括P型阱和N型阱。第一P +掺杂区和第一N +掺杂区位于N型阱中并形成SOI-NSCR的阳极。第二P +掺杂区和第二N +掺杂区位于P型阱中并形成SOI-NSCR的阴极。第一P +掺杂区，N型阱，P型阱和第二N +掺杂区形成横向SCR。第三个N +掺杂区跨越N型阱和P型阱。栅极位于P型阱中，第三N +掺杂区，栅极和第二N +掺杂区形成NMOS。 N型阱中的伪栅极用于隔离第一P +掺杂区和第三N +掺杂区。当电压施加到导通NMOS的NMOS的栅极时，产生从N型阱到引导SOI-NSCR的P型阱的正向偏压。当向第三N +掺杂区域施加电压时，产生触发电流，使得横向SCR进入锁存状态，因此SOI-NSCR快速导通。利用相似和相关的设计，本发明公开了一种在绝缘体上硅（SOI-PSCR）中的PMOS触发可控硅整流器，以及利用SOI-NSCR和SOI-PSCR的ESD保护电路。

8. 发明授权

US06768619B2 Low-voltage-triggered SOI-SCR device and associated ESD protection circuit 有权
标题翻译：低电压触发SOI-SCR器件和相关的ESD保护电路
公开(公告)号：US06768619B2
公开(公告)日：2004-07-27
申请号：US10367502
申请日：2003-02-13
申请人： Ming-Dou Ker , Kei-Kang Hung , Shao-Chang Huang
发明人： Ming-Dou Ker , Kei-Kang Hung , Shao-Chang Huang
IPC分类号： H02H900
CPC分类号： H01L27/0262
摘要： A silicon-on-insulator low-voltage-triggered silicon controlled rectifier device structure that is built upon a substrate and an insulation layer. The insulation layer has a plurality of isolation structures thereon to define a device region. A first-type well and a second-type well are formed over the insulation layer. The first-type and second-type wells are connected. A first gate and a second gate are formed over the first-type well and the second-type well, respectively. The first-type well further includes a first second-type doped region and a first first-type doped region formed between the first second-type doped region and the isolation structure adjacent to the first second-type doped region. The first second-type doped region and the first first-type doped region together form a cathode of the SOI-SCR device. A second first-type doped region is formed within the first-type well between the first second-type doped region and the first gate structure adjacent to the first second-type doped region. A third first-type doped region is formed within the first and the second-type well around their junction between the first and second-type well. The second-type well further includes a second second-type doped region and a fourth first-type doped region within the second-type well between the second second-type doped region and the second gate adjacent to the second second-type doped region. The second second-type doped region and the fourth first-type doped region together form an anode of the SOI-SCR device.
摘要翻译：一种绝缘体上的绝缘体上的低电压触发的可控硅整流器件结构，其构造在衬底和绝缘层上。绝缘层在其上具有多个隔离结构以限定器件区域。在绝缘层上形成第一型阱和第二型阱。第一类和第二类型井连接。分别在第一型阱和第二型阱上形成第一栅极和第二栅极。第一类阱还包括形成在与第一第二类型掺杂区相邻的第一第二掺杂区和隔离结构之间的第一第二掺杂区和第一第一掺杂区。第一第二掺杂区域和第一第一掺杂区域一起形成SOI-SCR器件的阴极。在第一第二类型掺杂区域和与第一第二掺杂区域相邻的第一栅极结构之间的第一类型阱内形成第二第一类型掺杂区域。在第一和第二类型阱内围绕第一和第二类型阱的连接点形成第三第一类型掺杂区域。第二类阱还包括在第二第二类型掺杂区域和与第二第二类型掺杂区域相邻的第二栅极之间的第二类型阱内的第二第二类型掺杂区域和第四第一类型掺杂区域。第二二次掺杂区域和第四第一掺杂区域一起形成SOI-SCR器件的阳极。

9. 发明授权

US06671147B2 Double-triggered electrostatic discharge protection circuit 有权
公开(公告)号：US06671147B2
公开(公告)日：2003-12-30
申请号：US09872180
申请日：2001-06-01
申请人： Ming-Dou Ker , Kei-Kang Hung , Shao-Chang Huang
发明人： Ming-Dou Ker , Kei-Kang Hung , Shao-Chang Huang
IPC分类号： H02H900
CPC分类号： H01L27/0274 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A double-triggered electrostatic discharge (ESD) protection circuit for coupling with a first voltage source and a second voltage source. The circuit includes a diode series and a transistor. The diode series comprises a plurality of serially connected diodes with the cathode of one diode connected to the anode of a subsequent diode. The positive terminal of the first diode in the diode series connects with the first voltage source. The gate terminal of the transistor connects with the anode of the last diode in the diode series. The substrate of the transistor connects with the cathode of the last diode in the diode series. The source terminal and the drain terminal of the transistor connect with the first voltage source and the second voltage source, respectively. By using double-triggered design, the ESD clamp device can be quickly triggered on to bypass ESD current. Therefore, the ESD protection circuit has a better protection capability to protect the IC in deep-submicron CMOS technologies against ESD damage.

10. 发明授权

US06750515B2 SCR devices in silicon-on-insulator CMOS process for on-chip ESD protection 有权
标题翻译：用于片上ESD保护的硅绝缘体CMOS工艺中的SCR器件
公开(公告)号：US06750515B2
公开(公告)日：2004-06-15
申请号：US10062714
申请日：2002-02-05
申请人： Ming-Dou Ker , Kei-Kang Hung , Chyh-Yih Chang
发明人： Ming-Dou Ker , Kei-Kang Hung , Chyh-Yih Chang
IPC分类号： H01L2776
CPC分类号： H01L27/0262 , H01L27/1203
摘要： A silicon-on-isolator CMOS integrated circuit device includes a semiconductor substrate, an isolation layer formed over the semiconductor substrate, an n-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer, and a p-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer and contiguous with the n-type MOS transistor, wherein the n-type MOS transistor and the p-type MOS transistor form a silicon controlled rectifier to provide electrostatic discharge protection.
摘要翻译：硅隔离器CMOS集成电路器件包括半导体衬底，形成在半导体衬底上的隔离层，具有形成在隔离层上的栅极，漏极区域和源极区域的n型MOS晶体管，以及 p型MOS晶体管，其具有形成在隔离层上并与n型MOS晶体管邻接的栅极，漏极区域和源极区域，其中n型MOS晶体管和p型MOS晶体管形成硅控制整流器提供静电放电保护。

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