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1. 发明授权

US06534365B2 Method of fabricating TDMOS device using self-align technique 有权
标题翻译：使用自对准技术制造TDMOS器件的方法
公开(公告)号：US06534365B2
公开(公告)日：2003-03-18
申请号：US09726910
申请日：2000-11-29
申请人： Jong Dae Kim , Sang Gi Kim , Jin Gun Koo , Kee Soo Nam , Dae Woo Lee , Tae Moon Roh
发明人： Jong Dae Kim , Sang Gi Kim , Jin Gun Koo , Kee Soo Nam , Dae Woo Lee , Tae Moon Roh
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/42368
摘要： A method of fabricating a vertical TDMOS power device using sidewall spacers and a self-align technique and a TDMOS power device of the same. The TDMOS is fabricated using only 3 masks and a source is formed using the self-align technique to embody a highly integrated trench formation. During the process, ion implantation of high concentration into the bottom of the trench makes a thick oxide film grow on the bottom and the corner of the gate, so that electrical characteristic, specifically leakage current and breakdown voltage of the device can be improved. Also, process steps can be much decreased to lower process cost, high integration is possible, and reliability of the device can be improved.
摘要翻译：使用侧壁间隔物和自对准技术制造垂直TDMOS功率器件的方法以及使用其的TDMOS功率器件。 TDMOS仅使用3个掩模制造，并且使用自对准技术形成源以体现高度集成的沟槽形成。在此过程中，高浓度离子注入沟槽的底部使得厚的氧化膜在栅极的底部和拐角处生长，从而可以提高器件的电气特性，特别是漏电流和击穿电压。此外，可以大大降低工艺步骤以降低工艺成本，可以实现高集成度，并且可以提高器件的可靠性。

2. 发明授权

US6063201A Effusion cell assembly for epitaxial apparatus 有权
标题翻译：用于外延设备的流出池组件
公开(公告)号：US6063201A
公开(公告)日：2000-05-16
申请号：US141557
申请日：1998-08-28
申请人： Hae Gwon Lee , Gyu Hwan Sim , Sung Woo Choi , Mun Cheol Baek , Kee Soo Nam
发明人： Hae Gwon Lee , Gyu Hwan Sim , Sung Woo Choi , Mun Cheol Baek , Kee Soo Nam
IPC分类号： H01L21/20 , C30B23/06 , C23C16/00
CPC分类号： C30B23/066
摘要： An effusion cell assembly for epitaxial apparatus is disclosed. The assembly includes an effusion cell incluing a growing material, a heater for supplying heats with the effusion cell to effuse the growing material, a supporting plate for supporting the heater, a bolt having one end connected to the supporting plate, a cell flange coupled to a lower flange of an adaptor for supporting the cell assembly, bellows fixed between the supporting plate and the cell flange including the bolt, and a control nut for expanding and contracting the bellows so as to separate only the cell assembly from a vacuum chamber with entire vacuum maintained in the vacuum chamber and local vacuum released in the cell assembly. The epitaxial apparatus further includes a control valve located between an entrance flange of the vacuum chamber and an upper adaptor flange of the adaptor for introducing and maintaining vacuum in the vacuum chamber.
摘要翻译：公开了一种用于外延设备的渗流池组件。组件包括包含生长材料的积液池，用于向渗出池供应热量以加热生长材料的加热器，用于支撑加热器的支撑板，具有连接到支撑板的一端的螺栓，耦合到用于支撑电池组件的适配器的下凸缘，固定在支撑板和包括螺栓的电池凸缘之间的波纹管，以及用于膨胀和收缩波纹管的控制螺母，以便仅将电池组件与真空室整体分离在真空室中保持真空并在电池组件中释放局部真空。外延装置还包括位于真空室的入口凸缘和适配器的上适配器凸缘之间的控制阀，用于在真空室中引入和保持真空。

3. 发明授权

US5711693A Process for formation of large area flat panel display using side junction 失效
标题翻译：使用侧面结合形成大面积平板显示器的方法
公开(公告)号：US5711693A
公开(公告)日：1998-01-27
申请号：US357019
申请日：1994-12-16
申请人： Kee-Soo Nam , Sin-Chong Park , Sang-Joon Park , Sang-Ho Kim
发明人： Kee-Soo Nam , Sin-Chong Park , Sang-Joon Park , Sang-Ho Kim
IPC分类号： G02F1/1333 , G02F1/13 , G02F1/133 , G02F1/136 , G02F1/1362 , G02F1/1368 , G09F9/35 , H01L21/336 , H01L29/786 , H01J9/18
CPC分类号： G02F1/1362 , G02F1/13336
摘要： A process for formation of a large area flat panel display, and particularly a process for formation of a large area flat panel display using a side junction is disclosed, in which a large area is achieved by utilizing a side junction. More specifically, there is provided a process for formation of a thin film transistor liquid crystal display which can be used on all kinds of flat panel displays which uses glass as the substrate. The process for formation of a large area flat panel display utilizing a side junction according to the present invention includes the steps of: applying a side junction process on thin film transistor unit panels 2 so as to obtain a large area; and coupling a common electrode panel with said large area thin film transistor panel formed through said side junction process.
摘要翻译：公开了一种用于形成大面积平板显示器的方法，特别是用于形成使用侧面接合处的大面积平板显示器的工艺，其中通过利用侧面接合来实现大面积。更具体地，提供了可用于各种使用玻璃作为基板的平板显示器的薄膜晶体管液晶显示器的形成工艺。根据本发明的用于形成使用侧面接合的大面积平板显示器的方法包括以下步骤：在薄膜晶体管单元面板2上施加侧接处理以获得大面积; 以及将公共电极面板与通过所述侧面连接工艺形成的所述大面积薄膜晶体管面板耦合。

4. 发明授权

US6087232A Fabrication method of lateral double diffused MOS transistors 有权
标题翻译：横向双扩散MOS晶体管的制造方法
公开(公告)号：US6087232A
公开(公告)日：2000-07-11
申请号：US135645
申请日：1998-08-18
申请人： Jong Dae Kim , Sang Ki Kim , Jin Gun Koo , Kee Soo Nam
发明人： Jong Dae Kim , Sang Ki Kim , Jin Gun Koo , Kee Soo Nam
IPC分类号： H01L21/02 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66659 , H01L29/7835
摘要： According to a method for manufacturing double RESURF (reduced SURface Field) LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistors, on-resistance of double RESURF LDMOS transistors has been improved by using a new tapered p top layer on the surface of the drift region of the transistor, thereby decreasing the length of the drift region. Another advantage of the current invention is that the breakdown voltage similar with the on-resistance can be improved by using a reproducible tapered TEOS oxide by use of a multi-layer structure and low temperature annealing process. This is due to the reducing of the current path and impurity segregation in the drift region by using the tapered TEOS oxide instead of LOCOS filed oxide.
摘要翻译：根据制造双RESURF（减少的SURface Field）LDMOS（侧向扩散金属氧化物半导体）晶体管的方法，通过在漂移区的表面上使用新的锥形p顶层，改善了双RESURF LDMOS晶体管的导通电阻晶体管，从而减小漂移区的长度。本发明的另一个优点是可以通过使用多层结构和低温退火工艺使用可再现的锥形TEOS氧化物来改善与导通电阻相似的击穿电压。这是由于通过使用锥形TEOS氧化物而不是LOCOS氧化物来减少漂移区中的电流路径和杂质偏析。

5. 发明授权

US5793096A MOS transistor embedded inductor device using multi-layer metallization technology 失效
标题翻译： MOS晶体管嵌入式电感器件采用多层金属化技术
公开(公告)号：US5793096A
公开(公告)日：1998-08-11
申请号：US846422
申请日：1997-04-30
申请人： Hyun-Kyu Yu , Cheon-Soo Kim , Kee-Soo Nam
发明人： Hyun-Kyu Yu , Cheon-Soo Kim , Kee-Soo Nam
IPC分类号： H01L27/02 , H01L27/06 , H01L29/00
CPC分类号： H01L27/0617 , H01F2021/125
摘要： An inductor device with a MOS transistor internally installed is disclosed, in which an inductor can be arbitrarily connected in series or in parallel to the respective terminals of MOS transistors by applying a multi-layer wiring technique, thereby reducing the chip area. Within an inductor structure, MOS transistors which have an active region width of W .mu.m are formed in the number of n, and an inductor wire is connected to an arbitrary terminal of the MOS transistors by employing a multi-layer metal wiring process. Thus the inductor is connected to an arbitrary terminal of the MOS transistors in series. Thus an inductor device in which MOS transistors having a channel width of W.times.n .mu.m are internally installed is formed.
摘要翻译：公开了一种内置MOS晶体管的电感器件，其中通过施加多层布线技术，电感器可以与MOS晶体管的各个端子串联或并联连接，从而减小芯片面积。在电感器结构中，以n个数量形成有效区宽度为W m m的MOS晶体管，并且通过采用多层金属布线工艺将电感器线连接到MOS晶体管的任意端。因此，电感器串联连接到MOS晶体管的任意端子。因此，形成其内部安装有沟道宽度为Wxnμm的MOS晶体管的电感器件。

6. 发明授权

US5589083A Method of manufacturing microstructure by the anisotropic etching and bonding of substrates 失效
标题翻译：通过各向异性蚀刻和基板粘合制造微结构的方法
公开(公告)号：US5589083A
公开(公告)日：1996-12-31
申请号：US346205
申请日：1994-11-22
申请人： Kun-Young Ahn , Kyung-Ho Park , Kee-Soo Nam , Sang-Won Kang
发明人： Kun-Young Ahn , Kyung-Ho Park , Kee-Soo Nam , Sang-Won Kang
IPC分类号： B41J2/135 , B44C1/22 , B44C3/00 , B81C1/00 , G02B1/00 , H01L21/02 , H01L21/20 , H01L21/306 , H01L29/84 , H01L21/00
CPC分类号： B44C1/227 , B44C3/005 , B81C1/00626 , H01L21/2007 , B81B2201/047 , B81B2201/052 , B81B2203/0353 , B81B2203/0361 , B81C2201/0133 , B81C2201/019 , Y10S438/973
摘要： The present invention relates to a method of manufacturing microstructure by the anisotropic etching and bonding of substrates so as to manufacture mechanically functioning micro-structures in various forms by uniting the same or different substrate bonding technique and selective anisotropic etching technique. This invention manufactures a pyramidal optical divider or an optical divider with a pyramidal structure located on a quadrilateral pillar by bonding one substrate on a substrate different in the direction of crystallization and anisotropically etching them thereafter. This invention manufactures variously shaped nozzles by bonding those substrates crystallized in a different direction and anisotropically etching them so that substrates bonded by one photograph transferring process may form different etching holes. This invention manufactures a diaphragm having a uniform thickness and a wide area by bonding two substrates different in the direction of crystallization or in the concentration of an impurity, removing a substrate of prescribed concentration and anisotropically etching only one substrate of the remaining substrates.
摘要翻译：本发明涉及通过各向异性蚀刻和基板的接合来制造微结构的方法，以便通过结合相同或不同的基板接合技术和选择性各向异性蚀刻技术来制造各种形式的机械功能的微结构。本发明通过将一个衬底粘结在不同于结晶方向的衬底上并以其各向异性蚀刻的方式制造棱锥形光学分配器或具有位于四边形柱上的锥体结构的光学分配器。本发明通过将在不同方向上结晶的基片结合在一起，通过各向异性蚀刻它们来制造各种形状的喷嘴，使得通过一次照片转印工艺粘合的基板可以形成不同的蚀刻孔。本发明通过粘合两个不同结晶方向的基板或杂质浓度，除去规定浓度的基板，并且各向异性蚀刻剩余基板的一个基板，制造具有均匀厚度和宽面积的隔膜。

7. 发明授权

US06211018B1 Method for fabricating high density trench gate type power device 有权
标题翻译：高密度沟槽栅型功率器件的制造方法
公开(公告)号：US06211018B1
公开(公告)日：2001-04-03
申请号：US09475281
申请日：1999-12-30
申请人： Kee Soo Nam , Sang Gi Kim , Tae Moon Roh , Jin Gun Koo
发明人： Kee Soo Nam , Sang Gi Kim , Tae Moon Roh , Jin Gun Koo
IPC分类号： H01L21336
CPC分类号： H01L29/66727 , H01L29/66348
摘要： A semiconductor technique is disclosed. Particularly a low voltage high current power device for use in a lithium ion secondary battery protecting circuit, a DC-DC converter and a motor is disclosed. Further, a method for fabricating a high density trench gate type power device is disclosed. That is, in the present invention, a trench gate mask is used for forming the well and/or source, and for this purpose, a side wall spacer is introduced. In this manner, the well and/or source is defined by using the trench gate mask, and therefore, 1 or 2 masking processes are skipped unlike the conventional process in which the well mask and the source mask are separately used. The decrease in the use of the masking process decreases the mask align errors, and therefore, the realization of a high density is rendered possible. Consequently, the on-resistance which is an important factor for the power device can be lowered.
摘要翻译：公开了半导体技术。特别地，公开了一种用于锂离子二次电池保护电路，DC-DC转换器和电动机的低压大电流功率器件。此外，公开了一种制造高密度沟槽栅型功率器件的方法。也就是说，在本发明中，沟槽栅极掩模用于形成阱和/或源，为此，引入了侧壁间隔物。以这种方式，通过使用沟槽栅极掩模来定义阱和/或源，因此与分开使用阱掩模和源掩模的常规工艺不同，跳过1或2个屏蔽处理。掩蔽过程的使用减少会降低掩模对准误差，因此可以实现高密度。因此，作为功率器件的重要因素的导通电阻可以降低。

8. 发明授权

US6040001A Method of manufacturing a diamond vacuum device 失效
标题翻译：制造金刚石真空装置的方法
公开(公告)号：US6040001A
公开(公告)日：2000-03-21
申请号：US136614
申请日：1998-08-20
申请人： Mun Cheol Paek , Sung Woo Choi , Kee Soo Nam
发明人： Mun Cheol Paek , Sung Woo Choi , Kee Soo Nam
IPC分类号： H01L29/68 , H01J9/02 , H01J21/10 , B05D5/12 , C23C16/00
CPC分类号： H01J21/105 , H01J9/025 , H01J2201/30457
摘要： This invention discloses a method of manufacturing a diamond vacuum device, and more particularly a method of manufacturing a diamond vacuum device which uses a diamond thin film as an electron emitter by electric field. The present invention presents a method of manufacturing a vacuum device for use in high speed, high voltage, using diamond having a negative electron affinity, which can emit electrons even at a low voltage and is also resistant to chemical variations.
摘要翻译：本发明公开了一种制造金刚石真空装置的方法，特别是一种制造金刚石真空装置的方法，金刚石真空装置通过电场使用金刚石薄膜作为电子发射体。本发明提供了一种使用具有负电子亲和力的金刚石制造用于高速，高电压的真空装置的方法，其即使在低电压下也可以发射电子，并且也耐化学变化。

9. 发明授权

US6008097A MOS transistor of semiconductor device and method of manufacturing the same 失效
标题翻译：半导体器件的MOS晶体管及其制造方法
公开(公告)号：US6008097A
公开(公告)日：1999-12-28
申请号：US989033
申请日：1997-12-11
申请人： Yong Sun Yoon , Kyu Ha Baek , Kee Soo Nam
发明人： Yong Sun Yoon , Kyu Ha Baek , Kee Soo Nam
IPC分类号： H01L29/786 , H01L21/225 , H01L21/28 , H01L21/336 , H01L21/768 , H01L29/423
CPC分类号： H01L29/66606 , H01L21/28114 , H01L21/76895 , H01L21/2257 , H01L29/42376
摘要： The present invention relates to a MOS transistor of semiconductor device and method of manufacturing the same and, in particular, to MOS a transistor of semiconductor device and method of manufacturing the same which can reduce asymmetry of drain current due to bias of drain current, facilitate shallow junction and reduce the area to a minimum by forming a source/drain.
摘要翻译：本发明涉及一种半导体器件的MOS晶体管及其制造方法，特别是涉及MOS半导体器件的晶体管及其制造方法，其可以减少由于漏极电流的偏置导致的漏极电流的不对称性浅结，并通过形成源极/漏极将面积减小到最小。

10. 发明授权

US5769679A Method for manufacturing field emission display device 失效
标题翻译：场致发射显示装置的制造方法
公开(公告)号：US5769679A
公开(公告)日：1998-06-23
申请号：US710528
申请日：1996-09-18
申请人： Jong-Moon Park , Yeong-Cheol Hyeon , Kee-Soo Nam
发明人： Jong-Moon Park , Yeong-Cheol Hyeon , Kee-Soo Nam
IPC分类号： H01J17/49 , H01J9/02 , H01J1/30 , H01J9/18
CPC分类号： H01J9/025 , H01J2201/30423
摘要： In a method, a film for a gate electrode, exposed through the sidewall of a trench, is thermally treated to grow a thermal oxide film which is, then, removed at the lateral side of the gate electrode, to spatially separate the gate electrode from the gate insulating film in space. This method precisely controls the thermal oxide film formed at the lateral side of the gate electrode, so that the distance between the gate electrode and the electron emission cathode can be accurately adjusted. The electron emission cathodes are homogeneous in shape. Also, the reliability of the display can be improved since a silicide metal is formed on the electron emission cathodes.
摘要翻译：在一种方法中，通过沟槽的侧壁暴露的用于栅电极的膜被热处理以生长热氧化膜，然后在栅电极的横向侧被去除，以将栅电极与空穴分离栅极绝缘膜在空间。该方法精确地控制在栅电极的侧面形成的热氧化膜，从而可以精确地调节栅电极和电子发射阴极之间的距离。电子发射阴极的形状是均匀的。此外，由于在电子发射阴极上形成硅化物金属，所以可以提高显示器的可靠性。

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