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1. 发明授权

US07342364B2 Light source 有权
标题翻译：光源
公开(公告)号：US07342364B2
公开(公告)日：2008-03-11
申请号：US11226373
申请日：2005-09-15
申请人： Satoru Kato , Tetsu Kachi , Kazuyoshi Tomita , Hiroshi Ito , Masanori Kojima
发明人： Satoru Kato , Tetsu Kachi , Kazuyoshi Tomita , Hiroshi Ito , Masanori Kojima
IPC分类号： H05B37/00
CPC分类号： H05B33/0845 , B82Y20/00 , H01S5/34333 , H05B33/0818 , Y02B20/346
摘要： A light source comprising a light emitting diode comprising a GaN-based compound and having a single quantum well structure, and a driving voltage source for applying a pulse voltage to the light emitting diode, wherein a voltage at a low level of the pulse voltage is set to a voltage lower than a voltage at which a fall time of the light emitting diode is made the longest.
摘要翻译：一种光源，包括包含GaN基化合物并且具有单量子阱结构的发光二极管，以及用于向所述发光二极管施加脉冲电压的驱动电压源，其中所述脉冲电压为低电平的电压为设定为低于发光二极管的下降时间最长的电压的电压。

2. 发明授权

US06964705B2 Method for producing semiconductor crystal 失效
标题翻译：半导体晶体的制造方法
公开(公告)号：US06964705B2
公开(公告)日：2005-11-15
申请号：US10620970
申请日：2003-07-17
申请人： Seiji Nagai , Akira Kojima , Kazuyoshi Tomita
发明人： Seiji Nagai , Akira Kojima , Kazuyoshi Tomita
IPC分类号： C30B29/40 , C30B25/02 , C30B25/18 , H01L21/20 , H01L21/205 , H01L21/324 , H01L33/12 , H01L33/32 , C30B25/12 , C30B25/14
CPC分类号： C30B29/406 , C30B25/02 , C30B25/18 , C30B29/403 , H01L21/0237 , H01L21/0242 , H01L21/02458 , H01L21/02502 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/0265
摘要： A seed layer as a laminate of a GaN layer (second seed layer) and an AlN buffer layer (first seed layer) is formed on a sapphire substrate. A front surface thereof is etched in the form of stripes with a stripe width (seed width) of about 5 μm, a wing width of about 15 μm and a depth of about 0.5 μm. As a result, mesa portions each shaped like nearly a rectangle in sectional view are formed. Non-etched portions each having the seed multilayer as its flat top portion are arranged at arrangement intervals of L≈20 μm. Part of the sapphire substrate is exposed in trough portions of wings. The ratio S/W of the seed width to the wing width is preferably selected to be in a range of from about ⅓ to about ⅕. Then, a semiconductor crystal A is grown to obtain a thickness of not smaller than 50 μm. The semiconductor crystal is separated from the starting substrate to thereby obtain a high-quality single crystal independent of the starting substrate. When a halide vapor phase epitaxy method is used in the condition that the V/III ratio is selected to be in a range of from 30 to 80, both inclusively, a semiconductor crystal free from cracks can be obtained.
摘要翻译：在蓝宝石衬底上形成作为GaN层（第二种子层）和AlN缓冲层（第一种子层）的叠层的种子层。其前表面以条纹宽度（种子宽度）约5μm，翼宽度约15μm，深度约0.5μm的条纹形式蚀刻。结果，形成了截面图中形状为大致矩形的台面部。每个具有种子多层作为其平坦顶部的非蚀刻部分以L≈20μm的排列间隔布置。蓝宝石衬底的一部分暴露在机翼的槽部分。种子宽度与机翼宽度的比率S / W优选选择在约1/3至约1/5的范围内。然后，生长半导体晶体A以获得不小于50μm的厚度。半导体晶体与起始衬底分离，从而获得独立于起始衬底的高质量单晶。在V / III比选择在30〜80的范围内的情况下使用卤化物气相外延法的情况下，均可以获得不含裂纹的半导体结晶。

3. 发明授权

US5940314A Ultra-high density memory device 失效
标题翻译：超高密度存储器件
公开(公告)号：US5940314A
公开(公告)日：1999-08-17
申请号：US9304
申请日：1998-01-20
申请人： Motofumi Suzuki , Takeshi Ohwaki , Yasunori Taga , Hiroshi Tadano , Testu Kachi , Yuichi Tanaka , Kazuyoshi Tomita
发明人： Motofumi Suzuki , Takeshi Ohwaki , Yasunori Taga , Hiroshi Tadano , Testu Kachi , Yuichi Tanaka , Kazuyoshi Tomita
IPC分类号： G11B11/00 , G11B5/00 , G11B5/74 , G11B9/00 , G11B9/14 , G11B13/04 , H01L43/08 , G11C11/42
CPC分类号： B82Y10/00 , G11B5/00 , G11B5/74 , G11B9/14 , G11B9/1409 , G11B13/04 , Y10S977/947
摘要： A ultra-high density memory device utilizing a photoinductive ferromagnetic thin film. A photoinductive ferromagnetic thin film is formed on a GaAs substrate, and a tip is arranged so as to face the photoinductive ferromagnetic thin film. The GaAs substrate is disposed on an xyz scanner, and the three-dimensional positional relationship between the GaAs substrate and the tip is changed by the xyz scanner. Blue light is radiated onto the thin film in order to make the magnetization orientation of molecules uniform. Through application of a relatively high voltage, a relatively large current is caused to flow between the tip and the substrate, so that randomization of the magnetization orientation of molecules of the photoinductive ferromagnetic thin film; i.e., writing operation is carried out. Also, through uniform radiation of circular polarized light onto the GaAs substrate and application of a relatively low voltage, tunneling current is caused to flow between the tip and the substrate, which tunneling current changes in accordance with the magnetization orientation of molecules of the photoinductive ferromagnetic thin film. Through detection of the tunneling current, the magnetization orientation of molecules of the photoinductive ferromagnetic thin film can be detected.
摘要翻译：一种利用感光铁磁性薄膜的超高密度存储器件。在GaAs衬底上形成感光铁磁性薄膜，并且将顶端配置为面对感光性铁磁性薄膜。 GaAs衬底设置在xyz扫描器上，并且通过xyz扫描器改变GaAs衬底和尖端之间的三维位置关系。将蓝光照射到薄膜上，以使分子的磁化取向均匀。通过施加相当高的电压，使得相对较大的电流在尖端和衬底之间流动，从而使感光铁磁性薄膜的分子的磁化取向随机化; 即执行写入操作。此外，通过将均匀的圆偏振光辐射到GaAs衬底上并施加相对低的电压，引起隧道电流在尖端和衬底之间流动，该隧道电流根据感光铁磁体的分子的磁化方向而改变薄膜。通过检测隧道电流，可以检测感光铁磁性薄膜的分子的磁化取向。

4. 发明申请

US20100151612A1 Group III-V semiconductor device and method for producing the same 有权
标题翻译： III-V族半导体器件及其制造方法
公开(公告)号：US20100151612A1
公开(公告)日：2010-06-17
申请号：US12656970
申请日：2010-02-22
申请人： Masanobu Ando , Shigemi Horiuchi , Yoshinori Kinoshita , Kazuyoshi Tomita
发明人： Masanobu Ando , Shigemi Horiuchi , Yoshinori Kinoshita , Kazuyoshi Tomita
IPC分类号： H01L21/20 , H01L21/18
CPC分类号： H01L33/025 , H01L33/0079 , H01L33/46
摘要： A method for producing a Group III-V semiconductor device, includes forming, on a base, a plurality of semiconductor devices isolated from one another, forming, through ion implantation, a high-resistance region in a surface layer of a side surface of each semiconductor device, after formation of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on the top surface of the semiconductor device, bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer, and removing the base through the laser lift-off process.
摘要翻译：一种制造III-V族半导体器件的方法，包括在基底上形成彼此隔离的多个半导体器件，通过离子注入形成每个半导体器件的侧表面的表面层中的高电阻区域半导体器件，在形成高电阻区域之后，在半导体器件的顶表面上形成p电极和低熔点金属扩散防止层，通过低电阻区域将半导体器件接合到导电支撑衬底，熔点金属层，并通过激光剥离工艺去除基体。

5. 发明授权

US07646036B2 Electrode and Group III nitride-based compound semiconductor light-emitting device having the electrode 有权
标题翻译：具有电极的电极和III族氮化物系化合物半导体发光元件
公开(公告)号：US07646036B2
公开(公告)日：2010-01-12
申请号：US12068247
申请日：2008-02-04
申请人： Takahiro Kozawa , Kazuyoshi Tomita , Toshiya Uemura , Shigemi Horiuchi
发明人： Takahiro Kozawa , Kazuyoshi Tomita , Toshiya Uemura , Shigemi Horiuchi
IPC分类号： H01L33/00
CPC分类号： H01L33/405 , H01L33/32 , H01L33/42
摘要： An object of the invention is to prevent migration of silver contained in an electrode of a Group III nitride-based compound semiconductor light-emitting device. A positive electrode is formed on a p-type layer. In the positive electrode, an ITO light-transmitting electrode layer, a silver alloy reflecting electrode layer, a diffusion-preventing layer in which a Ti layer and a Pt layer are stacked, and a gold thick-film electrode are sequentially stacked on the p-type layer. The reflecting electrode layer made of a silver alloy contains palladium (Pd) and copper (Cu) as additives and also contains oxygen (O). By virtue of this structure, migration of silver from the silver alloy reflecting electrode layer and blackening of the interface between the silver alloy layer and the ITO light-transmitting electrode layer disposed thereunder are prevented, whereby light extraction efficiency can be enhanced.
摘要翻译：本发明的目的是防止在III族氮化物系化合物半导体发光元件的电极中含有的银的迁移。正电极形成在p型层上。在正极中，将ITO透光电极层，银合金反射电极层，层叠有Ti层和Pt层的扩散防止层和金厚膜电极依次层叠在p 型层。由银合金制成的反射电极层包含钯（Pd）和铜（Cu）作为添加剂，并且还含有氧（O）。由于这种结构，防止银从银合金反射电极层的迁移以及布置在其上的银合金层和ITO透光电极层之间的界面变黑，从而可以提高光提取效率。

6. 发明授权

US07163876B2 Method for manufacturing group-III nitride compound semiconductor, and group-III nitride compound semiconductor device 有权
标题翻译： III族氮化物化合物半导体的制造方法以及III族氮化物化合物半导体装置
公开(公告)号：US07163876B2
公开(公告)日：2007-01-16
申请号：US10473075
申请日：2002-03-12
申请人： Seiji Nagai , Masayoshi Koike , Kazuyoshi Tomita
发明人： Seiji Nagai , Masayoshi Koike , Kazuyoshi Tomita
IPC分类号： H01L21/36
CPC分类号： H01L21/02647 , H01L21/0237 , H01L21/02381 , H01L21/0254 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L33/007
摘要： In the epitaxial growth process in which each growth region D is zoned by a mask 2 formed in grid pattern, because a consumption region C of the Group III nitride compound semiconductor is formed in the central portion of each band of the mask 2 between each adjacent edge portion of the growth region D, Group III or Group V raw material is never unnecessarily supplied to the edge portion of the growth region D. As a result, difference of Group III or Group V rare material supply amount to the edge portion and central portion of the device formation region D is suppressed and the edge portion of the device region may not be convexity.
摘要翻译：在其中每个生长区域D由栅格图案形成的掩模2划分的外延生长过程中，因为在相邻的每个相邻的掩模2的每个带的中心部分中形成III族氮化物化合物半导体的消耗区域C 生长区域D，组III或组V原料的边缘部分不会不必要地被供给到生长区域D的边缘部分。结果，III族或V族稀有材料供应量与边缘部分和中心器件形成区域D的部分被抑制，器件区域的边缘部分可能不是凸的。

7. 发明授权

US07052979B2 Production method for semiconductor crystal and semiconductor luminous element 有权
标题翻译：半导体晶体和半导体发光元件的制造方法
公开(公告)号：US07052979B2
公开(公告)日：2006-05-30
申请号：US10467566
申请日：2002-02-12
申请人： Seiji Nagai , Kazuyoshi Tomita , Shiro Yamazaki , Yuta Tezen , Toshio Hiramatsu
发明人： Seiji Nagai , Kazuyoshi Tomita , Shiro Yamazaki , Yuta Tezen , Toshio Hiramatsu
IPC分类号： H01L21/20
CPC分类号： C30B25/02 , C30B25/18 , C30B29/403 , C30B29/406 , H01L21/0237 , H01L21/02381 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/0265 , H01L33/0066 , H01L33/007
摘要： When a substrate layer (desired semiconductor crystal) made of a group III nitride compound is grown on a base substrate comprising a lot of projection parts, a cavity in which a semiconductor crystal is not deposited may be formed between each projection part although it depends on conditions such as the size of each projection part, arranging interval between each projection part and crystal growth. So when the thickness of the substrate layer is sufficiently larger compared with the height of the projection part, inner stress or outer stress become easier to act intensively to the projection part. As a result, such stress especially functions as shearing stress toward the projection part. When the shearing stress becomes larger, the projection part is ruptured. So utilizing the shearing stress enables to separate the base substrate and the substrate layer easily. The larger the cavities are formed, the more stress tends to concentrate to the projection parts, to thereby enable to separate the base substrate and the substrate layer more securely.
摘要翻译：当在包括大量投影部分的基底基板上生长由III族氮化物化合物制成的衬底层（期望的半导体晶体）时，可以在每个突出部分之间形成其中不沉积半导体晶体的空腔，尽管它取决于条件如每个投影部分的尺寸，每个投影部分之间的间隔和晶体生长。因此，当基板层的厚度与突出部分的高度相比足够大时，内应力或外应力变得更容易集中于投影部分。结果，这种应力特别地作用于朝向投影部分的剪切应力。当剪切应力变大时，突出部分破裂。因此，利用剪切应力使得能够容易地分离基底和基底层。形成空穴越大，应力越倾向于集中到突出部分，从而能够更牢固地分离基底基底和基底层。

8. 发明授权

US07011707B2 Production method for semiconductor substrate and semiconductor element 有权
标题翻译：半导体衬底和半导体元件的制造方法
公开(公告)号：US07011707B2
公开(公告)日：2006-03-14
申请号：US10473074
申请日：2002-03-27
申请人： Seiji Nagai , Kazuyoshi Tomita , Yoshihiro Irokawa , Kenji Ito
发明人： Seiji Nagai , Kazuyoshi Tomita , Yoshihiro Irokawa , Kenji Ito
IPC分类号： C30B25/22
CPC分类号： C23C16/0272 , H01L21/02381 , H01L21/02458 , H01L21/02505 , H01L21/0254 , H01L21/02664 , H01L33/007 , H01L33/32
摘要： A reaction prevention layer is formed to prevent Si from reacting with a gallium nitride group semiconductor (semiconductor crystal A) which is deposited after the reaction prevention layer is formed. By forming a reaction prevention layer comprising a material whose melting point or thermal stability is higher than that of a gallium nitride group semiconductor, e.g., AlN, on a sacrifice layer, a reaction part is not formed in the semiconductor substrate deposited on the reaction prevention layer when the gallium nitride group semiconductor is grown by crystal growth for a long time. In short, owing to the effect that the reaction prevention layer prevents silicon (Si) from diffusing, the reaction part is generated only in the sacrifice layer and it is never formed at the upper portion of the reaction prevention layer even by growing the semiconductor crystal A at a high temperature for a long time.
摘要翻译：形成反应防止层，以防止Si与形成反应防止层之后沉积的氮化镓基半导体（半导体晶体A）发生反应。通过在牺牲层上形成包含熔点或热稳定性高于氮化镓基半导体（例如AlN）的材料的反应防止层，在沉积在反应预防的半导体衬底中不形成反应部分通过长时间的晶体生长生长氮化镓族半导体时的层。简而言之，由于防反射层防止硅（Si）扩散，反应部分仅在牺牲层中产生，并且即使通过生长半导体晶体也不会形成在反应防止层的上部 A在高温下长时间。

9. 发明授权

US06716655B2 Group III nitride compound semiconductor element and method for producing the same 失效
标题翻译： III族氮化物化合物半导体元件及其制造方法
公开(公告)号：US06716655B2
公开(公告)日：2004-04-06
申请号：US10160288
申请日：2002-06-04
申请人： Seiji Nagai , Masayoshi Koike , Kazuyoshi Tomita
发明人： Seiji Nagai , Masayoshi Koike , Kazuyoshi Tomita
IPC分类号： H01L3304
CPC分类号： C30B23/02 , C30B25/02 , C30B25/18 , C30B29/403 , C30B29/406 , H01L21/02381 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L33/007
摘要： An object of the invention is to produce, at high efficiency, semiconductor elements which are formed of a high-quality crystalline semiconductor having no cracks and a low dislocation density and which have excellent characteristics. Specifically, a mask formed from SiO2 film is provided on the Si(111) plane of an n-type silicon substrate, and a window portion (crystal growth region) in the shape of an equilateral triangle having a side of approximately 300 &mgr;m is formed through the mask. The three sides of the equilateral triangle are composed of three edges; each edge defined by the (111) plane and another crystal plane that is cleavable. Subsequently, a multi-layer structure of semiconductor crystals in an LED is formed through crystal growth of a Group III nitride compound semiconductor. Thus, limiting the area of one crystal growth region to a considerably small area weakens a stress applied to a semiconductor layer, thereby readily producing semiconductor elements having excellent crystallinity. In addition, semiconductor elements can be arranged in a semiconductor wafer at high packing density without loss, and each side of these semiconductor elements can be readily arranged in a line on a semiconductor wafer, thereby enhancing quality, yield, productivity, etc. of semiconductor elements.
摘要翻译：本发明的目的是高效率地制造由没有裂纹和位错密度低且具有优异特性的高品质结晶半导体形成的半导体元件。具体地，在n型硅衬底的Si（111）面上设置由SiO 2膜形成的掩模，并且形成具有约300μm侧面的等边三角形形状的窗口部分（晶体生长区域）通过面具。等边三角形的三面由三边组成，每个边缘由（111）面和另一个可切割的晶体平面限定。随后，通过III族氮化物化合物半导体的晶体生长，形成LED中的半导体晶体的多层结构。因此，将一个晶体生长区域的面积限制在相当小的面积上，削弱施加到半导体层的应力，从而容易地制造具有优异结晶度的半导体元件。此外，半导体元件可以以高封装密度无损耗地布置在半导体晶片中，并且这些半导体元件的每一侧可以容易地布置在半导体晶片上的线上，从而提高半导体的质量，产量，生产率等元素。

10. 发明申请

US20080237629A1 Group III-V Semiconductor device and method for producing the same 审中-公开
标题翻译： III-V族半导体器件及其制造方法
公开(公告)号：US20080237629A1
公开(公告)日：2008-10-02
申请号：US12076234
申请日：2008-03-14
申请人： Masanobu Ando , Shigemi Horiuchi , Yoshinori Kinoshita , Kazuyoshi Tomita
发明人： Masanobu Ando , Shigemi Horiuchi , Yoshinori Kinoshita , Kazuyoshi Tomita
IPC分类号： H01L33/00
CPC分类号： H01L33/025 , H01L33/0079 , H01L33/46
摘要： A Group III-V semiconductor device bonded to a conductive support substrate, which device has a side surface whose surface layer has a high-resistance region formed through ion implantation.
摘要翻译：接合到导电支撑基板的III-V族半导体器件，该器件具有其表面具有通过离子注入形成的高电阻区域的侧表面。

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