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1. 发明申请

US20100013567A1 SWITCHING CAPACITOR GENERATION CIRCUIT 审中-公开
公开(公告)号：US20100013567A1
公开(公告)日：2010-01-21
申请号：US12562107
申请日：2009-09-17
申请人： Kazuhiro TOMITA
发明人： Kazuhiro TOMITA
IPC分类号： H03K3/36
CPC分类号： H03B5/04 , H03H19/004
摘要： A switching capacitor generation circuit which reduces the on-resistance and parasitic capacitance of a switch element and improves the operation properties of the switch element. The switching capacitor generation circuit, which has first and second output terminals, includes a first capacitor coupled to the first output terminal, a second capacitor coupled to the second output terminal, and a single switch element coupled between the first and the second capacitors.

2. 发明申请

US20090322379A1 PEAK HOLD CIRCUIT 有权
标题翻译：峰值保持电路
公开(公告)号：US20090322379A1
公开(公告)日：2009-12-31
申请号：US12483579
申请日：2009-06-12
申请人： Kazuhiro TOMITA
发明人： Kazuhiro TOMITA
IPC分类号： H03K5/153
CPC分类号： H03K5/1532 , G11B7/1263
摘要： A peak hold circuit includes an input transistor, which is provided with an input signal, and a first hold capacitor, which holds a maximum or minimum value of the input signal. A correction circuit, which corrects the hold voltage held by the first hold capacitor, includes an operational amplifier, which is supplied with the hold voltage, and a correction transistor, which is provided with an output signal of the operational amplifier. A source/emitter of the correction transistor is coupled to the operational amplifier. The peak hold circuit also includes a current detection circuit, which detects current flowing to the input transistor, and a peak current hold circuit, which holds the peak value of the current detected by the current detection circuit as a peak current and supplies the peak current to the correction transistor.
摘要翻译：峰值保持电路包括具有输入信号的输入晶体管和保持输入信号的最大值或最小值的第一保持电容器。校正由第一保持电容器保持的保持电压的校正电路包括被提供有保持电压的运算放大器和设置有运算放大器的输出信号的校正晶体管。校正晶体管的源极/发射极耦合到运算放大器。峰值保持电路还包括检测流向输入晶体管的电流的电流检测电路和将电流检测电路检测到的电流的峰值保持为峰值电流的峰值电流保持电路，并提供峰值电流到校正晶体管。

3. 发明授权

US07120416B2 Semiconductor device and receiver 有权
标题翻译：半导体器件和接收器
公开(公告)号：US07120416B2
公开(公告)日：2006-10-10
申请号：US10625569
申请日：2003-07-24
申请人： Kazuhiro Tomita
发明人： Kazuhiro Tomita
IPC分类号： H04B1/10
CPC分类号： H03J3/08 , H03J7/065
摘要： A semiconductor device for demodulating a received signal in a satisfactory manner when the frequency of the received signal deviates. The semiconductor device is used in a receiver having a reference oscillator. The semiconductor device includes a local oscillator, a PLL controller, and a comparator. The local oscillator generates a local signal having a local frequency. The PLL controller controls the local frequency in accordance with a reference signal of the reference oscillator. The comparator compares the frequency of the received signal with the frequency of the reference signal or the phase of the received signal with the phase of the reference signal to generate an error signal for correcting the local frequency in accordance with the comparison.
摘要翻译：一种用于当接收信号的频率偏离时以令人满意的方式解调接收信号的半导体器件。半导体器件用于具有参考振荡器的接收机中。半导体器件包括本地振荡器，PLL控制器和比较器。本地振荡器产生具有本地频率的本地信号。 PLL控制器根据参考振荡器的参考信号控制本地频率。比较器将接收信号的频率与参考信号的频率或接收信号的相位与参考信号的相位进行比较，以根据比较生成用于校正本地频率的误差信号。

4. 发明申请

US20100330933A1 OUTPUT CIRCUIT OF HIGH-FREQUENCY TRANSMITTER 有权
标题翻译：高频发射机的输出电路
公开(公告)号：US20100330933A1
公开(公告)日：2010-12-30
申请号：US12822651
申请日：2010-06-24
申请人： Kazuhiro TOMITA
发明人： Kazuhiro TOMITA
IPC分类号： H04B1/40
CPC分类号： H04L27/32
摘要： A transmitting and receiving device includes: a transmission circuit that transmits a signal by FM-modulating a carrier wave of the signal; an FM demodulation circuit that generates a demodulation signal by FM-demodulating the received signal; and a first filter circuit that changes a pass-band for letting the received signal pass through according to the demodulation signal, wherein the transmitting and receiving device perform a power supply line communication through the power supply line in which a signal is transmitted and received among a plurality of the transmitting and receiving devices.
摘要翻译：发送和接收设备包括：发送电路，通过对信号的载波进行FM调制来发送信号; FM解调电路，通过对所接收的信号进行FM解调来产生解调信号; 以及第一滤波器电路，其根据解调信号改变使接收信号通过的通带，其中发送和接收装置通过其中发送和接收信号的电源线执行电源线通信，多个发送和接收设备。

5. 发明申请

US20100007427A1 SWITCHING CAPACITOR GENERATION CIRCUIT 有权
标题翻译：切换电容器生成电路
公开(公告)号：US20100007427A1
公开(公告)日：2010-01-14
申请号：US12562118
申请日：2009-09-17
申请人： Kazuhiro TOMITA
发明人： Kazuhiro TOMITA
IPC分类号： H03K3/01 , H03K17/687 , H03H7/01
CPC分类号： H03B5/04 , H03H19/004
摘要： A switching capacitor generation circuit which reduces the on-resistance and parasitic capacitance of a switch element and improves the operation properties of the switch element. The switching capacitor generation circuit, which has first and second output terminals, includes a first capacitor coupled to the first output terminal, a second capacitor coupled to the second output terminal, and a single switch element coupled between the first and the second capacitors.
摘要翻译：一种开关电容器生成电路，其减小开关元件的导通电阻和寄生电容，并提高开关元件的操作性能。具有第一和第二输出端的开关电容器生成电路包括耦合到第一输出端子的第一电容器，耦合到第二输出端子的第二电容器和耦合在第一和第二电容器之间的单个开关元件。

6. 发明授权

US07622760B2 MOS type variable capacitance device 有权
标题翻译： MOS型可变电容器件
公开(公告)号：US07622760B2
公开(公告)日：2009-11-24
申请号：US11047559
申请日：2005-02-02
申请人： Takaoki Ogawa , Kazuhiro Tomita , Koju Aoki
发明人： Takaoki Ogawa , Kazuhiro Tomita , Koju Aoki
IPC分类号： H01L27/12
CPC分类号： H01L29/0684 , H01L27/0808 , H01L29/42312 , H01L29/93 , H01L29/94
摘要： An n-well is formed in a p-type semiconductor substrate. A gate insulative film is formed to the p-type semiconductor substrate and the n-well, and a gate electrode is formed on the gate insulative film. A source layer selectively diffused with n-type impurities at high concentration is formed adjacent to the gate insulative film on the surface of the p-type semiconductor substrate, the n-well and a region extending on both of them. Further, a contact layer selectively diffused with p-type impurities at high concentration is formed being spaced from the source layer. A capacitance characteristic of good linearity over a wide range relative to the inter-terminal voltage VT can be obtained by applying an inter-terminal voltage VT between the source layer and the gate electrode. A MOS type variable capacitance device capable of obtaining a characteristic of good linearity for a wide range relative to the inter-terminal voltage VT and capable of coping with the improvement of the performance of a VCO circuit, etc., as well as simple in the structure, and capable of being manufactured easily with no requirement for addition of masks and steps can be provided.
摘要翻译：在p型半导体衬底中形成n阱。对p型半导体衬底和n阱形成栅极绝缘膜，并且在栅极绝缘膜上形成栅电极。与p型半导体衬底的表面上的栅极绝缘膜相邻地形成与n型杂质高浓度选择性扩散的源极层，n阱以及在其上延伸的区域。此外，形成与源极层间隔开的与高浓度的p型杂质选择性扩散的接触层。通过在源极层和栅电极之间施加端子间电压VT，可以获得相对于端子间电压VT在宽范围内具有良好线性度的电容特性。一种MOS型可变电容器件，其能够获得相对于端子间电压VT的宽范围的良好线性特性，并且能够应对VCO电路的性能的提高等，以及简单的结构，并且能够容易地制造，而不需要添加掩模和步骤。

7. 发明授权

US07363190B2 Sensor control circuit 有权
标题翻译：传感器控制电路
公开(公告)号：US07363190B2
公开(公告)日：2008-04-22
申请号：US11723252
申请日：2007-03-19
申请人： Kazuhiro Yamashita , Kazuhiro Tomita
发明人： Kazuhiro Yamashita , Kazuhiro Tomita
IPC分类号： G06F19/00
CPC分类号： G01P15/0891 , G01P15/18 , G11B19/04
摘要： A sensor control circuit includes an acceleration sensor which detects acceleration and generates a detection signal. The sensor control circuit also includes a processing section which generates a calculation result by calculating the acceleration in accordance with the detection signal, and generates an interrupt notification. The sensor control circuit also includes an interrupt output circuit. The interrupt output circuit has a threshold value determination section which generates a detection result by determining a change condition. The change condition is determined by comparing the calculation result with the threshold value. The interrupt output circuit also has a plurality of INT terminals and a selection section. The selection section selects the detection result or the interruption notification in accordance with mode information which is set from a host CPU and sends the selected signal from the INT terminal through the associated INT terminal.
摘要翻译：传感器控制电路包括检测加速度并产生检测信号的加速度传感器。传感器控制电路还包括处理部，其通过根据检测信号计算加速度来生成计算结果，并生成中断通知。传感器控制电路还包括一个中断输出电路。中断输出电路具有阈值确定部分，其通过确定改变状况来产生检测结果。通过将计算结果与阈值进行比较来确定变化条件。中断输出电路还具有多个INT端子和选择部分。选择部分根据从主机CPU设置的模式信息来选择检测结果或中断通知，并通过相关联的INT端口从INT终端发送所选择的信号。

8. 发明申请

US20070075805A1 Phase shift circuit and phase correcting method 有权
标题翻译：相移电路和相位校正方法
公开(公告)号：US20070075805A1
公开(公告)日：2007-04-05
申请号：US11602320
申请日：2006-11-21
申请人： Kazuhiro Tomita
发明人： Kazuhiro Tomita
IPC分类号： H01P9/00
CPC分类号： H03H7/21
摘要： A phase shift circuit includes a 45° phase corrector that performs vector synthesis of signals supposed to have a 45° phase difference, out of a plurality of sets of orthogonal phase signals having an about 45° phase difference and an equal amplitude, the orthogonal phase signals in each set having undergone 90° phase correction, and outputs signals resulting from the vector synthesis, whereby a phase error between the orthogonal phase signals in the different sets is eliminated by the vector synthesis to make it possible to correct their phase difference to accurately 45°.
摘要翻译：相移电路包括：45°相位校正器，其在具有约45°相位差和相等振幅的多组正交相位信号中执行假设具有45°相位差的信号的矢量合成，正交相位每个组中的信号经过90°相位校正，并且输出由矢量合成产生的信号，由此通过矢量合成消除了不同组中的正交相位信号之间的相位误差，使得可以将它们的相位差精确地校正 45°。

9. 发明申请

US20050127411A1 Mos type variable capacitance device 有权
标题翻译： Mos型可变电容器件
公开(公告)号：US20050127411A1
公开(公告)日：2005-06-16
申请号：US11047559
申请日：2005-02-02
申请人： Takaoki Ogawa , Kazuhiro Tomita , Koju Aoki
发明人： Takaoki Ogawa , Kazuhiro Tomita , Koju Aoki
IPC分类号： H01L27/08 , H01L29/93 , H01L29/94 , H01L29/76
CPC分类号： H01L29/0684 , H01L27/0808 , H01L29/42312 , H01L29/93 , H01L29/94
摘要： An n-well is formed in a p-type semiconductor substrate. A gate insulative film is formed to the p-type semiconductor substrate and the n-well, and a gate electrode is formed on the gate insulative film. A source layer selectively diffused with n-type impurities at high concentration is formed adjacent to the gate insulative film on the surface of the p-type semiconductor substrate, the n-well and a region extending on both of them. Further, a contact layer selectively diffused with p-type impurities at high concentration is formed being spaced from the source layer. A capacitance characteristic of good linearity over a wide range relative to the inter-terminal voltage VT can be obtained by applying an inter-terminal voltage VT between the source layer and the gate electrode. A MOS type variable capacitance device capable of obtaining a characteristic of good linearity for a wide range relative to the inter-terminal voltage VT and capable of coping with the improvement of the performance of a VCO circuit, etc., as well as simple in the structure, and capable of being manufactured easily with no requirement for addition of masks and steps can be provided.
摘要翻译：在p型半导体衬底中形成n阱。对p型半导体衬底和n阱形成栅极绝缘膜，并且在栅极绝缘膜上形成栅电极。与p型半导体衬底的表面上的栅极绝缘膜相邻地形成与n型杂质高浓度选择性扩散的源极层，n阱以及在其上延伸的区域。此外，形成与源极层间隔开的与高浓度的p型杂质选择性扩散的接触层。通过在源极层和栅电极之间施加端子间电压VT，可以获得相对于端子间电压VT在宽范围内具有良好线性度的电容特性。一种MOS型可变电容器件，其能够获得相对于端子间电压VT的宽范围的良好线性特性，并且能够应对VCO电路的性能的提高等，以及简单的结构，并且能够容易地制造，而不需要添加掩模和步骤。

10. 发明授权

US5142222A Integrated circuit device having signal discrimination circuit and method of testing same 失效
标题翻译：具有信号鉴别电路的集成电路装置及其测试方法
公开(公告)号：US5142222A
公开(公告)日：1992-08-25
申请号：US789814
申请日：1991-11-12
申请人： Masahiro Tanaka , Kazuhiro Tomita , Kazumi Ogawa
发明人： Masahiro Tanaka , Kazuhiro Tomita , Kazumi Ogawa
IPC分类号： G01R31/317
CPC分类号： G01R31/31701
摘要： An integrated circuit device formed on a chip includes a pair of signal input terminals, a signal discriminating circuit having a pair of input terminals coupled to the signal input terminals, for comparing a data signal and a reference signal supplied through the input terminals and for determining whether or not the level of said data signal is higher than that of said reference signal, a pair of test signal terminals to which a predetermined voltage is applied, and a voltage dividing circuit for dividing the predetermined voltage to thereby generate a test signal to be supplied to the signal discriminating circuit through the input terminals.
摘要翻译：形成在芯片上的集成电路器件包括一对信号输入端子，信号鉴别电路，其具有耦合到信号输入端子的一对输入端子，用于比较数据信号和通过输入端子提供的参考信号，并用于确定所述数据信号的电平是否高于所述参考信号的电平，施加预定电压的一对测试信号端子以及用于划分所述预定电压的分压电路，从而产生测试信号为通过输入端子提供给信号鉴别电路。

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