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1. 发明授权

US11430635B2 Precise plasma control system 有权
公开(公告)号：US11430635B2
公开(公告)日：2022-08-30
申请号：US16937948
申请日：2020-07-24
申请人： Eagle Harbor Technologies, Inc.
发明人： Timothy Ziemba , Kenneth Miller , James Prager , Kevin Muggli , Eric Hanson
IPC分类号： H01J37/32 , H03K3/57 , H03K3/36 , H03K17/56
摘要： Some embodiments include a plasma system comprising: a plasma chamber, an RF plasma generator, a bias generator, and a controller. The RF plasma generator may be electrically coupled with the plasma chamber and may produce a plurality of RF bursts, each of the plurality of RF bursts including RF waveforms, each of the plurality of RF bursts having an RF burst turn on time and an RF burst turn off time. The bias generator may be electrically coupled with the plasma chamber and may produce a plurality of bias bursts, each of the plurality of bias bursts including bias pulses, each of the plurality of bias bursts having an bias burst turn on time and an bias burst turn off time. In some embodiments the controller is in communication with the RF plasma generator and the bias generator that controls the timing of various bursts or waveforms.

2. 发明申请

US20220224317A1 HIGH VOLTAGE PRE-PULSING 有权
公开(公告)号：US20220224317A1
公开(公告)日：2022-07-14
申请号：US17707902
申请日：2022-03-29
申请人： EAGLE HARBOR TECHNOLOGIES, INC.
发明人： Kenneth E. Miller , James R. Prager , Ilia Slobodov , Julian F. Picard
IPC分类号： H03K3/57 , H03K17/16 , H02M11/00 , H03K3/53 , H02M3/158 , H03K3/36 , H03K17/56
摘要： Some embodiments of the invention include a pre-pulse switching system. The pre-pulsing switching system may include: a power source configured to provide a voltage greater than 100 V; a pre-pulse switch coupled with the power source and configured to provide a pre-pulse having a pulse width of Tpp; and a main switch coupled with the power source and configured to provide a main pulse such that an output pulse comprises a single pulse with negligible ringing. The pre-pulse may be provided to a load by closing the pre-pulse switch while the main switch is open. The main pulse may be provided to the load by closing the main switch after a delay Tdelay after the pre-pulse switch has been opened.

3. 发明授权

US11004660B2 Variable output impedance RF generator 有权
公开(公告)号：US11004660B2
公开(公告)日：2021-05-11
申请号：US16697173
申请日：2019-11-26
申请人： Eagle Harbor Technologies, Inc.
发明人： James Prager , Timothy Ziemba
IPC分类号： H01J37/32 , H03K17/56 , H03K3/57 , H03K3/36
摘要： Various RF plasma systems are disclosed that do not require a matching network. In some embodiments, the RF plasma system includes an energy storage capacitor; a switching circuit coupled with the energy storage capacitor, the switching circuit producing a plurality of pulses with a pulse amplitude and a pulse frequency, the pulse amplitude being greater than 100 volts; a resonant circuit coupled with the switching circuit. In some embodiments, the resonant circuit includes: a transformer having a primary side and a secondary side; and at least one of a capacitor, an inductor, and a resistor. In some embodiments, the resonant circuit having a resonant frequency substantially equal to the pulse frequency, and the resonant circuit increases the pulse amplitude to a voltage greater than 2 kV.

4. 发明授权

US09912320B2 Exponentially scaling switched capacitor 有权
公开(公告)号：US09912320B2
公开(公告)日：2018-03-06
申请号：US15180442
申请日：2016-06-13
申请人： The Hong Kong University of Science and Technology
发明人： Howard Cam Luong , Zhiqiang Huang
IPC分类号： H03J3/18 , H03B5/12 , H03H7/00 , H03K3/36
CPC分类号： H03J3/185 , H03H7/004 , H03H7/24 , H03K3/36 , H03L7/0991 , H03L2207/50
摘要： An exponentially-scaling switched impedance circuit includes: two or more impedance scaling circuits, wherein each impedance scaling circuit comprises: an input port; an output port; and a switched impedance circuit connected in parallel to the output port. Each impedance scaling circuit is configured to provide an effective impedance at the input port corresponding to a scaled-down version of the exponentially-scaling switched impedance circuit. The two or more impedance scaling circuits are connected in a cascade such that an input of an impedance scaling circuit is connected to an output of a previous impedance scaling circuit and/or an output of the impedance scaling circuit is connected to an input of a next impedance scaling circuit.

5. 发明申请

US20180061741A1 SEMICONDUCTOR DIE PACKAGE AND METHOD OF PRODUCING THE PACKAGE 有权
公开(公告)号：US20180061741A1
公开(公告)日：2018-03-01
申请号：US15686015
申请日：2017-08-24
申请人： IMEC VZW
发明人： Eric Beyne
IPC分类号： H01L23/48 , H01L27/105 , H03K3/36
CPC分类号： H01L23/481 , H01L21/561 , H01L21/568 , H01L23/3135 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L27/1052 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/73209 , H01L2224/73253 , H01L2224/73267 , H01L2224/81005 , H01L2224/81815 , H01L2224/83005 , H01L2224/92124 , H01L2224/97 , H01L2924/1431 , H01L2924/1434 , H01L2924/1436 , H01L2924/15192 , H01L2924/15311 , H03K3/36 , H01L2224/81 , H01L2224/83
摘要： A package including a first die embedded in a reconstructed wafer obtainable by the known FO-WLP or eWLB technologies is disclosed. In one aspect and in addition to the first die, a Through Substrate Via insert is embedded in the wafer, the TSV insert being a separate element, possibly a silicon die with metal filled vias interconnecting contacts on the front and back sides of the insert. A second die is mounted on the back side of the substrate, with contacts on the second die in electrical connection with the TSV insert's contacts on the back side of the substrate. On the front side of the substrate, a lateral connecting device is mounted which interconnects the TSV insert's contacts on the front side of the substrate to contacts on the front side of the first die. The lateral connecting device and the TSV insert thereby effectively interconnect the contacts on the first and second dies. In another aspect, the lateral connecting device is mounted on a redistribution layer on the front side of the substrate, as it is known from FO-WLP technology.

6. 发明授权

US09831878B2 Semiconductor device and selector circuit 有权
公开(公告)号：US09831878B2
公开(公告)日：2017-11-28
申请号：US15291677
申请日：2016-10-12
申请人： LAPIS Semiconductor Co., Ltd.
发明人： Shigeru Nagatomo
IPC分类号： H03K19/0185 , H01L27/092 , H03K3/36 , H03K3/356 , H03K17/22 , H01L29/06
CPC分类号： H03K19/018521 , H01L27/092 , H01L29/0684 , H03K3/356113 , H03K3/356165 , H03K3/36 , H03K17/223
摘要： A semiconductor device includes a setting circuit and a reset circuit. The setting circuit includes a latch circuit having first and second inverters driven by a first power voltage whose level is fixed and a first transistor which is switched between an ON state and an OFF state on the basis of a level of a second power voltage whose level varies depending on a surrounding environment, and sets data corresponding to a reference voltage to the latch circuit in response to the first transistor being switched to the ON state. The reset circuit includes an N-type second transistor connected to an output of the first inverter and an input of the second inverter. The second transistor sets data corresponding to the reference voltage to the latch circuit in response to the second voltage being equal to or lower than a predetermined voltage value.

7. 发明申请

US20150215051A1 MIXER AND MIXING METHOD 有权
标题翻译：混合和混合方法
公开(公告)号：US20150215051A1
公开(公告)日：2015-07-30
申请号：US14580765
申请日：2014-12-23
申请人： GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
发明人： Minjae LEE , Dongju LEE
IPC分类号： H04B15/00 , H04L27/152 , H04B15/06 , H03K3/36 , H03K17/56
CPC分类号： H04B15/005 , H03D7/1441 , H03K17/56 , H04B15/06 , H04L27/152
摘要： Disclosed herein is a mixer. The mixer may include an MLO switching unit configured to include at least three MLO switches provided in odd numbers and configured to branch a signal from an input stage and to receive respective MLO signals and an LO switching unit configured to include pairs of LO switches connected in parallel to output sides of the MLO switches, wherein each of the pairs of LO switches corresponds to each of the MLO switches. Each of the pairs of LO switches is connected to the positive and negative intermediate frequency (IF) output sides so that the output sides of each of the pairs of LO switches alternately apply output signals to the positive and negative IF output sides when LO signals are sequentially input to each of the pairs of LO switches.
摘要翻译：本文公开了一种混合器。混频器可以包括MLO开关单元，其被配置为包括以奇数提供的至少三个MLO开关，并且被配置为分支来自输入级的信号并且接收相应的MLO信号，并且LO切换单元被配置为包括连接在一起的LO开关对平行于MLO开关的输出侧，其中每对LO开关对应于每个MLO开关。 LO开关对中的每一对连接到正和负中频（IF）输出侧，使得当LO信号为...时，每对LO开关的输出侧交替地将输出信号施加到正和负IF输出侧顺序输入到每对LO开关。

8. 发明申请

US20140232480A1 CLOCK APPARATUS 审中-公开
标题翻译：时钟设备
公开(公告)号：US20140232480A1
公开(公告)日：2014-08-21
申请号：US13769829
申请日：2013-02-19
申请人： ISSC TECHNOLOGIES CORP.
发明人： Yi-Lung Chen
IPC分类号： H03K3/36
CPC分类号： H03K3/36 , H03K3/03
摘要： The invention provides a clock apparatus includes a clock source, a first resistor, a diode, an amplifier, and an oscillator. The current source provides a current, and the current has a first temperature coefficient. The first resistor has a first end, and the first end receives the current. The anode of the diode is coupled to a second end of the first resistor, the cathode of the diode is coupled to a reference ground. The diode has a second temperature coefficient. The amplifier receives a power source. The amplifier generates an output voltage according to the power source and a voltage on the first end of the first resistor. The oscillator receives the output voltage to be an operating power. Wherein, the first and second temperature coefficients are complementary.
摘要翻译：本发明提供一种时钟装置，包括时钟源，第一电阻器，二极管，放大器和振荡器。电流源提供电流，电流具有第一温度系数。第一电阻具有第一端，第一端接收电流。二极管的阳极耦合到第一电阻器的第二端，二极管的阴极耦合到参考地。二极管具有第二温度系数。放大器接收电源。放大器根据电源产生输出电压，并在第一电阻的第一端产生电压。振荡器接收输出电压为工作电源。其中，第一和第二温度系数是互补的。

9. 发明申请

US20140210564A1 RELAXATION OSCILLATOR WITH SELF-BIASED COMPARATOR 有权
标题翻译：具有自偏置比较器的松弛振荡器
公开(公告)号：US20140210564A1
公开(公告)日：2014-07-31
申请号：US13753544
申请日：2013-01-30
申请人： Anand Kumar Sinha , Sanjay K. Wadhwa
发明人： Anand Kumar Sinha , Sanjay K. Wadhwa
IPC分类号： H03K3/36
CPC分类号： H03K3/0231
摘要： A relaxation oscillator for generating an output clock signal includes an RC circuit, a self-biased comparator stage, and a logic circuit. The RC circuit generates first and second comparator input signals that are provided to the self-biased comparator stage. The self-biased comparator stage includes first and second input stages and a voltage reference circuit. Each of the first and second input stages in conjunction with the voltage reference circuit forms a comparator, i.e., first and second comparators corresponding to the first and second input stages, respectively. The self-biased comparator stage generates first and second comparator output signals, based on the first and second comparator input signals. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.
摘要翻译：用于产生输出时钟信号的放大振荡器包括RC电路，自偏置比较器级和逻辑电路。 RC电路产生提供给自偏置比较器级的第一和第二比较器输入信号。自偏置比较器级包括第一和第二输入级和电压参考电路。第一和第二输入级中的每一个结合电压参考电路分别形成比较器，即分别对应于第一和第二输入级的第一和第二比较器。自偏置比较器级基于第一和第二比较器输入信号产生第一和第二比较器输出信号。第一和第二比较器输出信号被提供给产生输出时钟信号的逻辑电路。

10. 发明申请

US20130162323A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20130162323A1
公开(公告)日：2013-06-27
申请号：US13767694
申请日：2013-02-14
申请人： Kabushiki Kaisha Toshiba
发明人： Chen Kong TEH
IPC分类号： H03K3/36
CPC分类号： H03K3/356139
摘要： In a clear period, transistors NT38 and PT38 turn on and state retention nodes HQ and H/Q are cleared to an L level and an H level, respectively. In this clear period, a transistor NT21 is off. Consequently, a precharge node PS maintains itself at an H level. Thus, transistors PT31 and NT32 are off, thereby preventing a short circuit from occurring in a clear period. A short circuit is also prevented from occurring in a preset period.
摘要翻译：在一个清晰的时间段，晶体管NT38和PT38导通，状态保持节点HQ和H / Q分别被清除为L电平和H电平。在这个清晰的时间段内，晶体管NT21截止。因此，预充电节点PS将自身维持在H电平。因此，晶体管PT31和NT32截止，从而防止在清除时段内发生短路。也可以防止在预设期间发生短路。

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