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1. 发明授权

US07131035B2 Serial bus host controller diagnosis 有权
标题翻译：串行总线主机控制器诊断
公开(公告)号：US07131035B2
公开(公告)日：2006-10-31
申请号：US10283612
申请日：2002-10-30
申请人： Dale E. Gulick , Siegfried Kay Hesse
发明人： Dale E. Gulick , Siegfried Kay Hesse
IPC分类号： G06F11/00
CPC分类号： G06F11/26
摘要： A diagnosis mechanism for host controllers such as USB (Universal Serial Bus) host controllers is provided. The host controller has a register set that comprises at least one host controller capability register storing data indicative of operational capabilities of the host controller, and at least one host controller operational register storing data for controlling the operation of the host controller. The at least one host controller capability register stores data that is indicative of available diagnostic modes that the host controller can enter. The at least one host controller operational register stores diagnosis data for controlling the operation of the USB host controller in diagnostic modes. This diagnosis mechanism may improve the reliability of the host controller operation.
摘要翻译：提供了诸如USB（通用串行总线）主机控制器的主机控制器的诊断机制。主机控制器具有寄存器集合，其包括至少一个主机控制器能力寄存器，其存储指示主机控制器的操作能力的数据，以及存储用于控制主机控制器的操作的数据的至少一个主控制器操作寄存器。至少一个主机控制器能力寄存器存储指示主机控制器可以进入的可用诊断模式的数据。所述至少一个主机控制器操作寄存器存储用于以诊断模式控制所述USB主机控制器的操作的诊断数据。该诊断机制可以提高主机控制器操作的可靠性。

2. 发明授权

US07194583B2 Controlling the replacement of prefetched descriptors in a cache 有权
标题翻译：控制高速缓存中预取描述符的替换
公开(公告)号：US07194583B2
公开(公告)日：2007-03-20
申请号：US10464966
申请日：2003-06-19
申请人： Siegfried Kay Hesse , Dale E. Gulick
发明人： Siegfried Kay Hesse , Dale E. Gulick
IPC分类号： G06F12/00 , G06F12/12
CPC分类号： G06F12/121
摘要： A host controller such as a USB host controller in a southbridge, and a corresponding operation method are provided. The host controller comprises a descriptor fetch unit that is adapted to send out requests for descriptors and receive descriptors in reply to the requests. The descriptors are data structures for describing attributes of the data transfer to and from the devices controlled by the host controller. The host controller further comprises a descriptor cache that is adapted to store prefetched descriptors. The descriptor cache is further adapted to store individual replacement control values for at least a part of the stored prefetched descriptors. The host controller is arranged to replace a stored prefetched descriptor in the descriptor cache by a newly prefetched descriptor based on the replacement control value that is associated with the stored prefetched descriptor. The replacement technique may improve the overall efficiency of the host controller operation.
摘要翻译：提供了诸如南桥的USB主机控制器的主机控制器以及相应的操作方法。主机控制器包括描述符提取单元，其适于发送对描述符的请求并且接收描述符以回复请求。描述符是用于描述从主机控制器控制的设备传输数据的属性的数据结构。主机控制器还包括适于存储预取描述符的描述符高速缓存。所述描述符缓存进一步适于存储所存储的预取描述符的至少一部分的各个替换控制值。主机控制器被设置为基于与所存储的预取描述符相关联的替换控制值，用新的预取描述符替换描述符高速缓存中存储的预取描述符。替代技术可以提高主机控制器操作的整体效率。

3. 发明授权

US06990550B2 Transaction duration management in a USB host controller 有权
公开(公告)号：US06990550B2
公开(公告)日：2006-01-24
申请号：US10283555
申请日：2002-10-30
申请人： Siegfried Kay Hesse , Dale E. Gulick
发明人： Siegfried Kay Hesse , Dale E. Gulick
IPC分类号： G06F13/20 , H04J3/16
CPC分类号： G06F13/1605
摘要： A USB (Universal Serial Bus) host controller, a corresponding integrated circuit chip, a computer system and an operation method are provided for handling the data traffic between at least one USB device and the computer system having system memory. A transaction processing unit processes transactions to or from the at least one USB device. Further, a transaction duration management unit is provided for determining estimated duration values of the transactions. The transaction processing unit is adapted to process the transactions dependent on the estimated duration values. A descriptor-to-transaction converter may be provided, and the prefetched mechanism may be made dependent on a threshold value relating to the estimated duration values.

4. 发明授权

US06944725B2 Reciprocally adjustable dual queue mechanism 失效
标题翻译：相互可调的双排队机制
公开(公告)号：US06944725B2
公开(公告)日：2005-09-13
申请号：US10283733
申请日：2002-10-30
申请人： Siegfried Kay Hesse , Dale E. Gulick
发明人： Siegfried Kay Hesse , Dale E. Gulick
IPC分类号： G06F3/06 , G06F12/00 , G06F13/00 , G06F13/38
CPC分类号： G06F13/385 , G06F3/0601 , G06F2003/0691 , G06F2213/0042
摘要： A data storage mechanism is provided where a plurality of data items are stored in a plurality of register elements. Each registered element is capable of storing at least one data item. The plurality of register elements is arranged to form a sequence of register elements. First data is stored in a first part of the sequence and second data is stored in a second part of the sequence. The first part and the second part are of variable lengths with the sum of the variable lengths being equal to the lengths of the sequence of register elements. Thus, a double-ended queue mechanism is provided which may be used to store data of different type or data which is either scheduled periodically or asynchronously. The mechanism may be used in a USB 2.0 compliant host controller.
摘要翻译：提供了一种数据存储机制，其中多个数据项被存储在多个寄存器元件中。每个注册的元素能够存储至少一个数据项。多个寄存器元件被布置成形成寄存器元件的序列。第一数据存储在序列的第一部分中，第二数据被存储在序列的第二部分中。第一部分和第二部分是可变长度，其可变长度之和等于寄存器元件序列的长度。因此，提供了一种双端口队列机制，其可以用于存储周期性地或异步地调度的不同类型或数据的数据。该机制可用于兼容USB 2.0的主机控制器。

5. 发明授权

US06823403B2 DMA mechanism for high-speed packet bus 有权
标题翻译： DMA机制用于高速分组总线
公开(公告)号：US06823403B2
公开(公告)日：2004-11-23
申请号：US10184407
申请日：2002-06-27
申请人： Dale E. Gulick , Siegfried Kay Hesse
发明人： Dale E. Gulick , Siegfried Kay Hesse
IPC分类号： G06F1328
CPC分类号： G06F12/0879 , G06F13/28 , H04B7/0822
摘要： A DMA (Direct Memory Access) mechanism is provided that may be of improved performance in particular in connection with high-speed packet buses. A transmit DMA engine for outputting read requests for a memory interface and receiving requested data from the memory interface, comprises a data transfer initiating unit for outputting first address data identifying a first memory range. Further, a boundary alignment unit is provided for generating second address data using the first address data, where the second address data identifies a second memory range that differs from the first memory range in at least one boundary. Further a corresponding boundary alignment may be done in a receive DMA engine. The DMA mechanism may be performed in a USB-2 host controller that has HyperTransport capabilities.
摘要翻译：提供了DMA（直接存储器访问）机制，其可以具有改进的性能，特别是与高速分组总线相关。一种用于输出对存储器接口的读取请求并从存储器接口接收所请求的数据的发送DMA引擎，包括用于输出识别第一存储器范围的第一地址数据的数据传输启动单元。此外，提供边界对齐单元，用于使用第一地址数据生成第二地址数据，其中第二地址数据标识与至少一个边界中的第一存储器范围不同的第二存储器范围。此外，可以在接收DMA引擎中进行相应的边界对准。 DMA机制可以在具有HyperTransport功能的USB-2主机控制器中执行。

6. 发明授权

US08392777B2 Centralized MBIST failure information 有权
标题翻译：集中MBIST故障信息
公开(公告)号：US08392777B2
公开(公告)日：2013-03-05
申请号：US12549164
申请日：2009-08-27
申请人： Wei-Yu Chen , Kevin B. Badgett , Siegfried Kay Hesse , Timothy J. Wood
发明人： Wei-Yu Chen , Kevin B. Badgett , Siegfried Kay Hesse , Timothy J. Wood
IPC分类号： G01R31/28
CPC分类号： G11C29/44 , G11C29/4401 , G11C2029/0401 , G11C2029/1208 , G11C2029/4402
摘要： Failure and repair information collected during self-testing of arrays in an integrated circuit is stored in a centralized array in the integrated circuit. In that way, a centralized array can be read out to provide failure and repair information on the arrays in the integrated circuit rather than having to read from each array. In addition, the failure and repair information may also be stored in the array under test for certain of the arrays.
摘要翻译：在集成电路中的阵列自检期间收集的故障和修复信息存储在集成电路中的集中式阵列中。以这种方式，可以读取集中式阵列，以提供集成电路中阵列的故障和修复信息，而不必从每个阵列读取。此外，故障和修复信息也可能存储在被测阵列中的某些阵列中。

7. 发明授权

US07225288B2 Extended host controller test mode support for use with full-speed USB devices 有权
标题翻译：扩展的主机控制器测试模式支持全速USB设备使用
公开(公告)号：US07225288B2
公开(公告)日：2007-05-29
申请号：US10324782
申请日：2002-12-20
申请人： Stefan Schulze , Siegfried Kay Hesse
发明人： Stefan Schulze , Siegfried Kay Hesse
IPC分类号： G06F13/20 , G06F11/00 , G01R31/28
CPC分类号： G06F11/267
摘要： An extended host controller test mode support is provided. In the example of USB host controllers, an enhanced host controller is provided to control the high-speed traffic. Further at least one companion host controller controls the full-speed and/or low-speed traffic. The enhanced host controller comprises a test circuit for controlling a USB transceiver macrocell to perform full-speed and/or low-speed test functions. The test functions may include a test-J function, a test-K function, a single-ended-zero test function, and the sending of test patterns.
摘要翻译：提供扩展的主机控制器测试模式支持。在USB主机控制器的例子中，提供了增强的主机控制器来控制高速流量。此外，至少一个伴随主机控制器控制全速和/或低速业务。增强的主机控制器包括用于控制USB收发器宏单元以执行全速和/或低速测试功能的测试电路。测试功能可以包括测试J功能，测试K功能，单端零测试功能和发送测试模式。

8. 发明申请

US20110055644A1 CENTRALIZED MBIST FAILURE INFORMATION 有权
标题翻译：集中MBIST失败信息
公开(公告)号：US20110055644A1
公开(公告)日：2011-03-03
申请号：US12549164
申请日：2009-08-27
申请人： Wei-Yu Chen , Kevin B. Badgett , Siegfried Kay Hesse , Timothy J. Wood
发明人： Wei-Yu Chen , Kevin B. Badgett , Siegfried Kay Hesse , Timothy J. Wood
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/44 , G11C29/4401 , G11C2029/0401 , G11C2029/1208 , G11C2029/4402
摘要： Failure and repair information collected during self-testing of arrays in an integrated circuit is stored in a centralized array in the integrated circuit. In that way, a centralized array can be read out to provide failure and repair information on the arrays in the integrated circuit rather than having to read from each array. In addition, the failure and repair information may also be stored in the array under test for certain of the arrays.
摘要翻译：在集成电路中的阵列自检期间收集的故障和修复信息存储在集成电路中的集中式阵列中。以这种方式，可以读取集中式阵列，以提供集成电路中阵列的故障和修复信息，而不必从每个阵列读取。此外，故障和修复信息也可能存储在被测阵列中的某些阵列中。

9. 发明授权

US06798067B2 Switching metal line configurations in metal layer structures 失效
标题翻译：在金属层结构中切换金属线配置
公开(公告)号：US06798067B2
公开(公告)日：2004-09-28
申请号：US10327157
申请日：2002-12-20
申请人： Siegfried Kay Hesse
发明人： Siegfried Kay Hesse
IPC分类号： H01L2348
CPC分类号： H01L23/544 , H01L23/5226 , H01L2223/5444 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a metal layer structure and a corresponding integrated circuit chip are provided, wherein the integrated circuit chip comprises metal layers and via holes. The via holes electrically connect a metal line of one metal layer with a metal line of another metal layer. The metal lines and via holes form a signal path that electrically connects a first tap with a second tap. The metal lines in each metal layer are arranged in a first predefined configuration. There is for each metal layer a second predefined configuration that arranges the metal lines in the metal layer to form, together with the via holes and the metal lines in the other metal layers, a modified signal path that electrically connects the first tap with a third tap. This technique is particularly useful for storing revision identification data.
摘要翻译：提供一种制造金属层结构的方法和相应的集成电路芯片，其中集成电路芯片包括金属层和通孔。通孔将一个金属层的金属线与另一金属层的金属线电连接。金属线和通孔形成将第一分接头与第二分接头电连接的信号路径。每个金属层中的金属线以第一预定构型排列。每个金属层具有第二预定义构造，其将金属线布置在金属层中，以与其他金属层中的通孔和金属线一起形成修改的信号路径，其将第一分接头与第三接头电连接点击。该技术对于存储修订标识数据特别有用。

10. 发明授权

US07653845B2 Test algorithm selection in memory built-in self test controller 有权
标题翻译：内存测试控制器内置测试算法选择
公开(公告)号：US07653845B2
公开(公告)日：2010-01-26
申请号：US11484157
申请日：2006-07-11
申请人： Siegfried Kay Hesse , Markus Seuring , Thomas Herrmann
发明人： Siegfried Kay Hesse , Markus Seuring , Thomas Herrmann
IPC分类号： G11C29/00
CPC分类号： G11C29/16
摘要： An integrated circuit chip is provided that comprises on-chip memory and test circuitry. The test circuitry is configured to perform operational testing of the on-chip memory. The test circuitry comprises a controller which is configured to perform a selection out of a plurality of test algorithms to perform the operational testing. The plurality of test algorithms includes a fault detection test algorithm to perform operational testing of the on-chip memory in order to detect whether or not there is a memory fault, without locating the memory fault. The plurality of test algorithms further includes a fault location test algorithm to perform operational testing of the on-chip memory in order to detect and locate a memory fault. Further, a method to perform a memory built-in self test and an MBIST (Memory Built-In Self Test) control circuit template are provided.
摘要翻译：提供了一种集成电路芯片，其包括片上存储器和测试电路。测试电路被配置为执行片上存储器的操作测试。测试电路包括控制器，其被配置为执行从多个测试算法中的选择以执行操作测试。多个测试算法包括故障检测测试算法，以对片内存储器进行操作测试，以便检测是否存在存储器故障，而不定位存储器故障。多个测试算法还包括故障定位测试算法，以执行片上存储器的操作测试，以便检测和定位存储器故障。此外，提供了执行存储器内置自检和MBIST（存储器内置自检）控制电路模板的方法。

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