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1. 发明授权

US08607443B2 Method of manufacturing a connector chip 有权
标题翻译：制造连接器芯片的方法
公开(公告)号：US08607443B2
公开(公告)日：2013-12-17
申请号：US12827755
申请日：2010-06-30
申请人： Shinji Okamoto , Katsumi Takeuchi , Yutaka Nomura
发明人： Shinji Okamoto , Katsumi Takeuchi , Yutaka Nomura
IPC分类号： H05K3/36
CPC分类号： H05K3/368 , H01R12/52 , H05K3/3442 , H05K2201/10378 , Y10T29/49126
摘要： A method of manufacturing a connector chip includes preparing a plate-like insulating substrate material with a plurality of through hole rows arranged therein; forming a plurality of first and second base layers on opposite surfaces of the insulating substrate material; forming insulating layers between each two adjoining first base layers and between each two adjoining second base layers; forming third base layers on the one side over edge portions of the first base layers, internal surfaces of the through holes, and edge portions of the second base layers; forming fourth base layers on the other side over edge portions of the first base layers, the internal surfaces of the through holes, and edge portions of the second base layers; cutting the insulating substrate material along a middle of each of the through hole rows; and forming one or more plated layers over the first to fourth base layers.
摘要翻译：一种制造连接器芯片的方法包括制备其中布置有多个通孔列的板状绝缘基板材料; 在所述绝缘基板材料的相对表面上形成多个第一和第二基底层; 在每个两个邻接的第一基底层之间和每个两个相邻的第二基底层之间形成绝缘层; 在所述第一基底层的边缘部分，所述通孔的内表面和所述第二基底层的边缘部分的一侧上形成第三基底层; 在所述第一基底层的边缘部分的另一侧上形成第四基底层，所述通孔的内表面和所述第二基底层的边缘部分; 沿着每个通孔列的中间切割绝缘基板材料; 以及在所述第一至第四基底层上形成一个或多个镀层。

2. 发明申请

US20110080251A1 CHIP-LIKE ELECTRIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：芯片式电气元件及其制造方法
公开(公告)号：US20110080251A1
公开(公告)日：2011-04-07
申请号：US12995867
申请日：2009-06-01
申请人： Katsumi Takeuchi , Yutaka Nomura , Hiroyuki Kurokawa
发明人： Katsumi Takeuchi , Yutaka Nomura , Hiroyuki Kurokawa
IPC分类号： H01C1/034 , H05K3/10
CPC分类号： H01C7/003 , H01C1/06 , H01C17/006 , H01C17/06506 , Y10T29/49155
摘要： A chip-like electric component such as a chip resistor is provided, which is easy to manufacture and in which cracks or fractures of an insulating substrate are unlikely to occur. A pair of surface electrodes 21, 23 are formed so that thicknesses of the pair of surface electrodes increase from a resistor layer 13 toward end portions 30 of an insulating substrate 29 in a direction in which the pair of surface electrodes 21, 23 are arranged. A plating reservoir S is formed between one of the surface electrodes 21, 23 and an insulating protective layer 15. When forming at least one plated layer 33, a plated metal pools in the plating reservoir S. The at least one plated layer 33 may work to reduce to some extent a height difference between a soldering electrode portion 21, 23, 27, 33 and the insulating protective layer 15.
摘要翻译：提供了诸如片状电阻器的芯片状电气部件，其易于制造，并且其中不可能发生绝缘基板的裂纹或断裂。形成一对表面电极21,23，使得一对表面电极的厚度从电阻层13朝向绝缘基板29的端部配置在一对表面电极21,23的方向上增加。在一个表面电极21,23和绝缘保护层15之间形成电镀槽S.当形成至少一个镀层33时，电镀金属池在电镀槽S中。至少一个镀层33可以工作以在一定程度上减少焊接电极部分21,23,27,33与绝缘保护层15之间的高度差。

3. 发明申请

US20070072454A1 CONNECTOR CHIP AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：连接器芯片及其制造方法
公开(公告)号：US20070072454A1
公开(公告)日：2007-03-29
申请号：US10595809
申请日：2004-11-12
申请人： Shinji Okamoto , Katsumi Takeuchi , Yutaka Nomura
发明人： Shinji Okamoto , Katsumi Takeuchi , Yutaka Nomura
IPC分类号： H01R4/58
CPC分类号： H05K3/368 , H01R12/52 , H05K3/3442 , H05K2201/10378 , Y10T29/49126
摘要： The present invention provides a connector chip capable of preventing electrical shorting between adjoining electrodes and also capable of readily connecting a plurality of electrodes on a first circuit substrate and a plurality of electrodes on a second circuit substrate without using a dedicated mounting device or the like. A plurality of conductive paths 5 are formed on an outer periphery surface constituted by continuous four surfaces 9A to 9D of an insulating substrate 3 including six surfaces of the surfaces 9A to 9D and surfaces 9E and 9F. Each of the conductive paths 5 goes round on the outer periphery surface. The conductive paths 5 are formed on the outer periphery surface at a predetermined interval in an opposing direction in which the remaining two surfaces 9E and 9F are opposing to each other. Each of insulating layers 7 having a property of repelling molten solder is formed between portions of each two adjoining conductive paths located on a pair of the surfaces 9A and 9B. The width of a conductive-path-formed portion 3A with a conductive path 5 formed thereon, orthogonal to a center line C is formed to be smaller than the width of a conductive-path-unformed portion 3B with no conductive path 5 formed thereon, orthogonal to the center line C.
摘要翻译：本发明提供一种连接器芯片，其能够防止相邻电极之间的电短路，并且还能够容易地连接第一电路基板上的多个电极和第二电路基板上的多个电极，而不使用专用的安装装置等。在由包括表面9A至9D的六个表面和表面9E和9F的绝缘基板3的连续的四个表面9A至9D构成的外周面上形成多个导电路径5。导电路径5在外周表面上圆周。导电路径5以与剩下的两个表面9E和9F相对的相反方向以预定的间隔形成在外周表面上。具有排斥熔融焊料性质的绝缘层7中的每一个形成在位于一对表面9A和9B上的每个两个邻接导电路径的部分之间。具有导电性的导电路径形成部分3A的宽度形成在其上的与中心线C正交的路径5形成为小于没有形成在其上的导电路径5的与中心线C正交的导电路径未成形部分3B的宽度。

4. 发明授权

US07825769B2 Terminal structure of chiplike electric component 有权
标题翻译： chiplike电气元件的端子结构
公开(公告)号：US07825769B2
公开(公告)日：2010-11-02
申请号：US12088268
申请日：2006-09-27
申请人： Yutaka Nomura , Katsumi Takeuchi
发明人： Yutaka Nomura , Katsumi Takeuchi
IPC分类号： H01C1/012
CPC分类号： H01C1/142 , H01C1/012 , H01C1/148 , H01C7/003 , H01C17/006
摘要： A terminal structure of a chip-like electric component capable of blocking entry of electromigration-causing factors through an insulating resin layer in the vicinity of the peak of a raised portion of an electrical element forming layer is obtained. A metal-glaze-based front electrode 103 containing silver is provided on a surface of an insulating ceramic substrate 101. A resistor layer 107 electrically connected to the front electrode 103 is provided on the substrate surface. A glass layer 109a is provided to completely cover a surface of the resistor layer 107 as well as a surface of an end portion of the resistor layer 107 and also to partially cover the front electrode 103. An insulating resin layer 109b is provided to cover a surface of the glass layer 109a as well as a surface of at least an end portion of the glass layer 109a and to partially cover the front electrode 103. A conductive layer 117 made of a resin-based conductive paint is provided to extend over the surface of the front electrode 103 and an portion of the insulating resin layer 109b in the vicinity of the peak of raised end portion of the insulating resin layer 109b. The resin-based conductive paint is made by kneading particulate conductive silver powder and scale-like conductive silver powder into an epoxy-based insulating resin paint.
摘要翻译：可以获得能够通过电气元件形成层的凸起部分的峰附近的绝缘树脂层阻挡电迁移因子的芯片状电气部件的端子结构。在绝缘陶瓷基板101的表面上设置有含有银的金属釉基前电极103.电连接到前电极103的电阻层107设置在基板表面上。提供玻璃层109a以完全覆盖电阻层107的表面以及电阻层107的端部的表面，并且还部分覆盖前电极103.设置绝缘树脂层109b以覆盖玻璃层109a的表面以及玻璃层109a的至少一个端部的表面，并且部分地覆盖前电极103.设置由树脂基导电涂料制成的导电层117以在表面上延伸的绝缘树脂层109b的顶端附近的绝缘树脂层109b的一部分。树脂系导电性涂料通过将颗粒状导电性银粉末和鳞状导电性银粉末混合成环氧系绝缘树脂涂料而制成。

5. 发明授权

US5212247A Polypropylene resin compositions of high syndiotacticity and preparation process thereof 失效
标题翻译：高分子量聚丙烯的聚丙烯树脂组合物及其制备方法
公开(公告)号：US5212247A
公开(公告)日：1993-05-18
申请号：US533757
申请日：1990-06-06
申请人： Tadashi Asanuma , Tetsunosuke Shiomura , Nobutaka Uchikawa , Tutomu Iwatani , Katsumi Takeuchi
发明人： Tadashi Asanuma , Tetsunosuke Shiomura , Nobutaka Uchikawa , Tutomu Iwatani , Katsumi Takeuchi
IPC分类号： C08F2/44 , C08F297/08 , C08L23/12 , C08L23/14 , C08L23/16
CPC分类号： C08F297/083 , C08L23/12 , C08L2207/12 , C08L23/14 , C08L23/142 , C08L23/16 , Y10S526/943
摘要： Disclosed herein is a polypropylene resin composition of a high syndiotacticity comprising a substantial homopolymer of propylene, in which the ratio of the intensity of the peak attributable to the syndiotactic pentad bonds to the sum of the intensities of all the peaks attributable to the methyl groups in the spectrum of the methyl groups measured by .sup.13 C-NMR is 0.7 or more, and a copolymer of ethylene and propylene, and a preparation process thereof.

6. 发明授权

US08193899B2 Chip-like electric component and method for manufacturing the same 有权
标题翻译：片状电气元件及其制造方法
公开(公告)号：US08193899B2
公开(公告)日：2012-06-05
申请号：US12995867
申请日：2009-06-01
申请人： Katsumi Takeuchi , Yutaka Nomura , Hiroyuki Kurokawa
发明人： Katsumi Takeuchi , Yutaka Nomura , Hiroyuki Kurokawa
IPC分类号： H01C1/034
CPC分类号： H01C7/003 , H01C1/06 , H01C17/006 , H01C17/06506 , Y10T29/49155
摘要： A chip-like electric component such as a chip resistor is provided, which is easy to manufacture and in which cracks or fractures of an insulating substrate are unlikely to occur. A pair of surface electrodes 21, 23 are formed so that thicknesses of the pair of surface electrodes increase from a resistor layer 13 toward end portions 30 of an insulating substrate 29 in a direction in which the pair of surface electrodes 21, 23 are arranged. A plating reservoir S is formed between one of the surface electrodes 21, 23 and an insulating protective layer 15. When forming at least one plated layer 33, a plated metal pools in the plating reservoir S. The at least one plated layer 33 may work to reduce to some extent a height difference between a soldering electrode portion 21, 23, 27, 33 and the insulating protective layer 15.
摘要翻译：提供了诸如片状电阻器的芯片状电气部件，其易于制造，并且其中不可能发生绝缘基板的裂纹或断裂。形成一对表面电极21,23，使得一对表面电极的厚度从电阻层13朝向绝缘基板29的端部配置在一对表面电极21,23的方向上增加。在一个表面电极21,23和绝缘保护层15之间形成电镀槽S.当形成至少一个镀层33时，电镀金属池在电镀槽S中。至少一个镀层33可以工作以在一定程度上减少焊接电极部分21,23,27,33与绝缘保护层15之间的高度差。

7. 发明申请

US20100266753A1 CONNECTOR CHIP AND MANUFACTURING METHOD THEREOF 有权
标题翻译：连接器芯片及其制造方法
公开(公告)号：US20100266753A1
公开(公告)日：2010-10-21
申请号：US12827755
申请日：2010-06-30
申请人： Shinji Okamoto , Katsumi Takeuchi , Yutaka Nomura
发明人： Shinji Okamoto , Katsumi Takeuchi , Yutaka Nomura
IPC分类号： H01R43/00
CPC分类号： H05K3/368 , H01R12/52 , H05K3/3442 , H05K2201/10378 , Y10T29/49126
摘要： The present invention provides a connector chip capable of preventing electrical shorting between adjoining electrodes and also capable of readily connecting a plurality of electrodes on a first circuit substrate and a plurality of electrodes on a second circuit substrate without using a dedicated mounting device or the like. A plurality of conductive paths 5 are formed on an outer periphery surface constituted by continuous four surfaces 9A to 9D of an insulating substrate 3 including six surfaces of the surfaces 9A to 9D and surfaces 9E and 9F. Each of the conductive paths 5 goes round on the outer periphery surface. The conductive paths 5 are formed on the outer periphery surface at a predetermined interval in an opposing direction in which the remaining two surfaces 9E and 9F are opposing to each other. Each of insulating layers 7 having a property of repelling molten solder is formed between portions of each two adjoining conductive paths located on a pair of the surfaces 9A and 9B. The width of a conductive-path-formed portion 3A with a conductive path 5 formed thereon, orthogonal to a center line C is formed to be smaller than the width of a conductive-path-unformed portion 3B with no conductive path 5 formed thereon, orthogonal to the center line C.
摘要翻译：本发明提供一种连接器芯片，其能够防止相邻电极之间的电短路，并且还能够容易地连接第一电路基板上的多个电极和第二电路基板上的多个电极，而不使用专用的安装装置等。在由包括表面9A至9D的六个表面和表面9E和9F的绝缘基板3的连续四个表面9A至9D构成的外周表面上形成多个导电通路5。导电路径5中的每一个在外周表面上圆周。导电路径5在剩余的两个表面9E和9F彼此相对的相反方向上以预定的间隔形成在外周表面上。在位于一对表面9A和9B上的每个两个邻接的导电路径的部分之间形成具有排斥熔融焊料性质的绝缘层7。形成有与中心线C正交的导电路径5的导电路径形成部3A的宽度形成为比形成有导电路径5的导电路径未成形部3B的宽度小，与中心线C正交

8. 发明申请

US20090231086A1 TERMINAL STRUCTURE OF CHIPLIKE ELECTRIC COMPONENT 有权
标题翻译： CHIPLIKE电气部件的终端结构
公开(公告)号：US20090231086A1
公开(公告)日：2009-09-17
申请号：US12088268
申请日：2006-09-27
申请人： Yutaka Nomura , Katsumi Takeuchi
发明人： Yutaka Nomura , Katsumi Takeuchi
IPC分类号： H01C1/012
CPC分类号： H01C1/142 , H01C1/012 , H01C1/148 , H01C7/003 , H01C17/006
摘要： A terminal structure of a chip-like electric component capable of blocking entry of electromigration-causing factors through an insulating resin layer in the vicinity of the peak of a raised portion of an electrical element forming layer is obtained. A metal-glaze-based front electrode 103 containing silver is provided on a surface of an insulating ceramic substrate 101. A resistor layer 107 electrically connected to the front electrode 103 is provided on the substrate surface. A glass layer 109a is provided to completely cover a surface of the resistor layer 107 as well as a surface of an end portion of the resistor layer 107 and also to partially cover the front electrode 103. An insulating resin layer 109b is provided to cover a surface of the glass layer 109a as well as a surface of at least an end portion of the glass layer 109a and to partially cover the front electrode 103. A conductive layer 117 made of a resin-based conductive paint is provided to extend over the surface of the front electrode 103 and an portion of the insulating resin layer 109b in the vicinity of the peak of raised end portion of the insulating resin layer 109b. The resin-based conductive paint is made by kneading particulate conductive silver powder and scale-like conductive silver powder into an epoxy-based insulating resin paint.
摘要翻译：可以获得能够通过电气元件形成层的凸起部分的峰附近的绝缘树脂层阻挡电迁移因子的芯片状电气部件的端子结构。在绝缘陶瓷基板101的表面上设置有含有银的金属釉基前电极103.电连接到前电极103的电阻层107设置在基板表面上。提供玻璃层109a以完全覆盖电阻层107的表面以及电阻层107的端部的表面，并且还部分覆盖前电极103.设置绝缘树脂层109b以覆盖玻璃层109a的表面以及玻璃层109a的至少一个端部的表面，并且部分地覆盖前电极103.设置由树脂基导电涂料制成的导电层117在表面上延伸的绝缘树脂层109b的顶端附近的绝缘树脂层109b的一部分。树脂系导电性涂料通过将颗粒状导电性银粉末和鳞状导电性银粉末混合成环氧系绝缘树脂涂料而制成。

9. 发明授权

US6121394A Metallocene-catalyzed olefin polymerization in the absence of aluminoxane 失效
标题翻译：在没有铝氧烷的情况下茂金属催化的烯烃聚合
公开(公告)号：US6121394A
公开(公告)日：2000-09-19
申请号：US450735
申请日：1995-05-25
申请人： Ryuichi Sugimoto , Tadashi Asanuma , Tutomu Iwatani , Katsumi Takeuchi , Osamu Uchida
发明人： Ryuichi Sugimoto , Tadashi Asanuma , Tutomu Iwatani , Katsumi Takeuchi , Osamu Uchida
IPC分类号： C08F4/44 , C08F4/619 , C08F4/6192 , C08F4/646 , C08F4/647 , C08F4/659 , C08F4/6592 , C08F10/00 , C08F110/06
CPC分类号： C08F10/00 , C08F110/06 , C08F4/61908 , C08F4/61912 , C08F4/61916 , C08F4/61922 , C08F4/65908 , C08F4/65912 , C08F4/65916 , C08F4/65922 , Y10S526/943
摘要： The present invention is directed to a method for polymerizing an .alpha.-olefin characterized by using a catalyst system which is obtained by reacting a halogenated metallocene compound with an organometallic compound, and then bringing the resultant reaction product into contact with a compound which will be a stable anion by reaction with the reaction product of the halogenated metallocene compound and the organometallic compound.When the method of the present invention is carried out, a polyolefin can be obtained by the use of the inexpensive catalyst in a high activity per unit amount of the catalyst.
摘要翻译：本发明涉及一种聚合α-烯烃的方法，其特征在于使用通过使卤代茂金属化合物与有机金属化合物反应获得的催化剂体系，然后使所得反应产物与将成为通过与卤代茂金属化合物和有机金属化合物的反应产物反应来制备稳定的阴离子。当进行本发明的方法时，可以通过使用廉价催化剂以每单位量催化剂的高活性获得聚烯烃。

10. 发明授权

US5314956A Polypropylene resin compositions of high syndiotacticity and preparation process thereof 失效
标题翻译：具有高间同立构规整度的聚丙烯树脂组合物及其制备方法
公开(公告)号：US5314956A
公开(公告)日：1994-05-24
申请号：US10787
申请日：1993-01-29
申请人： Tadashi Asanuma , Tetsunosuke Shiomura , Nobutaka Uchikawa , Tutomu Iwatani , Katsumi Takeuchi
发明人： Tadashi Asanuma , Tetsunosuke Shiomura , Nobutaka Uchikawa , Tutomu Iwatani , Katsumi Takeuchi
IPC分类号： C08F2/44 , C08F297/08 , C08L23/12 , C08L23/14 , C08L23/16
CPC分类号： C08F297/083 , C08L23/12 , C08L2207/12 , C08L23/14 , C08L23/142 , C08L23/16 , Y10S526/943
摘要： Disclosed herein is a polypropylene resin composition of a high syndiotacticity comprising a substantial homopolymer of propylene, in which the ratio of the intensity of the peak attributable to the syndiotactic pentad bonds to the sum of the intensities of all the peaks attributable to the methyl groups in the spectrum of the methyl groups measured by .sup.13 C-NMR is 0.7 or more, and a copolymer of ethylene and propylene, and a preparation process thereof.
摘要翻译：本文公开了一种具有高间同立构规整性的聚丙烯树脂组合物，其包含基本上均匀的丙烯均聚物，其中归因于间同立构五键键的峰的强度与归因于甲基的所有峰的强度之和的比值通过13 C-NMR测定的甲基的光谱为0.7以上，乙烯与丙烯的共聚物及其制备方法。

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