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1. 发明申请

US20100164625A1 Slew-Rate-Enhanced Error Amp with Adaptive Transconductance and Single Dominant Pole Shared by Main and Auxiliary Amps 有权
标题翻译：具有自适应跨导和主主导极共同的主要和辅助放大器的转换率增益误差放大器
公开(公告)号：US20100164625A1
公开(公告)日：2010-07-01
申请号：US12345862
申请日：2008-12-30
申请人： Yat To (William) Wong , Chik Wai (David) Ng , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
发明人： Yat To (William) Wong , Chik Wai (David) Ng , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
IPC分类号： H03F3/45
CPC分类号： H03F3/45197 , H03F3/3023 , H03F3/45475 , H03F2203/45248 , H03F2203/45646 , H03F2203/45652 , H03F2203/45678
摘要： An error amplifier can be used to control a power regulator transistor. The error amplifier has a main amplifier, a pull-up auxiliary amplifier, and a pull-down auxiliary amplifier that all drive an output. A compensating capacitor on the output sets a single dominant pole for all amplifiers, increasing stability. High slew rates are provided by increased slew current from the auxiliary amplifiers that turn on when the differential input has an absolute voltage difference larger than an intentional offset. The intentional offset is introduced into the auxiliary amplifiers by adjusting a p-channel to n-channel transistor ratio in a leg of the auxiliary amplifiers. A source degenerated resistor in the main amplifier reduces supply headroom and increases linearity by connecting sources of two differential transistors that receive the differential input. Cascode transistors increase gain and output impedance. Reliability is increased as no positive feedback is used in the amplifiers.
摘要翻译：误差放大器可用于控制功率调节晶体管。误差放大器具有主放大器，上拉辅助放大器和全部驱动输出的下拉辅助放大器。输出上的补偿电容为所有放大器设置单个主极，从而提高稳定性。当差分输入具有大于有意偏移的绝对电压差时，来自辅助放大器的增加的转换电流提供高转换速率。通过调整辅助放大器的一个支路中的p沟道至n沟道晶体管比，将有意的偏移引入辅助放大器。主放大器中的源极退化电阻通过连接接收差分输入的两个差分晶体管的源极减小了供电余量并增加了线性度。串联晶体管增加了增益和输出阻抗。在放大器中没有使用正反馈的情况下，可靠性提高。

2. 发明授权

US07741981B1 Dual-use comparator/op amp for use as both a successive-approximation ADC and DAC 有权
标题翻译：双用比较器/运算放大器用作逐次逼近ADC和DAC
公开(公告)号：US07741981B1
公开(公告)日：2010-06-22
申请号：US12345844
申请日：2008-12-30
申请人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Hok Mo Yau , Tin Ho Andy Wu , Kwok Kuen David Kwong
发明人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Hok Mo Yau , Tin Ho Andy Wu , Kwok Kuen David Kwong
IPC分类号： H03M1/00
CPC分类号： H03M1/02 , H03M1/468 , H03M1/804
摘要： A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes.
摘要翻译：一个可重新配置的电路充当模数转换器（ADC）和数模转换器（DAC）。一组二进制加权电容器存储模拟输入。开关将阵列中的不同电容连接到固定电压，从而与端子电容器进行电荷共享。对于电容器的每个不同组合，端子电容器的电压通过可重新配置的比较器级进行比较。分析比较结果以确定模拟输入的最接近的数字值。在DAC模式下，基于输入数字值切换阵列电容器。开关电容器连接到电荷共享线路以产生施加到可重新配置的比较器级的模拟电压。差分放大器产生缓冲的模拟电压，反馈到可重新配置的比较器级的另一个输入以获得单位增益。可重新配置的比较器级的增益适用于ADC和DAC模式。

3. 发明授权

US07236040B2 Method and apparatus for generating multiphase clocks 有权
标题翻译：用于产生多相时钟的方法和装置
公开(公告)号：US07236040B2
公开(公告)日：2007-06-26
申请号：US11004754
申请日：2004-12-03
申请人： Ronny C. Chan , Mikhail Rodionov , Karen Wan , Richard W. Fung , Paul Edelshteyn , Ramesh Senthinathan
发明人： Ronny C. Chan , Mikhail Rodionov , Karen Wan , Richard W. Fung , Paul Edelshteyn , Ramesh Senthinathan
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： A multiphase clock generating circuit includes a multiphase clock generator that produces a plurality of multiphase output signals at a first frequency and a multiphase divider with delayed reset control. The multiphase divider with delayed reset control is operatively coupled to receive the plurality of multiphase output signals at the first frequency and further operative to produce a plurality of multiphase output signals at a second frequency based on reset control information. As a result, an interface can be supplied with and switch between multiphase clock at different frequencies within a short amount of time with reduced power consumption and circuit area.
摘要翻译：多相时钟发生电路包括多相时钟发生器，其产生具有第一频率的多个多相输出信号和具有延迟复位控制的多相分频器。具有延迟复位控制的多相分压器可操作地耦合以在第一频率处接收多个多相输出信号，并进一步操作以基于复位控制信息以第二频率产生多个多相输出信号。结果，可以在短时间内提供接口并在不同频率的多相时钟之间切换，同时降低功耗和电路面积。

4. 发明申请

US20130141264A1 REDUCED RESIDUAL OFFSET SIGMA DELTA ANALOG-TO-DIGITAL CONVERTER (ADC) WITH CHOPPER TIMING AT END OF INTEGRATING PHASE BEFORE TRAILING EDGE 有权
标题翻译：减少残留偏移SIGMA DELTA模拟数字转换器（ADC）在跟踪边缘之前的整合阶段结束时的切换时序
公开(公告)号：US20130141264A1
公开(公告)日：2013-06-06
申请号：US13308737
申请日：2011-12-01
申请人： Ho Ming (Karen) WAN , Yat To (William) WONG , Kwai Chi CHAN
发明人： Ho Ming (Karen) WAN , Yat To (William) WONG , Kwai Chi CHAN
IPC分类号： H03M3/02 , H03M1/12
CPC分类号： H03M3/34 , H03M3/43 , H03M3/454
摘要： An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.
摘要翻译：模数转换器（ADC）具有斩波稳定的Σ-Δ调制器（SDM）。 SDM使用开关电容积分器来采样，保持和集成模拟输入以响应不重叠的多相时钟。斩波倍增器插入在第一级积分器中的运算放大器的输入和输出端。斩波器乘法器响应于不重叠的斩波时钟交换或通过差分输入。以多相时钟频率工作的主时钟被分频以触发斩波时钟的产生。延迟线确保斩波时钟的边沿在多相时钟的边沿之前发生。当多相时钟变化时，斩波倍增器已经切换并稳定，因此在由多相时钟控制的开关处的电荷注入不会被斩波乘法器立即调制。该时钟定时增加了可以在改善线性度的开关处对电荷注入进行响应的时间。

5. 发明申请

US20100164770A1 MULTI-STAGE COMPARATOR WITH OFFSET CANCELING CAPACITOR ACROSS SECONDARY DIFFERENTIAL INPUTS FOR HIGH-SPEED LOW-GAIN COMPARE AND HIGH-GAIN AUTO-ZEROING 有权
标题翻译：具有偏移取消电容器的多级比较器，用于高速低增益比较和高增益自动调零的二次差分输入
公开(公告)号：US20100164770A1
公开(公告)日：2010-07-01
申请号：US12347113
申请日：2008-12-31
申请人： Ho Ming (Karen) Wan , Yat To (William) Wong , Kwai Chi Chan , Kwok Kuen Kwong
发明人： Ho Ming (Karen) Wan , Yat To (William) Wong , Kwai Chi Chan , Kwok Kuen Kwong
IPC分类号： H03M1/12 , H03M1/00 , H03F3/217
CPC分类号： H03F3/005 , H03F3/45183 , H03F2200/375 , H03F2200/555 , H03F2203/45536 , H03F2203/45544 , H03F2203/45586 , H03F2203/45616 , H03F2203/45631 , H03F2203/45678 , H03F2203/45702 , H03F2203/45726 , H03F2203/45732 , H03M1/0607 , H03M1/0682 , H03M1/46
摘要： An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an analog voltage compared to an input voltage by a series of stages. The last stage feeds a compare signal to the SAR. Each stage has a dual-input differential amplifier that operates as a unity gain op amp during an auto-zeroing phase and as a high-speed low-gain amplifier during an amplifying phase. The dual-input differential amplifier has two pairs of differential inputs. A secondary pair has an offset-storing capacitor across it, and connects to the output pair through feedback switches during auto-zeroing. A primary pair connects to stage inputs through input switches during the amplifying phase. Since two pairs of differential inputs are provided to the dual-input differential amplifier, the offset capacitor is completely isolated from the input pair. The current sink in the dual-input differential amplifier is adjusted higher during the amplifying period.
摘要翻译：模数转换器（ADC）具有驱动数模转换器（DAC）的逐次逼近寄存器（SAR），其通过一系列级与输入电压相比产生模拟电压。最后一个阶段向SAR提供比较信号。每个阶段都有一个双输入差分放大器，在自动归零阶段作为单位增益运算放大器工作，在放大阶段则作为高速低增益放大器工作。双输入差分放大器有两对差分输入。辅助对在其之间具有一个补偿存储电容器，并在自动归零期间通过反馈开关连接到输出对。在放大阶段，初级对通过输入开关连接到级输入。由于两对差分输入提供给双输入差分放大器，所以偏移电容与输入对完全隔离。在放大期间，双输入差分放大器中的电流吸收器被调高。

6. 发明授权

US07535272B1 Zero-delay buffer with common-mode equalizer for input and feedback differential clocks into a phase-locked loop (PLL) 有权
标题翻译：具有共模均衡器的零延迟缓冲器，用于输入和反馈差分时钟进入锁相环（PLL）
公开(公告)号：US07535272B1
公开(公告)日：2009-05-19
申请号：US11944545
申请日：2007-11-23
申请人： Kwok Kuen David Kwong , Ho Ming Karen Wan
发明人： Kwok Kuen David Kwong , Ho Ming Karen Wan
IPC分类号： H03L7/06
CPC分类号： H03L7/081 , H03L7/0891
摘要： A zero-delay clock generator has a phase-locked loop (PLL) that generates a feedback clock and receives a reference clocks. All clocks are differential and have a common-mode voltage. The common-mode voltage of an externally-generated reference clock can vary from the common-mode voltage of the internally-generated feedback clock. Differences in common-mode voltage of the reference clock and feedback clock cause delay variations resulting in static phase offsets of generated clocks. A common-mode sense and equalizer senses the common-mode voltages of the buffered reference and feedback clocks, and generates control voltages. The control voltages adjust the common-mode voltage and delay of differential buffers that receive the reference and feedback clocks. The control voltages adjust the differential buffers to match the common-mode voltages of the buffered reference and feedback clocks. The buffered clocks are then applied to a phase and frequency detector of the PLL.
摘要翻译：零延迟时钟发生器具有产生反馈时钟并接收参考时钟的锁相环（PLL）。所有时钟均为差分并具有共模电压。外部产生的参考时钟的共模电压可以从内部产生的反馈时钟的共模电压变化。参考时钟和反馈时钟的共模电压差异导致延迟变化，导致产生的时钟的静态相位偏移。共模感测和均衡器感测缓冲的参考和反馈时钟的共模电压，并产生控制电压。控制电压调节接收参考和反馈时钟的差分缓冲器的共模电压和延迟。控制电压调节差分缓冲器以匹配缓冲参考和反馈时钟的共模电压。缓冲时钟然后被施加到PLL的相位和频率检测器。

7. 发明申请

US20090045867A1 FUSE CELL AND METHOD FOR PROGRAMMING THE SAME 有权
标题翻译：保险丝盒及其编程方法
公开(公告)号：US20090045867A1
公开(公告)日：2009-02-19
申请号：US11838051
申请日：2007-08-13
申请人： David Kwok Kuen Kwong , Ho Ming Karen Wan , Kam Chuen Wan , Chik Wai Ng
发明人： David Kwok Kuen Kwong , Ho Ming Karen Wan , Kam Chuen Wan , Chik Wai Ng
IPC分类号： H01H85/00
CPC分类号： G11C17/16 , Y02P80/30
摘要： The fuse cell architecture 371 for the presently claimed invention employs a multiple fuse structure 301, 302 architecture in lieu of a single fuse structure. As such, the terminals of these fuse structures that couple to other on-chip devices are always at ground potential throughout the application of programming voltage to the fuse pads 311. This approach overcomes previous single fuse problems owing to the fact that a sufficiently high programming voltage can be applied to blow fuse structures with unexpectedly high resistance without damaging nearby on-chip devices. Furthermore, even if one of the fuse structures 301, 302 possessed an abnormally high resistance which would not be blown under typical conditions, the desired circuit trimming result can still be achieved owing to the blowing of the other fuse structure in the fuse cell 371.
摘要翻译：用于当前要求保护的发明的熔丝单元结构371采用多个熔丝结构301,302代替单个熔丝结构。因此，耦合到其它片上器件的这些熔丝结构的端子在编程电压施加到熔丝焊盘311时始终处于地电位。由于以下事实，该方法克服了先前的单熔丝问题，这是因为足够高的编程可以施加电压来熔断具有意想不到的高电阻的熔丝结构，而不会损坏附近的片上器件。此外，即使保险丝结构301,302中的一个具有在典型条件下不会被烧断的异常高电阻，由于熔丝单元371中的另一熔丝结构的吹动，仍然可以实现期望的电路修整结果。

8. 发明申请

US20060119408A1 Method and apparatus for generating multiphase clocks 有权
标题翻译：用于产生多相时钟的方法和装置
公开(公告)号：US20060119408A1
公开(公告)日：2006-06-08
申请号：US11004754
申请日：2004-12-03
申请人： Ronny Chan , Mikhail Rodionov , Karen Wan , Richard Fung , Paul Edelshteyn , Ramesh Senthinathan
发明人： Ronny Chan , Mikhail Rodionov , Karen Wan , Richard Fung , Paul Edelshteyn , Ramesh Senthinathan
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： A multiphase clock generating circuit includes a multiphase clock generator that produces a plurality of multiphase output signals at a first frequency and a multiphase divider with delayed reset control. The multiphase divider with delayed reset control is operatively coupled to receive the plurality of multiphase output signals at the first frequency and further operative to produce a plurality of multiphase output signals at a second frequency based on reset control information. As a result, an interface can be supplied with and switch between multiphase clock at different frequencies within a short amount of time with reduced power consumption and circuit area.
摘要翻译：多相时钟发生电路包括多相时钟发生器，其产生具有第一频率的多个多相输出信号和具有延迟复位控制的多相分频器。具有延迟复位控制的多相分压器可操作地耦合以在第一频率处接收多个多相输出信号，并进一步操作以基于复位控制信息以第二频率产生多个多相输出信号。结果，可以在短时间内提供接口并在不同频率的多相时钟之间切换，同时降低功耗和电路面积。

9. 发明授权

US08421660B1 Configurable cascading sigma delta analog-to digital converter (ADC) for adjusting power and performance 有权
标题翻译：可配置的级联Σ-Δ模数转换器（ADC），用于调节功率和性能
公开(公告)号：US08421660B1
公开(公告)日：2013-04-16
申请号：US13304526
申请日：2011-11-25
申请人： Ho Ming (Karen) Wan , Yat To (William) Wong , Kwai Chi Chan , Andrea Baschirotto
发明人： Ho Ming (Karen) Wan , Yat To (William) Wong , Kwai Chi Chan , Andrea Baschirotto
IPC分类号： H03M3/00
CPC分类号： H03M3/392 , H03M3/414
摘要： A cascaded sigma-delta modulator has several modulator loops that have one or two sets of integrators, summers, and scalers, and a quantizer that generates a loop output. Input muxes to each loop select either an overall input or the loop output from a prior loop, allowing the modulator loops to be cascaded in series or to operate separately. Filter-configuring muxes after each modulator loop select either that loop's output or a loop output from any prior loop, or a zero. Each filter-configuring mux drives an input to a modified CIC filter. The modified CIC filter has an initial delay stage that receives the first filter-configuring mux output, and successive integrator stages that each receives a successive filter-configuring mux output. The modified CIC filter is a combination of a digital transform filter and a Cascaded-Integrator-Comb (CIC) filter. Modulator loops are powered down for lower-performance configurations or cascaded together for higher-performance configurations.
摘要翻译：级联的Σ-Δ调制器具有多个调制器环路，其具有一组或两组积分器，加法器和定标器，以及产生回路输出的量化器。对每个环路输入多路复用器，从一个先前的循环中选择一个总体输入或一个环路输出，使调制器回路串联级联或单独运行。在每个调制器环路之后，滤波器配置的多路复用器选择该环路的输出或来自任何先前循环的回路输出或零。每个过滤器配置的多路复用器驱动输入到修改后的CIC过滤器。修改的CIC滤波器具有接收第一滤波器配置多路复用器输出的初始延迟级，以及每个接收连续的滤波器配置多路复用器输出的连续积分器级。改进的CIC滤波器是数字变换滤波器和级联积分器（CIC） - 滤波器（Cascaded-Integrator-Comb，CIC）滤波器的组合。调制解调器环路已经掉电，用于低性能配置或级联在一起以实现更高性能的配置。

10. 发明授权

US08416107B1 Charge compensation calibration for high resolution data converter 有权
标题翻译：高分辨率数据转换器的充电补偿校准
公开(公告)号：US08416107B1
公开(公告)日：2013-04-09
申请号：US13247119
申请日：2011-09-28
申请人： Kam Chuen Wan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kwai Chi Chan
发明人： Kam Chuen Wan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kwai Chi Chan
IPC分类号： H03M1/10
CPC分类号： H03M1/1033 , H03M1/0682 , H03M1/804
摘要： A calibrating Analog-to-Digital Converter (ADC) has an X-side array with binary-weighted capacitors that connect to an X-side line and a Y-side array connected to a Y-side line. Each array has binary-weighted capacitors from a most-significant-bit (MSB) to a least-significant-bit (LSB), but the LSB capacitor is duplicated as a termination capacitor and a middle capacitor between upper and lower groups is also duplicated as a surrogate capacitor. During calibration, lower array capacitors are switched low while the upper capacitors are driven by a thermometer-code value on both X and Y arrays. The thermometer value is inverted to the X-array but remains uninverted on the Y array. The lower array bits are tested to final a calibration value that has X and Y side voltages balanced.
摘要翻译：校准模数转换器（ADC）具有X侧阵列，其具有连接到Y侧线的X侧线和Y侧阵列的二进制加权电容器。每个阵列具有从最高有效位（MSB）到最低有效位（LSB）的二进制加权电容，但是LSB电容复制为终端电容，并且上下组之间的中间电容也被复制作为替代电容器。在校准期间，低阵列电容器切换低电平，而上电容器由X和Y阵列上的温度计代码值驱动。温度计值反转到X阵列，但在Y阵列上保持不变。测试较低的阵列位以最终确定平衡X和Y侧电压的校准值。

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