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1. 发明申请

US20100164625A1 Slew-Rate-Enhanced Error Amp with Adaptive Transconductance and Single Dominant Pole Shared by Main and Auxiliary Amps 有权
标题翻译：具有自适应跨导和主主导极共同的主要和辅助放大器的转换率增益误差放大器
公开(公告)号：US20100164625A1
公开(公告)日：2010-07-01
申请号：US12345862
申请日：2008-12-30
申请人： Yat To (William) Wong , Chik Wai (David) Ng , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
发明人： Yat To (William) Wong , Chik Wai (David) Ng , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
IPC分类号： H03F3/45
CPC分类号： H03F3/45197 , H03F3/3023 , H03F3/45475 , H03F2203/45248 , H03F2203/45646 , H03F2203/45652 , H03F2203/45678
摘要： An error amplifier can be used to control a power regulator transistor. The error amplifier has a main amplifier, a pull-up auxiliary amplifier, and a pull-down auxiliary amplifier that all drive an output. A compensating capacitor on the output sets a single dominant pole for all amplifiers, increasing stability. High slew rates are provided by increased slew current from the auxiliary amplifiers that turn on when the differential input has an absolute voltage difference larger than an intentional offset. The intentional offset is introduced into the auxiliary amplifiers by adjusting a p-channel to n-channel transistor ratio in a leg of the auxiliary amplifiers. A source degenerated resistor in the main amplifier reduces supply headroom and increases linearity by connecting sources of two differential transistors that receive the differential input. Cascode transistors increase gain and output impedance. Reliability is increased as no positive feedback is used in the amplifiers.
摘要翻译：误差放大器可用于控制功率调节晶体管。误差放大器具有主放大器，上拉辅助放大器和全部驱动输出的下拉辅助放大器。输出上的补偿电容为所有放大器设置单个主极，从而提高稳定性。当差分输入具有大于有意偏移的绝对电压差时，来自辅助放大器的增加的转换电流提供高转换速率。通过调整辅助放大器的一个支路中的p沟道至n沟道晶体管比，将有意的偏移引入辅助放大器。主放大器中的源极退化电阻通过连接接收差分输入的两个差分晶体管的源极减小了供电余量并增加了线性度。串联晶体管增加了增益和输出阻抗。在放大器中没有使用正反馈的情况下，可靠性提高。

2. 发明授权

US07795976B2 Slew-rate-enhanced error amp with adaptive transconductance and single dominant pole shared by main and auxiliary amps 有权
标题翻译：具有自适应跨导的转换率增益误差放大器和主和辅助放大器共享的单个主导极
公开(公告)号：US07795976B2
公开(公告)日：2010-09-14
申请号：US12345862
申请日：2008-12-30
申请人： Yat To William Wong , Chik Wai David Ng , Ho Ming Karen Wan , Kam Chuen Wan , Kwok Kuen David Kwong
发明人： Yat To William Wong , Chik Wai David Ng , Ho Ming Karen Wan , Kam Chuen Wan , Kwok Kuen David Kwong
IPC分类号： H03F3/45
CPC分类号： H03F3/45197 , H03F3/3023 , H03F3/45475 , H03F2203/45248 , H03F2203/45646 , H03F2203/45652 , H03F2203/45678
摘要： An error amplifier can be used to control a power regulator transistor. The error amplifier has a main amplifier, a pull-up auxiliary amplifier, and a pull-down auxiliary amplifier that all drive an output. A compensating capacitor on the output sets a single dominant pole for all amplifiers, increasing stability. High slew rates are provided by increased slew current from the auxiliary amplifiers that turn on when the differential input has an absolute voltage difference larger than an intentional offset. The intentional offset is introduced into the auxiliary amplifiers by adjusting a p-channel to n-channel transistor ratio in a leg of the auxiliary amplifiers. A source degenerated resistor in the main amplifier reduces supply headroom and increases linearity by connecting sources of two differential transistors that receive the differential input. Cascode transistors increase gain and output impedance. Reliability is increased as no positive feedback is used in the amplifiers.
摘要翻译：误差放大器可用于控制功率调节晶体管。误差放大器具有主放大器，上拉辅助放大器和全部驱动输出的下拉辅助放大器。输出上的补偿电容为所有放大器设置单个主极，从而提高稳定性。当差分输入具有大于有意偏移的绝对电压差时，来自辅助放大器的增加的转换电流提供高转换速率。通过调整辅助放大器的一个支路中的p沟道至n沟道晶体管比，将有意的偏移引入辅助放大器。主放大器中的源极退化电阻通过连接接收差分输入的两个差分晶体管的源极减小了供电余量并增加了线性度。串联晶体管增加了增益和输出阻抗。在放大器中没有使用正反馈的情况下，可靠性提高。

3. 发明授权

US08258864B1 Ultra low voltage multi-stage high-speed CMOS comparator with autozeroing 有权
标题翻译：具有自动调零功能的超低压多级高速CMOS比较器
公开(公告)号：US08258864B1
公开(公告)日：2012-09-04
申请号：US13238236
申请日：2011-09-21
申请人： Kwai Chi Chan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
发明人： Kwai Chi Chan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
IPC分类号： H03F1/02
CPC分类号： H03F3/45183 , H03F3/45636 , H03F2200/261 , H03F2200/294 , H03F2200/453 , H03F2203/45616 , H03F2203/45628
摘要： A pre-amplifier circuit can be cascaded and drive a latch for use in a precision analog-to-digital converter (ADC). The pre-amplifier has a main section and a feedback section connected by feedback resistors that do not produce voltage drops in the main section. Offset is stored on offset capacitors during an autozeroing phase and isolated by transmission gates during an amplifying phase. The offset capacitors drive the gates of feedback transistors that drive output nodes in the main section. Autozeroing sink transistors in the feedback section operate in the linear region while current sink transistors in the main section operate in the saturated region. Kickback-charge isolation transistors may be added for charge isolation. The output may also be equalized by an equalizing transmission gate. A very low power-supply voltage is supported even for high-speed operation with offset cancellation, due to the folded feedback resistor arrangement.
摘要翻译：前级放大器电路可以级联并驱动锁存器，用于精密模数转换器（ADC）。前置放大器有一个主要部分和一个反馈部分，通过反馈电阻连接，主部分不产生电压降。偏移量在自动调零阶段存储在偏移电容上，并在放大阶段由传输门隔离。偏移电容器驱动驱动主部分中的输出节点的反馈晶体管的栅极。反馈部分中的自动归零陷波晶体管工作在线性区域，而主部分中的电流吸收晶体管工作在饱和区域。可以添加Kickback电荷隔离晶体管用于电荷隔离。输出也可以通过均衡的传输门来均衡。由于折叠的反馈电阻器布置，即使对于具有偏移消除的高速操作也支持非常低的电源电压。

4. 发明授权

US08193854B2 Bi-directional trimming methods and circuits for a precise band-gap reference 有权
标题翻译：用于精确带隙参考的双向修整方法和电路
公开(公告)号：US08193854B2
公开(公告)日：2012-06-05
申请号：US12651993
申请日：2010-01-04
申请人： Xiao Fei Kuang , Kam Chuen Wan , Kwai Chi Chan , Yat To (William) Wong , Kwok Kuen (David) Kwong
发明人： Xiao Fei Kuang , Kam Chuen Wan , Kwai Chi Chan , Yat To (William) Wong , Kwok Kuen (David) Kwong
IPC分类号： G05F3/02
CPC分类号： G05F3/30 , H01C17/22
摘要： A bandgap reference circuit has trimming-up resistors and trimming-down resistors for bi-directional trimming. PNP transistors have base and collectors grounded and emitters connected to parallel resistors. A difference resistor drives an inverting input of an op amp that drives a transistor that generates the bandgap reference voltage Vbg. A sensing resistor connects Vbg to a splitting node that connects to the non-inverting input through a first parallel resistor. The splitting node also connects through a second parallel resistor to the inverting input. Fuses or switches enable the trimming-up and trimming-down resistors. The trimming-up resistors are in series with the sensing resistor and the trimming-down resistors are in series with an output resistor that connects Vbg to reference voltage Vref. The circuit can be designed for a more typical process since bi-directional trimming allows Vref to be raised or lowered. Many circuits need no trimming when targeted for the typical process.
摘要翻译：带隙参考电路具有用于双向修剪的微调电阻和微调电阻。 PNP晶体管的基极和集电极接地，发射极连接到并联电阻。差分电阻驱动驱动产生带隙参考电压Vbg的晶体管的运算放大器的反相输入。感测电阻器将Vbg连接到通过第一并联电阻器连接到非反相输入的分离节点。分离节点还通过第二并联电阻器连接到反相输入端。保险丝或开关使能微调和微调电阻。修整电阻与感测电阻串联，并且减法电阻与将Vbg连接到参考电压Vref的输出电阻串联。该电路可以设计用于更典型的工艺，因为双向修整允许Vref被升高或降低。许多电路在针对典型过程时不需要修剪。

5. 发明授权

US07710094B1 Current-mode-controlled current sensor circuit for power switching converter 有权
标题翻译：用于电源开关变换器的电流模式控制电流传感器电路
公开(公告)号：US07710094B1
公开(公告)日：2010-05-04
申请号：US12333979
申请日：2008-12-12
申请人： Yat To William Wong , Xiao Fei Kuang , Kam Chuen Wan , Kwok Kuen David Kwong
发明人： Yat To William Wong , Xiao Fei Kuang , Kam Chuen Wan , Kwok Kuen David Kwong
IPC分类号： G05F1/00 , G05F3/02 , G05F3/16
CPC分类号： H02M3/156 , G01R19/0092 , H02M2001/0009
摘要： A power converter has a power transistor driving a power current through an inductor to provide a controlled power-supply voltage. The power transistor is on during a first state but off during a second state when a sink transistor reduces the power current through the inductor. Both voltage sensing of the power-supply voltage and current sensing at the power transistor provide feedback to control the amount of time that the first state is active, and thus control the power current. Current sensing is provided by a smaller minor transistor in parallel with the power transistor. The minor transistor turns on after the power transistor to reduce disturbance spikes. Switches connect sources of the power and mirror transistors to an amplifier that drives a sensing transistor. The sensing transistor generates a sensing voltage from the mirror transistor source. During the second state the amplifier's inputs are equalized to provide fast response.
摘要翻译：功率转换器具有驱动通过电感器的功率电流以提供受控的电源电压的功率晶体管。功率晶体管在第一状态期间导通，而在第二状态期间，当晶体管晶体管降低通过电感器的功率电流时，功率晶体管截止。在功率晶体管处的电源电压和电流感测的两个电压检测提供反馈以控制第一状态是有效的时间量，从而控制功率电流。电流感测由与功率晶体管并联的较小次级晶体管提供。次晶体管在功率晶体管之后导通，以减少干扰尖峰。将电源和镜像晶体管的源极连接到驱动感测晶体管的放大器。感测晶体管产生来自反射镜晶体管源的感测电压。在第二状态期间，放大器的输入被均衡以提供快速响应。

6. 发明授权

US07812757B1 Hybrid analog-to-digital converter (ADC) with binary-weighted-capacitor sampling array and a sub-sampling charge-redistributing array for sub-voltage generation 有权
标题翻译：具有二进制加权电容采样阵列的混合模数转换器（ADC）和用于子电压发生的子采样电荷重分配阵列
公开(公告)号：US07812757B1
公开(公告)日：2010-10-12
申请号：US12483250
申请日：2009-06-12
申请人： Yat To William Wong , Kam Chuen Wan , Kwok Kuen David Kwong
发明人： Yat To William Wong , Kam Chuen Wan , Kwok Kuen David Kwong
IPC分类号： H03M1/12
CPC分类号： H03M1/468 , H03M1/68 , H03M1/804 , H03M1/806
摘要： A hybrid Analog-to-Digital Converter (ADC) has a binary-weighted capacitor array and a sub-voltage capacitor array that are coupled together by a coupling capacitor. The sub-voltage capacitor array uses a minimum capacitor size that matches the minimum capacitor size of the binary-weighted capacitor array. The coupling capacitor is double the minimum size and reduces a voltage effect on a charge sharing line by half. Second coupling capacitors in the sub-voltage capacitor array each reduce the voltage effect by half, so that first, second, and third sub-voltage capacitors in the sub-voltage capacitor array produce ½, ¼, and ⅛ voltage swings using the minimum size capacitance. Only MSB capacitors in the binary-weighted capacitor array sample the analog input voltage. During conversion, MSB's from a Successive-Approximation-Register (SAR) are applied to binary-weighted capacitors while LSB's are applied to sub-voltage capacitors. The total capacitance is reduced by applying the LSB's only to the sub-voltage capacitor array.
摘要翻译：混合模数转换器（ADC）具有通过耦合电容器耦合在一起的二进制加权电容器阵列和子电压电容器阵列。子电压电容器阵列使用与二进制加权电容器阵列的最小电容器尺寸匹配的最小电容器尺寸。耦合电容是最小尺寸的两倍，并将电荷共享线上的电压降低一半。次级电容器阵列中的第二耦合电容器将电压效应降低一半，使得次级电压电容器阵列中的第一，第二和第三子电压电容器使用最小尺寸产生½，¼和⅛电压摆幅电容。二进制加权电容阵列中只有MSB电容采样模拟输入电压。在转换期间，来自连续近似寄存器（SAR）的MSB被应用于二进制加权电容器，而LSB被应用于子电压电容器。通过将LSB仅施加到子电压电容器阵列来减小总电容。

7. 发明授权

US08416107B1 Charge compensation calibration for high resolution data converter 有权
标题翻译：高分辨率数据转换器的充电补偿校准
公开(公告)号：US08416107B1
公开(公告)日：2013-04-09
申请号：US13247119
申请日：2011-09-28
申请人： Kam Chuen Wan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kwai Chi Chan
发明人： Kam Chuen Wan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kwai Chi Chan
IPC分类号： H03M1/10
CPC分类号： H03M1/1033 , H03M1/0682 , H03M1/804
摘要： A calibrating Analog-to-Digital Converter (ADC) has an X-side array with binary-weighted capacitors that connect to an X-side line and a Y-side array connected to a Y-side line. Each array has binary-weighted capacitors from a most-significant-bit (MSB) to a least-significant-bit (LSB), but the LSB capacitor is duplicated as a termination capacitor and a middle capacitor between upper and lower groups is also duplicated as a surrogate capacitor. During calibration, lower array capacitors are switched low while the upper capacitors are driven by a thermometer-code value on both X and Y arrays. The thermometer value is inverted to the X-array but remains uninverted on the Y array. The lower array bits are tested to final a calibration value that has X and Y side voltages balanced.
摘要翻译：校准模数转换器（ADC）具有X侧阵列，其具有连接到Y侧线的X侧线和Y侧阵列的二进制加权电容器。每个阵列具有从最高有效位（MSB）到最低有效位（LSB）的二进制加权电容，但是LSB电容复制为终端电容，并且上下组之间的中间电容也被复制作为替代电容器。在校准期间，低阵列电容器切换低电平，而上电容器由X和Y阵列上的温度计代码值驱动。温度计值反转到X阵列，但在Y阵列上保持不变。测试较低的阵列位以最终确定平衡X和Y侧电压的校准值。

8. 发明授权

US08421658B1 Parallel pipelined calculation of two calibration values during the prior conversion cycle in a successive-approximation-register analog-to-digital converter (SAR-ADC) 有权
标题翻译：在逐次逼近寄存器模数转换器（SAR-ADC）中，在先前的转换周期内对两个校准值进行并行流水线计算，
公开(公告)号：US08421658B1
公开(公告)日：2013-04-16
申请号：US13304346
申请日：2011-11-24
申请人： Hok Mo Yau , Tin Ho (Andy) Wu , Kam Chuen Wan , Yat To (William) Wong
发明人： Hok Mo Yau , Tin Ho (Andy) Wu , Kam Chuen Wan , Yat To (William) Wong
IPC分类号： H03M1/10
CPC分类号： H03M1/1004 , H03M1/1047 , H03M1/468
摘要： A Successive-Approximation Register Analog-to-Digital Converter (SAR-ADC) predicts compensation values for use in a future cycle. A compensation value is applied to capacitors in a calibration Y-side capacitor array to compensate for capacitance errors in a binary-weighted X-side capacitor array. Two compute engines pre-calculate predicted-0 and predicted-1 compensation values for a next bit to be converted. At the end of the current cycle when the comparator determines the current bit, the comparator also controls a mux to select one of the two predicted compensation values. Thus the compensation value is available at the beginning of the next bit's cycle, eliminating a long calculation delay. The compensation value for the first bit to be converted, such as the MSB, is calculated during calibration. Compensation values for other bits are data-dependent. Calibration values are accumulated during calibration to generate the first conversion compensation value for the first bit to be converted.
摘要翻译：逐次近似寄存器模数转换器（SAR-ADC）预测在未来周期中使用的补偿值。补偿值用于校准Y侧电容器阵列中的电容器，以补偿二进制加权的X侧电容器阵列中的电容误差。两个计算引擎预先计算下一个要转换的位的预测0和预测-1补偿值。在比较器确定当前位的当前周期结束时，比较器还控制多路复用器来选择两个预测补偿值之一。因此，补偿值在下一位循环开始时可用，消除了长时间的计算延迟。在校准期间计算要转换的第一位的补偿值，例如MSB。其他位的补偿值依赖于数据。在校准期间累积校准值，以生成要转换的第一个位的第一个转换补偿值。

9. 发明申请

US20090045867A1 FUSE CELL AND METHOD FOR PROGRAMMING THE SAME 有权
标题翻译：保险丝盒及其编程方法
公开(公告)号：US20090045867A1
公开(公告)日：2009-02-19
申请号：US11838051
申请日：2007-08-13
申请人： David Kwok Kuen Kwong , Ho Ming Karen Wan , Kam Chuen Wan , Chik Wai Ng
发明人： David Kwok Kuen Kwong , Ho Ming Karen Wan , Kam Chuen Wan , Chik Wai Ng
IPC分类号： H01H85/00
CPC分类号： G11C17/16 , Y02P80/30
摘要： The fuse cell architecture 371 for the presently claimed invention employs a multiple fuse structure 301, 302 architecture in lieu of a single fuse structure. As such, the terminals of these fuse structures that couple to other on-chip devices are always at ground potential throughout the application of programming voltage to the fuse pads 311. This approach overcomes previous single fuse problems owing to the fact that a sufficiently high programming voltage can be applied to blow fuse structures with unexpectedly high resistance without damaging nearby on-chip devices. Furthermore, even if one of the fuse structures 301, 302 possessed an abnormally high resistance which would not be blown under typical conditions, the desired circuit trimming result can still be achieved owing to the blowing of the other fuse structure in the fuse cell 371.
摘要翻译：用于当前要求保护的发明的熔丝单元结构371采用多个熔丝结构301,302代替单个熔丝结构。因此，耦合到其它片上器件的这些熔丝结构的端子在编程电压施加到熔丝焊盘311时始终处于地电位。由于以下事实，该方法克服了先前的单熔丝问题，这是因为足够高的编程可以施加电压来熔断具有意想不到的高电阻的熔丝结构，而不会损坏附近的片上器件。此外，即使保险丝结构301,302中的一个具有在典型条件下不会被烧断的异常高电阻，由于熔丝单元371中的另一熔丝结构的吹动，仍然可以实现期望的电路修整结果。

10. 发明授权

US07538597B2 Fuse cell and method for programming the same 有权
标题翻译：保险丝盒及其编程方法
公开(公告)号：US07538597B2
公开(公告)日：2009-05-26
申请号：US11838051
申请日：2007-08-13
申请人： David Kwok Kuen Kwong , Ho Ming Karen Wan , Kam Chuen Wan , Chik Wai Ng
发明人： David Kwok Kuen Kwong , Ho Ming Karen Wan , Kam Chuen Wan , Chik Wai Ng
IPC分类号： H03H37/76
CPC分类号： G11C17/16 , Y02P80/30
摘要： The fuse cell architecture 371 for the presently claimed invention employs a multiple fuse structure 301, 302 architecture in lieu of a single fuse structure. As such, the terminals of these fuse structures that couple to other on-chip devices are always at ground potential throughout the application of programming voltage to the fuse pads 311. This approach overcomes previous single fuse problems owing to the fact that a sufficiently high programming voltage can be applied to blow fuse structures with unexpectedly high resistance without damaging nearby on-chip devices. Furthermore, even if one of the fuse structures 301, 302 possessed an abnormally high resistance which would not be blown under typical conditions, the desired circuit trimming result can still be achieved owing to the blowing of the other fuse structure in the fuse cell 371.
摘要翻译：用于当前要求保护的发明的熔丝单元结构371采用多个熔丝结构301,302代替单个熔丝结构。因此，耦合到其它片上器件的这些熔丝结构的端子在编程电压施加到熔丝焊盘311时始终处于地电位。由于以下事实，该方法克服了先前的单熔丝问题，这是因为足够高的编程可以施加电压来熔断具有意想不到的高电阻的熔丝结构，而不会损坏附近的片上器件。此外，即使保险丝结构301,302中的一个具有在典型条件下不会被烧断的异常高电阻，由于熔丝单元371中的另一熔丝结构的吹动，仍然可以实现期望的电路修整结果。

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