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    • 5. 发明授权
    • Enhancement normally off nitride semiconductor device manufacturing the same
    • 增强通常关闭氮化物半导体器件制造相同
    • US08551821B2
    • 2013-10-08
    • US12960499
    • 2010-12-04
    • Jung Hee LeeKi Sik ImJong Bong Ha
    • Jung Hee LeeKi Sik ImJong Bong Ha
    • H01L21/335H01L21/8232H01L21/339H01L21/00H01L21/84
    • H01L29/7787H01L29/1033H01L29/2003H01L29/517H01L29/66462
    • The present invention relates to an enhancement normally off nitride semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buffer layer on a substrate; forming a first nitride semiconductor layer on the buffer layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer; etching a gate region above the second nitride semiconductor layer up to a predetermined depth of the first nitride semiconductor layer; forming an insulating film on the etched region and the second nitride semiconductor layer; patterning a source/drain region, etching the insulating film in the source/drain region, and forming electrodes in the source/drain region; and forming a gate electrode on the insulating film in the gate region. In this manner, the present invention provides a method of easily implementing a normally off enhancement semiconductor device by originally blocking 2DEG which is generated under a gate region. In addition, the present invention provides an enhancement normally off power semiconductor device with a simple and efficient driving circuit in a HEMT device.
    • 本发明涉及一种增强常关氮化物半导体器件及其制造方法。 该方法包括以下步骤:在衬底上形成缓冲层; 在所述缓冲层上形成第一氮化物半导体层; 在所述第一氮化物半导体层上形成第二氮化物半导体层; 将第二氮化物半导体层上方的栅极区域蚀刻到第一氮化物半导体层的预定深度; 在蚀刻区域和第二氮化物半导体层上形成绝缘膜; 图案化源极/漏极区域,蚀刻源极/漏极区域中的绝缘膜,以及在源极/漏极区域中形成电极; 以及在栅极区域的绝缘膜上形成栅电极。 以这种方式,本发明提供了一种通过最初阻挡在栅极区域下产生的2DEG来容易地实现常关的增强型半导体器件的方法。 此外,本发明提供了一种在HEMT装置中具有简单有效的驱动电路的增强型常关功率半导体器件。
    • 9. 发明授权
    • Liquid crystal display and thin film transistor array panel therefor
    • 液晶显示器和薄膜晶体管阵列面板
    • US08228452B2
    • 2012-07-24
    • US12630249
    • 2009-12-03
    • Jung-Hee LeeYoon-Sung UmJong-Ho SonJae-Jin Lyu
    • Jung-Hee LeeYoon-Sung UmJong-Ho SonJae-Jin Lyu
    • G02F1/1343
    • G02F1/1368G02F1/13624G02F2001/134345H01L27/1255
    • A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer opposite the gate electrode; a data line formed on the gate insulating layer and including a first source electrode located on the semiconductor layer; first and second drain electrodes formed on the semiconductor layer, separated from each other and overlapping the gate electrode; a passivation layer formed on the data line and the first and second drain electrodes; and first and second pixel electrodes electrically connected to the first and second electrodes, respectively, wherein an overlapping area between the gate electrode and the first drain electrode is different from an overlapping area between the gate electrode and the second drain electrode.
    • 提供薄膜晶体管阵列面板,其包括:绝缘基板; 形成在所述基板上并包括栅电极的栅极线; 栅极绝缘层,形成在栅极线上; 形成在与栅电极相对的栅极绝缘层上的半导体层; 形成在所述栅绝缘层上并且包括位于所述半导体层上的第一源电极的数据线; 形成在半导体层上的第一和第二漏极彼此分离并与栅电极重叠; 形成在所述数据线和所述第一和第二漏电极上的钝化层; 以及分别电连接到第一和第二电极的第一和第二像素电极,其中栅电极和第一漏电极之间的重叠区域与栅电极和第二漏电极之间的重叠区域不同。