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1. 发明授权

US07652725B2 Liquid crystal display and thin film transistor array panel therefor 有权
标题翻译：液晶显示器和薄膜晶体管阵列面板
公开(公告)号：US07652725B2
公开(公告)日：2010-01-26
申请号：US11288246
申请日：2005-11-29
申请人： Jung-Hee Lee , Yoon-Sung Um , Jong-Ho Son , Jae-Jin Lyu
发明人： Jung-Hee Lee , Yoon-Sung Um , Jong-Ho Son , Jae-Jin Lyu
IPC分类号： G02F1/1343
CPC分类号： G02F1/1368 , G02F1/13624 , G02F2001/134345 , H01L27/1255
摘要： A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer opposite the gate electrode; a data line formed on the gate insulating layer and including a first source electrode located on the semiconductor layer; first and second drain electrodes formed on the semiconductor layer, separated from each other and overlapping the gate electrode; a passivation layer formed on the data line and the first and the second drain electrodes; and first and second pixel electrodes electrically connected to the first and the second drain electrodes, respectively, wherein an overlapping area between the gate electrode and the first drain electrode is different from an overlapping area between the gate electrode and the second drain electrode.
摘要翻译：提供薄膜晶体管阵列面板，其包括：绝缘基板; 形成在所述基板上并包括栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在与栅电极相对的栅极绝缘层上的半导体层; 形成在所述栅绝缘层上并且包括位于所述半导体层上的第一源电极的数据线; 形成在半导体层上的第一和第二漏极彼此分离并与栅电极重叠; 形成在数据线和第一和第二漏电极上的钝化层; 以及分别与第一和第二漏电极电连接的第一和第二像素电极，其中栅电极和第一漏电极之间的重叠区域与栅电极和第二漏电极之间的重叠区域不同。

2. 发明申请

US20060072048A1 Liquid crystal display and thin film transistor array panel therefor 有权
公开(公告)号：US20060072048A1
公开(公告)日：2006-04-06
申请号：US11288246
申请日：2005-11-29
申请人： Jung-Hee Lee , Yoon-Sung Um , Jong-Ho Son , Jae-Jin Lyu
发明人： Jung-Hee Lee , Yoon-Sung Um , Jong-Ho Son , Jae-Jin Lyu
IPC分类号： G02F1/1343
CPC分类号： G02F1/1368 , G02F1/13624 , G02F2001/134345 , H01L27/1255
摘要： A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer opposite the gate electrode; a data line formed on the gate insulating layer and including a first source electrode located on the semiconductor layer; first and second drain electrodes formed on the semiconductor layer, separated from each other and overlapping the gate electrode; a passivation layer formed on the data line and the first and the second drain electrodes; and first and second pixel electrodes electrically connected to the first and the second drain electrodes, respectively, wherein an overlapping area between the gate electrode and the first drain electrode is different from an overlapping area between the gate electrode and the second drain electrode.

3. 发明授权

US08228452B2 Liquid crystal display and thin film transistor array panel therefor 失效
标题翻译：液晶显示器和薄膜晶体管阵列面板
公开(公告)号：US08228452B2
公开(公告)日：2012-07-24
申请号：US12630249
申请日：2009-12-03
申请人： Jung-Hee Lee , Yoon-Sung Um , Jong-Ho Son , Jae-Jin Lyu
发明人： Jung-Hee Lee , Yoon-Sung Um , Jong-Ho Son , Jae-Jin Lyu
IPC分类号： G02F1/1343
CPC分类号： G02F1/1368 , G02F1/13624 , G02F2001/134345 , H01L27/1255
摘要： A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer opposite the gate electrode; a data line formed on the gate insulating layer and including a first source electrode located on the semiconductor layer; first and second drain electrodes formed on the semiconductor layer, separated from each other and overlapping the gate electrode; a passivation layer formed on the data line and the first and second drain electrodes; and first and second pixel electrodes electrically connected to the first and second electrodes, respectively, wherein an overlapping area between the gate electrode and the first drain electrode is different from an overlapping area between the gate electrode and the second drain electrode.
摘要翻译：提供薄膜晶体管阵列面板，其包括：绝缘基板; 形成在所述基板上并包括栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在与栅电极相对的栅极绝缘层上的半导体层; 形成在所述栅绝缘层上并且包括位于所述半导体层上的第一源电极的数据线; 形成在半导体层上的第一和第二漏极彼此分离并与栅电极重叠; 形成在所述数据线和所述第一和第二漏电极上的钝化层; 以及分别电连接到第一和第二电极的第一和第二像素电极，其中栅电极和第一漏电极之间的重叠区域与栅电极和第二漏电极之间的重叠区域不同。

4. 发明授权

US06999134B2 Liquid crystal display and thin film transistor array panel therefor 失效
标题翻译：液晶显示器和薄膜晶体管阵列面板
公开(公告)号：US06999134B2
公开(公告)日：2006-02-14
申请号：US10445849
申请日：2003-05-28
申请人： Jung-Hee Lee , Yoon-Sung Um , Jong-Ho Son , Jae-Jin Lyu
发明人： Jung-Hee Lee , Yoon-Sung Um , Jong-Ho Son , Jae-Jin Lyu
IPC分类号： G02F1/1343
CPC分类号： G02F1/1368 , G02F1/13624 , G02F2001/134345 , H01L27/1255
摘要： A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer opposite the gate electrode; a data line formed on the gate insulating layer and including a first source electrode located on the semiconductor layer; first and second drain electrodes formed on the semiconductor layer, separated from each other and overlapping the gate electrode; a passivation layer formed on the data line and the first and the second drain electrodes; and first and second pixel electrodes electrically connected to the first and the second drain electrodes, respectively, wherein an overlapping area between the gate electrode and the first drain electrode is different from an overlapping area between the gate electrode and the second drain electrode.
摘要翻译：提供薄膜晶体管阵列面板，其包括：绝缘基板; 形成在所述基板上并包括栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在与栅电极相对的栅极绝缘层上的半导体层; 形成在所述栅绝缘层上并且包括位于所述半导体层上的第一源电极的数据线; 形成在半导体层上的第一和第二漏极彼此分离并与栅电极重叠; 形成在数据线和第一和第二漏电极上的钝化层; 以及分别与第一和第二漏电极电连接的第一和第二像素电极，其中栅电极和第一漏电极之间的重叠区域与栅电极和第二漏电极之间的重叠区域不同。

5. 发明授权

US06904047B2 Cell scheduling method of input and output buffered switch using simple iterative matching algorithm 失效
标题翻译：使用简单迭代匹配算法的输入和输出缓冲交换机的小区调度方法
公开(公告)号：US06904047B2
公开(公告)日：2005-06-07
申请号：US09860273
申请日：2001-05-17
申请人： Man-Soo Han , Jung-Hee Lee , In-Tack Han , Bhum-Cheol Lee
发明人： Man-Soo Han , Jung-Hee Lee , In-Tack Han , Bhum-Cheol Lee
IPC分类号： H04L12/70 , H04L12/933 , H04L12/935 , H04L12/56
CPC分类号： H04L49/1576 , H04L49/1523 , H04L49/3018 , H04L49/3027 , H04L2012/5679 , H04L2012/5683
摘要： A method for scheduling an input and output buffered ATM or packet switch and, more particularly, to a method for cell-scheduling an input and output buffered switch that is adapted to a high-speed large switch is provided. The input and output buffered switch has multiple switching planes, and its structure is used to compensated for decreasing performance of the input buffered switch resulting from HOL (head-of-line) blocking of the input buffered switch. The input and output buffered switch consists of input buffer modules grouping several input ports and output ports and output buffer modules, and each input buffer module has several FIFO queues for the associated module output buffer modules. In the input and output buffered switch having multiple switching planes, cell scheduling is carried out using a simple iterative matching (SIM) method. The SIM method consists of three operations, those are, request operation, grant operation, and accepting operation, and in the SIM method, the operations are iteratively carried out several times in one cell period, thereby matching efficiency can be increased. Each input buffered module determines simultaneously multiple FIFO queues served in one cell period, so that the SIM method with multiple selection ability has higher speed operations and better performance than conventional scheduling methods.
摘要翻译：提供一种用于调度输入和输出缓冲的ATM或分组交换机的方法，更具体地说，涉及一种适用于高速大型交换机的输入和输出缓冲交换机的小区调度方法。输入和输出缓冲开关具有多个开关平面，其结构用于补偿由输入缓冲开关的HOL（线头）阻塞导致的输入缓冲开关的性能下降。输入和输出缓冲交换机由输入缓冲区模块组成，分组几个输入端口和输出端口以及输出缓冲模块，每个输入缓冲区模块都有相应的模块输出缓冲模块的多个FIFO队列。在具有多个交换平面的输入和输出缓冲交换机中，使用简单的迭代匹配（SIM）方法进行小区调度。 SIM方法由三种操作，即请求操作，授权操作和接受操作三种操作，在SIM方法中，在一个单元周期内对该操作进行多次迭代，可以提高匹配效率。每个输入缓冲模块同时确定在一个单元周期内服务的多个FIFO队列，使得具有多种选择能力的SIM方法具有比传统调度方法更高的速度操作和更好的性能。

6. 发明授权

US5925280A Fuse housing for a microwave oven 失效
标题翻译：保险丝外壳为微波炉
公开(公告)号：US5925280A
公开(公告)日：1999-07-20
申请号：US921360
申请日：1997-08-29
申请人： Jung-Hee Lee
发明人： Jung-Hee Lee
IPC分类号： F24C7/02 , H01H85/02 , H01H85/20 , H05B6/66 , H01H85/143
CPC分类号： H01H85/2045 , H01H85/0241
摘要： A microwave oven comprises a main body, a cooking chamber and an electrical component compartment. The electrical component compartment contains a fuse housing which is mounted on a bracket to hold a fuse. Plastic coupling members are integrally mounted onto the fuse housing bracket, into which a fuse is inserted. Each coupling member includes a guide projecting integrally upwardly from the bracket. Both sides of the fuse housing contact respective ones of the guides. A protruding portion on the top of each guide forms a cam surface for spreading the guides apart, and a stop surface for preventing upward dislodgement of the fuse housing.
摘要翻译：微波炉包括主体，烹饪室和电气部件隔间。电气部件隔间包含一个保险丝外壳，该保险丝外壳安装在支架上以保持保险丝。塑料联接构件一体地安装在保险丝壳体支架上，保险丝插入该保险丝支架中。每个联接构件包括从支架一体地向上突出的导向件。保险丝壳体的两侧与相应的导轨接触。每个引导件的顶部上的突出部分形成用于将引导件分开的凸轮表面和用于防止保险丝壳体向上移动的止动表面。

7. 发明申请

US20110051730A1 MULTI-LAYER DATA PROCESSING APPARATUS AND METHOD THEREOF 审中-公开
标题翻译：多层数据处理装置及其方法
公开(公告)号：US20110051730A1
公开(公告)日：2011-03-03
申请号：US12845335
申请日：2010-07-28
申请人： Dong-Myoung BAEK , Bhum-Cheol Lee , Jung-Hee Lee , Sang-Yoon Oh , Seung-Woo Lee
发明人： Dong-Myoung BAEK , Bhum-Cheol Lee , Jung-Hee Lee , Sang-Yoon Oh , Seung-Woo Lee
IPC分类号： H04L12/56
CPC分类号： H04W80/00 , H04L69/08 , H04L69/32
摘要： A multi-layer data processing apparatus and method. The multi-layer data processing unit may classify received multi-layer data into lower layer data and higher layer data using lower layer information, and generate and output a traffic flow of the lower layer data or traffic flows of the lower layer data and the higher layer data with reference to a rule information table. In the rule information table, pieces of lower layer rule information may be linked to pieces of higher layer rule information.
摘要翻译：一种多层数据处理装置和方法。多层数据处理单元可以使用较低层信息将接收的多层数据分类为较低层数据和较高层数据，并生成并输出较低层数据的业务流或较低层数据的业务流和较高层数据参考规则信息表的层数据。在规则信息表中，下层规则信息可以链接到多条高层规则信息。

8. 发明授权

US07619167B2 Fiber reinforced plastic wire for strength member of overhead transmission cable, method for manufacturing the same, and overhead transmission cable using the same 有权
标题翻译：用于架空传输电缆的强度部件的纤维增强塑料线及其制造方法，以及使用其的架空传输电缆
公开(公告)号：US07619167B2
公开(公告)日：2009-11-17
申请号：US11814937
申请日：2005-07-01
申请人： Jung-Hee Lee , Jae-Ik Lee
发明人： Jung-Hee Lee , Jae-Ik Lee
IPC分类号： H01B5/10
CPC分类号： H01B5/105 , D07B1/147 , D07B2201/2056 , D07B2201/2058 , D07B2201/2065 , D07B2201/2068 , D07B2205/2014 , D07B2205/205 , D07B2205/2096 , D07B2205/3003 , D07B2205/3007 , Y10T428/2967 , D07B2801/12 , D07B2801/14
摘要： Disclosed is a fiber reinforced plastic wire used as the overhead transmission cable. The fiber reinforced plastic wire for a strength member of an overhead transmission cable according to the present invention includes a wire having a predetermined diameter and composed of thermoset matrix resin; and a plurality of high strength fibers dispersed parallel to a longitudinal direction in an inside of the wire, the high strength fibers being surface-treated with a coupling agent to improve interfacial adhesion to the matrix resin. The fiber reinforced plastic wire of the present invention has the high tensile strength at the room temperature and the high temperature since its high strength fiber is surface-treated with a coupling agent. The fiber reinforced plastic wire can be also effectively used as the strength member in the overhead transmission cable since it has the excellent low coefficient of thermal expansion, etc. and is light-weight.
摘要翻译：公开了用作架空传输电缆的纤维增强塑料线。根据本发明的用于高架输电线缆的强度构件的纤维增强塑料线包括具有预定直径并由热固性基体树脂构成的线; 以及在线内部平行于纵向方向分散的多根高强度纤维，高强度纤维用偶联剂进行表面处理以改善与基质树脂的界面粘合性。本发明的纤维增强塑料线由于其高强度纤维用偶联剂进行表面处理，在室温和高温下具有高拉伸强度。纤维增强塑料线也可以有效地用作架空传输电缆中的强度构件，因为它具有优异的低的热膨胀系数等，并且重量轻。

9. 发明授权

US5945256A Exposing methods in photolithography used for manufacturing a liquid crystal display 失效
标题翻译：在用于制造液晶显示器的光刻中曝光方法
公开(公告)号：US5945256A
公开(公告)日：1999-08-31
申请号：US66908
申请日：1998-04-28
申请人： Dong-Kyu Kim , Jung-Hee Lee
发明人： Dong-Kyu Kim , Jung-Hee Lee
IPC分类号： G02F1/13 , G02F1/1333 , G02F1/1362 , G03F7/00 , G03F7/20 , H01J17/49 , H01L21/027 , H01L21/336 , H01L29/786
CPC分类号： G03F7/2022 , G02F1/1362 , G03F7/0007 , G02F2001/13625
摘要： A substrate for a microelectronic device is divided into at least two regions and a boundary region therebetween. The boundary region includes a first portion and a second portion. The boundary region may have subregions having equal area, and the sub-regions are arranged in a matrix shape to form the first portion and the second portion A photoresist is coated on the substrate. Portions of the photoresist on the first region and the first portion is exposed to light through a mask for photolithography, and other portions of the photoresist on the second region and the second portion is then exposed to light through the mask. The area of the sub-regions of the first portion in a column becomes larger as goes to the first region, while that of the second portion becomes smaller.
摘要翻译：用于微电子器件的衬底被分成至少两个区域和它们之间的边界区域。边界区域包括第一部分和第二部分。边界区域可以具有相同面积的子区域，并且子区域被布置成矩阵形状以形成第一部分，并且第二部分A将光致抗蚀剂涂覆在基板上。在第一区域和第一部分上的光致抗蚀剂的部分通过用于光刻的掩模曝光，然后在第二区域和第二部分上的光致抗蚀剂的其它部分通过掩模曝光。列中的第一部分的子区域的面积变得比第一区域变大，而第二部分的子区域的面积变小。

10. 发明授权

US08934506B2 Apparatus and method for estimating time stamp 有权
标题翻译：用于估计时间戳的装置和方法
公开(公告)号：US08934506B2
公开(公告)日：2015-01-13
申请号：US13328269
申请日：2011-12-16
申请人： Seung-Woo Lee , Bhum-Cheol Lee , Jung-Hee Lee
发明人： Seung-Woo Lee , Bhum-Cheol Lee , Jung-Hee Lee
IPC分类号： H04J3/06
CPC分类号： H04J3/0697 , H04J3/0638 , H04J3/0658 , H04J3/0667
摘要： An apparatus includes a difference extraction unit to extract a difference between a second time stamp value, which is obtained by adjusting a first time stamp value that is measured at a time of arrival of a synchronization message transmitted by the master at a Layer 3 to be synchronized in frequency with a clock of the master, and a third time stamp value, which is measured at a time of departure of the synchronization message from the master; a minimum filter to select a minimum from one or more difference values extracted by the difference extraction unit; and a delay variation calculation unit to estimate a time of arrival of a current synchronization message at the Layer 3 based on the selected minimum and calculate a delay variation.
摘要翻译：一种装置，包括差分提取单元，用于提取第二时间标记值之间的差异，该第二时间戳值是通过调整由第三层发送的由主机发送的同步消息的到达时所测量的第一时间戳值而获得的频率与主机的时钟同步，以及第三时间戳值，其在与主机的同步消息的离开时测量; 最小滤波器，用于从由所述差分提取单元提取的一个或多个差值中选择最小值; 以及延迟变化计算单元，基于所选择的最小值来估计当前同步消息在层3的到达时间，并计算延迟变化。

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