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1. 发明授权

US10478275B2 Medical diagnostic apparatus having height-adjustable table for animals 有权
公开(公告)号：US10478275B2
公开(公告)日：2019-11-19
申请号：US15636724
申请日：2017-06-29
申请人： Ju-Hyung Kim
发明人： Ju-Hyung Kim
IPC分类号： A61D3/00 , A61G13/06 , A61B90/50 , A61B6/04 , A61B6/00
摘要： A medical diagnostic apparatus having a height-adjustable table for animals according to an embodiment of the present invention includes: a table where an animal is placed; a support stand supporting the table such that the table vertically moves and adjusting height of the table to move the table close to a floor; an X-ray detector disposed under the table and coupled to the support stand to move with the table; and an imaging stand spaced from the table, connected to the support stand, and having an X-ray tube for radiating X-rays to the X-ray detector.

2. 发明授权

US09112045B2 Nonvolatile memory device and fabricating method thereof 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US09112045B2
公开(公告)日：2015-08-18
申请号：US13775833
申请日：2013-02-25
申请人： Ju-Hyung Kim , Chang-Seok Kang , Woon-Kyung Lee
发明人： Ju-Hyung Kim , Chang-Seok Kang , Woon-Kyung Lee
IPC分类号： H01L29/792 , H01L29/66 , H01L29/423 , H01L29/51 , H01L27/115
CPC分类号： H01L29/792 , H01L27/11582 , H01L29/4234 , H01L29/513 , H01L29/66833 , H01L29/7926
摘要： A nonvolatile memory device comprises a channel pattern, a first interlayer dielectric film and a second interlayer dielectric film spaced apart from each other and stacked over each other, a gate pattern disposed between the first interlayer dielectric film and the second interlayer dielectric film, a trap layer disposed between the gate pattern and the channel pattern and a charge spreading inhibition layer disposed between the channel pattern and the first interlayer dielectric film and between the channel pattern and the second interlayer dielectric film. The charge spreading inhibition layer may include charges inside or on its surface. The charge spreading inhibition layer includes at least one of a metal oxide film or a metal nitride film or a metal oxynitride film having a greater dielectric constant than a silicon oxide film.
摘要翻译：非易失性存储器件包括彼此间隔开并且彼此堆叠的沟道图案，第一层间电介质膜和第二层间电介质膜，布置在第一层间电介质膜和第二层间电介质膜之间的栅极图案，阱设置在栅极图案和沟道图案之间的层，以及设置在沟道图案和第一层间电介质膜之间以及沟道图案和第二层间电介质膜之间的电荷扩展抑制层。电荷扩散抑制层可以包括其表面内部或其表面上的电荷。电荷扩散抑制层包括金属氧化物膜或金属氮化物膜或具有比氧化硅膜更大的介电常数的金属氧氮化物膜中的至少一种。

3. 发明申请

US20120169477A1 COMMUNICATIONS SYSTEM AND METHOD OF COMMUNICATING DISPLAY INFORMATION, AND ELECTRONIC SHELF LABEL SYSTEM USING THE SAME 审中-公开
标题翻译：通信系统和通信显示信息的方法以及使用该显示信息的电子书签系统
公开(公告)号：US20120169477A1
公开(公告)日：2012-07-05
申请号：US13340161
申请日：2011-12-29
申请人： Jeong Su SEO , Song On Lee , Tae Ha Lee , Dong Hyun Kim , Hyun Hak Kim , Chang Soo Lim , Ju Hyung Kim
发明人： Jeong Su SEO , Song On Lee , Tae Ha Lee , Dong Hyun Kim , Hyun Hak Kim , Chang Soo Lim , Ju Hyung Kim
IPC分类号： G06K7/01
CPC分类号： G09F3/204 , G06F3/147 , G09F3/208 , G09G2380/04
摘要： There are provided a communications system and a method for more efficiently communicating display information in transmitting large-capacity data, such as graphics data, between communication nodes, and an electronic shelf label system using the same. The communications system communicating display information includes a first communications device transmitting display information and a second communications device having a display unit displaying the display information.
摘要翻译：提供了一种在通信节点之间传输大容量数据（诸如图形数据）和使用该数据的电子货架标签系统之间更有效地传送显示信息的通信系统和方法。通信显示信息的通信系统包括发送显示信息的第一通信设备和具有显示显示信息的显示单元的第二通信设备。

4. 发明授权

US07825459B2 Method of operating a SONOS memory device 有权
标题翻译：操作SONOS存储器件的方法
公开(公告)号：US07825459B2
公开(公告)日：2010-11-02
申请号：US12453147
申请日：2009-04-30
申请人： Ju-hyung Kim , Chung-woo Kim , Soo-doo Chae , Youn-seok Jeong
发明人： Ju-hyung Kim , Chung-woo Kim , Soo-doo Chae , Youn-seok Jeong
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/518 , H01L29/7887
摘要： A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.
摘要翻译：氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件包括在半导体衬底上包括具有SONOS结构的栅极的存储器型晶体管。栅极通过依次层叠隧道氧化物层，存储器结构结构，其包括具有纳米级陷阱元件的陷阱位置，其中通过隧道氧化物层的电荷被捕获，以及栅极电极。纳米尺寸的阱元件可以是由彼此分离以捕获电荷的纳米晶体组成的晶体层。存储器节点结构可以包括与纳米级陷阱元件隔离的附加存储器节点层。

5. 发明授权

US07662511B2 Secondary battery having an enlarged electrolytic solution inlet 有权
标题翻译：具有放大的电解液入口的二次电池
公开(公告)号：US07662511B2
公开(公告)日：2010-02-16
申请号：US10791854
申请日：2004-03-04
申请人： Su-Jin Han , Chang-Seob Kim , Yoon-Tai Kwak , Soo-Youn Maeng , Ju-Hyung Kim
发明人： Su-Jin Han , Chang-Seob Kim , Yoon-Tai Kwak , Soo-Youn Maeng , Ju-Hyung Kim
IPC分类号： H01M2/00 , H01M2/02 , H01M10/00 , H01M10/02
CPC分类号： H01M2/361 , H01M2/1235 , H01M2/263 , H01M2/30 , H01M10/0525
摘要： A secondary battery includes an electrode unit having a first electrode plate, a second electrode plate, a separator interposed therebetween, and first and second electrode tabs respectively extending from the first and second electrode plates, a can adapted to accommodate the electrode unit and an electrolytic solution, and a cap plate adapted to seal the can and having an electrolytic solution inlet, wherein the electrolytic solution inlet has an area on one surface of the cap plate different from that on another surface of the cap plate.
摘要翻译：二次电池包括电极单元，其具有第一电极板，第二电极板，插入其间的隔膜以及分别从第一和第二电极板延伸的第一和第二电极接头，适于容纳电极单元和电解质的电极溶液和适于密封罐并具有电解液入口的盖板，其中电解溶液入口具有与盖板的另一表面上不同的盖板的一个表面上的区域。

6. 发明申请

US20090238004A1 Method of operating sonos memory device 有权
标题翻译：操作sonos存储器的方法
公开(公告)号：US20090238004A1
公开(公告)日：2009-09-24
申请号：US12453147
申请日：2009-04-30
申请人： Ju-hyung Kim , Chung-woo Kim , Soo-doo Chae , Youn-seok Jeong
发明人： Ju-hyung Kim , Chung-woo Kim , Soo-doo Chae , Youn-seok Jeong
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/518 , H01L29/7887
摘要： A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.
摘要翻译：氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件包括在半导体衬底上包括具有SONOS结构的栅极的存储器型晶体管。栅极通过依次层叠隧道氧化物层，存储器结构结构，其包括具有纳米级陷阱元件的陷阱位置，其中通过隧道氧化物层的电荷被捕获，以及栅极电极。纳米尺寸的阱元件可以是由彼此分离以捕获电荷的纳米晶体组成的晶体层。存储器节点结构可以包括与纳米级陷阱元件隔离的附加存储器节点层。

7. 发明授权

US07586330B2 Pre-emphasis apparatus, low voltage differential signaling transmitter including the same and pre-emphasis method 有权
标题翻译：预加重装置，低压差分信号发射机包括相同的预加重方法
公开(公告)号：US07586330B2
公开(公告)日：2009-09-08
申请号：US11503311
申请日：2006-08-11
申请人： Ju-Hyung Kim
发明人： Ju-Hyung Kim
IPC分类号： H03K19/0175 , H03K3/00 , H03B1/00
CPC分类号： H04L25/0272 , H03K19/0185
摘要： A pre-emphasis apparatus of a LVDS transmitter includes a pre-emphasis signaling generation unit and a pre-emphasis current output unit. The pre-emphasis signal generation unit generates a pre-emphasis pulse signal based on N parallel data signals received from an external source and N-phase clock signals received from a phase locked loop, where N is an integer greater than 1. The pre-emphasis current output unit provides an additional current for a pre-emphasis operation to a current source of a LVDS driver in response to the pre-emphasis pulse signal generated by the pre-emphasis pulse signal generation unit. The pulse signal for pre-emphasis is generated based on the parallel data signals received from the external source and the multi-phase clock signals, which are output from the phase locked loop for performing a sampling of the parallel data signals.
摘要翻译： LVDS发射机的预加重装置包括预加重信令产生单元和预加重电流输出单元。预加重信号产生单元基于从外部源接收的N个并行数据信号和从锁相环接收的N相时钟信号产生预加重脉冲信号，其中N是大于1的整数。强调电流输出单元响应于由预加重脉冲信号产生单元产生的预加重脉冲信号，向LVDS驱动器的电流源提供用于预加重操作的附加电流。用于预加重的脉冲信号基于从外部源接收的并行数据信号和从锁相环输出的并行数据信号的采样的多相时钟信号产生。

8. 发明授权

US07292078B2 Phase locked loop integrated circuits having fast locking characteristics and methods of operating same 有权
标题翻译：具有快锁定特性的锁相环集成电路及其操作方法
公开(公告)号：US07292078B2
公开(公告)日：2007-11-06
申请号：US11178629
申请日：2005-07-11
申请人： Seok-Min Jung , Ju-Hyung Kim
发明人： Seok-Min Jung , Ju-Hyung Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/0893 , H03L7/093
摘要： An integrated circuit device includes a fast-locking phase locked loop (PLL). This PLL includes a phase-frequency detector and first and second charge pumps, which are responsive to first and second control signals generated by the phase-frequency detector. The first and second charge pumps have different current sourcing characteristics when the first control signal is active and different current sinking characteristics when the second control signal is active.
摘要翻译：集成电路器件包括快锁锁相环（PLL）。该PLL包括相位检测器和第一和第二电荷泵，其响应由相位频率检测器产生的第一和第二控制信号。当第二控制信号有效时，第一和第二电荷泵具有不同的电流源特性，当第二控制信号有效时，具有不同的电流吸收特性。

9. 发明授权

US07250653B2 SONOS memory device having nano-sized trap elements 有权
公开(公告)号：US07250653B2
公开(公告)日：2007-07-31
申请号：US10849446
申请日：2004-05-20
申请人： Ju-hyung Kim , Chung-woo Kim , Soo-doo Chae , Youn-seok Jeong
发明人： Ju-hyung Kim , Chung-woo Kim , Soo-doo Chae , Youn-seok Jeong
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/518 , H01L29/7887
摘要： A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.

10. 发明申请

US20060147793A1 Jelly-roll type battery unit and winding method thereof and lithium secondary battery comprising the same 有权
标题翻译：胶卷式电池单元及其卷绕方法以及包含该方法的锂二次电池
公开(公告)号：US20060147793A1
公开(公告)日：2006-07-06
申请号：US11304710
申请日：2005-12-16
申请人： Chang-Seob Kim , Ju-Hyung Kim , Min-Ho Song , Jun-Won Kang
发明人： Chang-Seob Kim , Ju-Hyung Kim , Min-Ho Song , Jun-Won Kang
IPC分类号： H01M4/64 , H01M2/26
CPC分类号： H01M2/263 , H01M4/70 , H01M10/052 , H01M10/0587 , Y02E60/122 , Y10T29/49108 , Y10T29/49114
摘要： A jelly-roll type battery unit includes a first electrode plate having a first electrode current collector with a first electrode tab, and a first electrode active material layer on a surface of the first electrode current collector; a second electrode plate having a second electrode current collector with a second electrode tab, and a second electrode active material layer on a surface of the second electrode current collector; and a separator interposed between the first electrode plate and the second electrode plate. The electrode tab is incorporated into the electrode current collector in an area of either first or second electrode plate where the corresponding electrode active material layer is not coated. The electrode tab is cut widthwise with respect to the electrode current collector from a center area of the electrode current collector and folded, and an insulating tape is adhered to either surface of the electrode tab.
摘要翻译：胶卷型电池单元包括：具有第一电极集电体的第一电极板和第一电极接线片;以及在第一电极集电体的表面上的第一电极活性物质层; 第二电极板，具有带有第二电极接线片的第二电极集电体和在第二电极集电体的表面上的第二电极活性物质层; 以及插入在第一电极板和第二电极板之间的隔膜。在第一或第二电极板的没有涂覆相应的电极活性物质层的区域中，电极片被并入到电极集电器中。电极片相对于电极集电体从电极集电体的中心区域横向切割并折叠，并且绝缘带粘附到电极片的任一表面。

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