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1. 发明申请

US20130049698A1 CELL BALANCING METHOD, CELL BALANCING DEVICE, AND ENERGY STORAGE SYSTEM INCLUDING THE CELL BALANCING DEVICE 有权
标题翻译：细胞平衡方法，细胞平衡装置和包括细胞平衡装置的能量储存系统
公开(公告)号：US20130049698A1
公开(公告)日：2013-02-28
申请号：US13534859
申请日：2012-06-27
申请人： Seok-Min Jung
发明人： Seok-Min Jung
IPC分类号： H02J7/00
CPC分类号： H02J7/0016 , H02J7/0086
摘要： A method of balancing a plurality of battery cells includes acquiring an open circuit voltage (OCV) of a battery cell of the plurality of battery cells connected in series; determining a state of charge (SOC) of the battery cell based on the OCV of the battery cell; determining a differential value in the OCV of the battery cell per a change of the SOC of the battery cell, in accordance with the SOC of the battery cell; and activating cell balancing of the plurality of battery cells when the differential value is greater than a reference value.
摘要翻译：平衡多个电池单元的方法包括获取串联连接的多个电池单元的电池单元的开路电压（OCV）; 基于电池单元的OCV确定电池单元的充电状态（SOC）; 根据电池单元的SOC，确定电池单元的SOC变化的OCV的差分值; 以及当所述差分值大于参考值时激活所述多个电池单元的电池平衡。

2. 发明授权

US07937742B2 Broadcasting receiving apparatus and control method for receiving audio/video signals and additional audio signal for outputting to an external device 有权
标题翻译：用于接收音频/视频信号的广播接收设备和控制方法以及用于输出到外部设备的附加音频信号
公开(公告)号：US07937742B2
公开(公告)日：2011-05-03
申请号：US11872077
申请日：2007-10-15
申请人： Seok-min Jung
发明人： Seok-min Jung
IPC分类号： H04N7/16
CPC分类号： H04H20/08
摘要： A broadcasting receiving apparatus includes: a signal receiving unit which receives a first signal and a second signal different from the first signal; a signal processing unit which processes the first and second signals; a communication unit which communicates with an external device to output a sound; and a controller which controls the signal processing unit and the communication unit to process a video signal of the first signal to be displayed and to process an audio signal of the second signal to be transmitted to the external device if the first signals contains the video signal and the second signal contains only the audio signal.
摘要翻译：广播接收装置包括：信号接收单元，其接收与第一信号不同的第一信号和第二信号; 信号处理单元，处理第一和第二信号; 与外部设备通信以输出声音的通信单元; 以及控制器，其控制所述信号处理单元和所述通信单元处理要显示的所述第一信号的视频信号，并且如果所述第一信号包含所述视频信号，则处理要发送到所述外部设备的所述第二信号的音频信号并且第二信号仅包含音频信号。

3. 发明授权

US07388412B2 Clock multipliers using filter bias of a phase-locked loop and methods of multiplying a clock 有权
标题翻译：使用锁相环的滤波器偏置的时钟乘法器和乘法时钟的方法
公开(公告)号：US07388412B2
公开(公告)日：2008-06-17
申请号：US11503803
申请日：2006-08-14
申请人： Seok-Min Jung
发明人： Seok-Min Jung
IPC分类号： H03B19/00 , H03L7/06 , H03H11/26
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/0805
摘要： A clock multiplier includes a phase-locked loop (PLL), a bias generator, a counter, a selection circuit, a flip-flop, a phase comparator, a delay controller and a variable delay circuit. The variable delay circuit, which is biased by a delay cell bias signal, delays a reference signal by a first delay time and by a second time that is longer than the first delay time, and generates a first feedback signal corresponding to the first delay time, and a second feedback signal corresponding to the second delay time. Therefore, a clock multiplier may reduce the size of a delay cell and may be designed to be insensitive to changes in environmental conditions, such as a process, a voltage, a temperature, and so on.
摘要翻译：时钟倍频器包括锁相环（PLL），偏置发生器，计数器，选择电路，触发器，相位比较器，延迟控制器和可变延迟电路。由延迟单元偏置信号偏置的可变延迟电路将参考信号延迟第一延迟时间，延迟长于第一延迟时间的第二时间，并产生对应于第一延迟时间的第一反馈信号以及对应于第二延迟时间的第二反馈信号。因此，时钟乘法器可以减小延迟单元的尺寸，并且可以被设计为对环境条件的变化（例如过程，电压，温度等）不敏感。

4. 发明授权

US07292078B2 Phase locked loop integrated circuits having fast locking characteristics and methods of operating same 有权
标题翻译：具有快锁定特性的锁相环集成电路及其操作方法
公开(公告)号：US07292078B2
公开(公告)日：2007-11-06
申请号：US11178629
申请日：2005-07-11
申请人： Seok-Min Jung , Ju-Hyung Kim
发明人： Seok-Min Jung , Ju-Hyung Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/0893 , H03L7/093
摘要： An integrated circuit device includes a fast-locking phase locked loop (PLL). This PLL includes a phase-frequency detector and first and second charge pumps, which are responsive to first and second control signals generated by the phase-frequency detector. The first and second charge pumps have different current sourcing characteristics when the first control signal is active and different current sinking characteristics when the second control signal is active.
摘要翻译：集成电路器件包括快锁锁相环（PLL）。该PLL包括相位检测器和第一和第二电荷泵，其响应由相位频率检测器产生的第一和第二控制信号。当第二控制信号有效时，第一和第二电荷泵具有不同的电流源特性，当第二控制信号有效时，具有不同的电流吸收特性。

5. 发明申请

US20070040594A1 Clock multipliers using filter bias of a phase-locked loop and methods of multiplying a clock 有权
标题翻译：使用锁相环的滤波器偏置的时钟乘法器和乘法时钟的方法
公开(公告)号：US20070040594A1
公开(公告)日：2007-02-22
申请号：US11503803
申请日：2006-08-14
申请人： Seok-Min Jung
发明人： Seok-Min Jung
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/0805
摘要： A clock multiplier includes a phase-locked loop (PLL), a bias generator, a counter, a selection circuit, a flip-flop, a phase comparator, a delay controller and a variable delay circuit. The variable delay circuit, which is biased by a delay cell bias signal, delays a reference signal by a first delay time and by a second time that is longer than the first delay time, and generates a first feedback signal corresponding to the first delay time, and a second feedback signal corresponding to the second delay time. Therefore, a clock multiplier may reduce the size of a delay cell and may be designed to be insensitive to changes in environmental conditions, such as a process, a voltage, a temperature, and so on.
摘要翻译：时钟倍频器包括锁相环（PLL），偏置发生器，计数器，选择电路，触发器，相位比较器，延迟控制器和可变延迟电路。由延迟单元偏置信号偏置的可变延迟电路将参考信号延迟第一延迟时间，延迟长于第一延迟时间的第二时间，并产生对应于第一延迟时间的第一反馈信号以及对应于第二延迟时间的第二反馈信号。因此，时钟乘法器可以减小延迟单元的尺寸，并且可以被设计为对环境条件的变化（例如过程，电压，温度等）不敏感。

6. 发明授权

US09118191B2 Cell balancing method, cell balancing device, and energy storage system including the cell balancing device 有权
标题翻译：电池平衡方法，电池平衡装置和包括电池平衡装置的能量存储系统
公开(公告)号：US09118191B2
公开(公告)日：2015-08-25
申请号：US13534859
申请日：2012-06-27
申请人： Seok-Min Jung
发明人： Seok-Min Jung
IPC分类号： H02J7/00
CPC分类号： H02J7/0016 , H02J7/0086
摘要： A method of balancing a plurality of battery cells includes acquiring an open circuit voltage (OCV) of a battery cell of the plurality of battery cells connected in series; determining a state of charge (SOC) of the battery cell based on the OCV of the battery cell; determining a differential value in the OCV of the battery cell per a change of the SOC of the battery cell, in accordance with the SOC of the battery cell; and activating cell balancing of the plurality of battery cells when the differential value is greater than a reference value.
摘要翻译：平衡多个电池单元的方法包括获取串联连接的多个电池单元的电池单元的开路电压（OCV）; 基于电池单元的OCV确定电池单元的充电状态（SOC）; 根据电池单元的SOC，确定电池单元的SOC变化的OCV的差分值; 以及当所述差分值大于参考值时激活所述多个电池单元的电池平衡。

7. 发明申请

US20080301752A1 BROADCASTING RECEIVING APPARATUS AND CONTROL METHOD THEREOF 有权
标题翻译：广播接收装置及其控制方法
公开(公告)号：US20080301752A1
公开(公告)日：2008-12-04
申请号：US11872077
申请日：2007-10-15
申请人： Seok-min JUNG
发明人： Seok-min JUNG
IPC分类号： H04N7/16
CPC分类号： H04H20/08
摘要： A broadcasting receiving apparatus includes: a signal receiving unit which receives a first signal and a second signal different from the first signal; a signal processing unit which processes the first and second signals; a communication unit which communicates with an external device to output a sound; and a controller which controls the signal processing unit and the communication unit to process a video signal of the first signal to be displayed and to process an audio signal of the second signal to be transmitted to the external device if the first signals contains the video signal and the second signal contains only the audio signal.
摘要翻译：广播接收装置包括：信号接收单元，其接收与第一信号不同的第一信号和第二信号; 信号处理单元，处理第一和第二信号; 与外部设备通信以输出声音的通信单元; 以及控制器，其控制所述信号处理单元和所述通信单元处理要显示的所述第一信号的视频信号，并且如果所述第一信号包含所述视频信号，则处理要发送到所述外部设备的所述第二信号的音频信号并且第二信号仅包含音频信号。

8. 发明申请

US20060017476A1 Phase locked loop integrated circuits having fast locking characteristics and methods of operating same 有权
标题翻译：具有快速锁定特性的锁相环集成电路及其操作方法
公开(公告)号：US20060017476A1
公开(公告)日：2006-01-26
申请号：US11178629
申请日：2005-07-11
申请人： Seok-Min Jung , Ju-Hyung Kim
发明人： Seok-Min Jung , Ju-Hyung Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/0893 , H03L7/093
摘要： An integrated circuit device includes a fast-locking phase locked loop (PLL). This PLL includes a phase-frequency detector and first and second charge pumps, which are responsive to first and second control signals generated by the phase-frequency detector. The first and second charge pumps have different current sourcing characteristics when the first control signal is active and different current sinking characteristics when the second control signal is active.
摘要翻译：集成电路器件包括快锁锁相环（PLL）。该PLL包括相位检测器和第一和第二电荷泵，其响应由相位频率检测器产生的第一和第二控制信号。当第二控制信号有效时，第一和第二电荷泵具有不同的电流源特性，当第二控制信号有效时，具有不同的电流吸收特性。

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