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1. 发明授权

US07825459B2 Method of operating a SONOS memory device 有权
标题翻译：操作SONOS存储器件的方法
公开(公告)号：US07825459B2
公开(公告)日：2010-11-02
申请号：US12453147
申请日：2009-04-30
申请人： Ju-hyung Kim , Chung-woo Kim , Soo-doo Chae , Youn-seok Jeong
发明人： Ju-hyung Kim , Chung-woo Kim , Soo-doo Chae , Youn-seok Jeong
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/518 , H01L29/7887
摘要： A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.
摘要翻译：氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件包括在半导体衬底上包括具有SONOS结构的栅极的存储器型晶体管。栅极通过依次层叠隧道氧化物层，存储器结构结构，其包括具有纳米级陷阱元件的陷阱位置，其中通过隧道氧化物层的电荷被捕获，以及栅极电极。纳米尺寸的阱元件可以是由彼此分离以捕获电荷的纳米晶体组成的晶体层。存储器节点结构可以包括与纳米级陷阱元件隔离的附加存储器节点层。

2. 发明申请

US20090238004A1 Method of operating sonos memory device 有权
标题翻译：操作sonos存储器的方法
公开(公告)号：US20090238004A1
公开(公告)日：2009-09-24
申请号：US12453147
申请日：2009-04-30
申请人： Ju-hyung Kim , Chung-woo Kim , Soo-doo Chae , Youn-seok Jeong
发明人： Ju-hyung Kim , Chung-woo Kim , Soo-doo Chae , Youn-seok Jeong
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/518 , H01L29/7887
摘要： A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.
摘要翻译：氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件包括在半导体衬底上包括具有SONOS结构的栅极的存储器型晶体管。栅极通过依次层叠隧道氧化物层，存储器结构结构，其包括具有纳米级陷阱元件的陷阱位置，其中通过隧道氧化物层的电荷被捕获，以及栅极电极。纳米尺寸的阱元件可以是由彼此分离以捕获电荷的纳米晶体组成的晶体层。存储器节点结构可以包括与纳米级陷阱元件隔离的附加存储器节点层。

3. 发明授权

US07250653B2 SONOS memory device having nano-sized trap elements 有权
公开(公告)号：US07250653B2
公开(公告)日：2007-07-31
申请号：US10849446
申请日：2004-05-20
申请人： Ju-hyung Kim , Chung-woo Kim , Soo-doo Chae , Youn-seok Jeong
发明人： Ju-hyung Kim , Chung-woo Kim , Soo-doo Chae , Youn-seok Jeong
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/518 , H01L29/7887
摘要： A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.

4. 发明申请

US20070267688A1 SONOS memory device having nano-sized trap elements 有权
标题翻译：具有纳米级陷阱元件的SONOS存储器件
公开(公告)号：US20070267688A1
公开(公告)日：2007-11-22
申请号：US11878277
申请日：2007-07-23
申请人： Ju-hyung Kim , Chung-woo Kim , Soo-doo Chae , Youn-seok Jeong
发明人： Ju-hyung Kim , Chung-woo Kim , Soo-doo Chae , Youn-seok Jeong
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/518 , H01L29/7887
摘要： A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.
摘要翻译：氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件包括在半导体衬底上包括具有SONOS结构的栅极的存储器型晶体管。栅极通过依次层叠隧道氧化物层，存储器结构结构，其包括具有纳米级陷阱元件的陷阱位置，其中通过隧道氧化物层的电荷被捕获，以及栅极电极。纳米尺寸的阱元件可以是由彼此分离以捕获电荷的纳米晶体组成的晶体层。存储器节点结构可以包括与纳米级陷阱元件隔离的附加存储器节点层。

5. 发明授权

US07531870B2 SONOS memory device having nano-sized trap elements 有权
标题翻译：具有纳米级陷阱元件的SONOS存储器件
公开(公告)号：US07531870B2
公开(公告)日：2009-05-12
申请号：US11878277
申请日：2007-07-23
申请人： Ju-hyung Kim , Chung-woo Kim , Soo-doo Chae , Youn-seok Jeong
发明人： Ju-hyung Kim , Chung-woo Kim , Soo-doo Chae , Youn-seok Jeong
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/518 , H01L29/7887
摘要： A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.
摘要翻译：氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件包括在半导体衬底上包括具有SONOS结构的栅极的存储器型晶体管。栅极通过依次层叠隧道氧化物层，存储器结构结构，其包括具有纳米级陷阱元件的陷阱位置，其中通过隧道氧化物层的电荷被捕获，以及栅极电极。纳米尺寸的阱元件可以是由彼此分离以捕获电荷的纳米晶体组成的晶体层。存储器节点结构可以包括与纳米级陷阱元件隔离的附加存储器节点层。

6. 发明授权

US08217445B2 SONOS memory device using an amorphous memory node material 有权
标题翻译： SONOS存储器件使用非晶体存储器节点材料
公开(公告)号：US08217445B2
公开(公告)日：2012-07-10
申请号：US10864499
申请日：2004-06-10
申请人： Sang-hun Jeon , Soo-doo Chae , Ju-hyung Kim , Chung-woo Kim
发明人： Sang-hun Jeon , Soo-doo Chae , Ju-hyung Kim , Chung-woo Kim
IPC分类号： H01L29/792
CPC分类号： H01L21/28282
摘要： A SONOS memory device, and a method of manufacturing the same, includes a substrate and a multifunctional device formed on the substrate. The multifunctional device performs both switching and data storing functions. The multifunctional device includes first and second impurities areas, a channel formed between the first and second impurities areas, and a stacked material formed on the channel for data storage. The stacked material for data storage is formed by sequentially stacking a tunneling oxide layer, a memory node layer in which data is stored, a blocking layer, and an electrode layer.
摘要翻译： SONOS存储器件及其制造方法包括形成在衬底上的衬底和多功能器件。多功能设备执行切换和数据存储功能。多功能装置包括第一和第二杂质区域，形成在第一和第二杂质区域之间的通道，以及形成在通道上用于数据存储的堆叠材料。用于数据存储的层叠材料通过依次层叠隧道氧化物层，存储数据的存储节点层，阻挡层和电极层而形成。

7. 发明申请

US20070296026A1 SONOS memory device 审中-公开
标题翻译： SONOS存储设备
公开(公告)号：US20070296026A1
公开(公告)日：2007-12-27
申请号：US11896698
申请日：2007-09-05
申请人： Sang-hun Jeon , Soo-doo Chae , Ju-hyung Kim , Chung-woo Kim
发明人： Sang-hun Jeon , Soo-doo Chae , Ju-hyung Kim , Chung-woo Kim
IPC分类号： H01L29/792
CPC分类号： H01L29/40117
摘要： A SONOS memory device, and a method of manufacturing the same, includes a substrate and a multifunctional device formed on the substrate. The multifunctional device performs both switching and data storing functions. The multifunctional device includes first and second impurities areas, a channel formed between the first and second impurities areas, and a stacked material formed on the channel for data storage. The stacked material for data storage is formed by sequentially stacking a tunneling oxide layer, a memory node layer in which data is stored, a blocking layer, and an electrode layer.
摘要翻译： SONOS存储器件及其制造方法包括形成在衬底上的衬底和多功能器件。多功能设备执行切换和数据存储功能。多功能装置包括第一和第二杂质区域，形成在第一和第二杂质区域之间的通道，以及形成在通道上用于数据存储的堆叠材料。用于数据存储的层叠材料通过依次层叠隧道氧化物层，存储数据的存储节点层，阻挡层和电极层而形成。

8. 发明申请

US20060255368A1 Single electron transistor having memory function and method of manufacturing the same 有权
标题翻译：具有记忆功能的单电子晶体管及其制造方法
公开(公告)号：US20060255368A1
公开(公告)日：2006-11-16
申请号：US11491281
申请日：2006-07-24
申请人： Soo-doo Chae , Chung-woo Kim , Ju-hyung Kim
发明人： Soo-doo Chae , Chung-woo Kim , Ju-hyung Kim
IPC分类号： H01L29/76
CPC分类号： B82Y10/00 , H01L29/7888 , Y10S977/937 , Y10S977/938
摘要： A single electron transistor having a memory function and a fabrication method thereof are disclosed. In the single electron transistor, a first substrate and an insulation film are sequentially stacked, a second substrate is stacked on the insulation film and includes a source region, a channel region, and a drain region, a tunneling film is formed on the second substrate, at least two trap layers are formed on the tunneling film and are separated by an interval such that at least one quantum dot may be formed in a same interval in the channel region, and a gate electrode is formed to contact the at least two trap layers and the tunneling film between the at least two trap layers. Because the single electron transistor is simple and includes a single gate electrode, a fabricating process and an operational circuit thereof may be simplified, and power consumption may be reduced.
摘要翻译：公开了具有记忆功能的单电子晶体管及其制造方法。在单电子晶体管中，第一衬底和绝缘膜依次层叠，第二衬底层叠在绝缘膜上，并且包括源极区域，沟道区域和漏极区域，在第二衬底上形成隧穿膜在隧道膜上形成至少两个陷阱层，并且以间隔隔开，使得至少一个量子点可以在沟道区域中以相同的间隔形成，并且形成栅电极以接触至少两个陷阱层和至少两个陷阱层之间的隧道膜。由于单电子晶体管简单并且包括单个栅极电极，所以可以简化制造工艺及其操作电路，并且可以降低功耗。

9. 发明授权

US07105874B2 Single electron transistor having memory function 有权
标题翻译：具有记忆功能的单电子晶体管
公开(公告)号：US07105874B2
公开(公告)日：2006-09-12
申请号：US10773288
申请日：2004-02-09
申请人： Soo-doo Chae , Chung-woo Kim , Ju-hyung Kim
发明人： Soo-doo Chae , Chung-woo Kim , Ju-hyung Kim
IPC分类号： H01L29/76
CPC分类号： B82Y10/00 , H01L29/7888 , Y10S977/937 , Y10S977/938
摘要： A single electron transistor having a memory function and a fabrication method thereof are disclosed. In the single electron transistor, a first substrate and an insulation film are sequentially stacked, a second substrate is stacked on the insulation film and includes a source region, a channel region, and a drain region, a tunneling film is formed on the second substrate, at least two trap layers are formed on the tunneling film and are separated by an interval such that at least one quantum dot may be formed in a same interval in the channel region, and a gate electrode is formed to contact the at least two trap layers and the tunneling film between the at least two trap layers. Because the single electron transistor is simple and includes a single gate electrode, a fabricating process and an operational circuit thereof may be simplified, and power consumption may be reduced.
摘要翻译：公开了具有记忆功能的单电子晶体管及其制造方法。在单电子晶体管中，第一衬底和绝缘膜依次层叠，第二衬底层叠在绝缘膜上，并且包括源极区域，沟道区域和漏极区域，在第二衬底上形成隧穿膜在隧道膜上形成至少两个陷阱层，并且以间隔隔开，使得至少一个量子点可以在沟道区域中以相同的间隔形成，并且形成栅电极以接触至少两个陷阱层和至少两个陷阱层之间的隧道膜。由于单电子晶体管简单并且包括单个栅极电极，所以可以简化制造工艺及其操作电路，并且可以降低功耗。

10. 发明授权

US07629244B2 Method of fabricating a single electron transistor having memory function 有权
标题翻译：制造具有记忆功能的单电子晶体管的方法
公开(公告)号：US07629244B2
公开(公告)日：2009-12-08
申请号：US11491281
申请日：2006-07-24
申请人： Soo-doo Chae , Chung-woo Kim , Ju-hyung Kim
发明人： Soo-doo Chae , Chung-woo Kim , Ju-hyung Kim
IPC分类号： H01L21/4763
CPC分类号： B82Y10/00 , H01L29/7888 , Y10S977/937 , Y10S977/938
摘要： A single electron transistor having a memory function and a fabrication method thereof are disclosed. In the single electron transistor, a first substrate and an insulation film are sequentially stacked, a second substrate is stacked on the insulation film and includes a source region, a channel region, and a drain region, a tunneling film is formed on the second substrate, at least two trap layers are formed on the tunneling film and are separated by an interval such that at least one quantum dot may be formed in a same interval in the channel region, and a gate electrode is formed to contact the at least two trap layers and the tunneling film between the at least two trap layers. Because the single electron transistor is simple and includes a single gate electrode, a fabricating process and an operational circuit thereof may be simplified, and power consumption may be reduced.
摘要翻译：公开了具有记忆功能的单电子晶体管及其制造方法。在单电子晶体管中，第一衬底和绝缘膜依次层叠，第二衬底层叠在绝缘膜上，并且包括源极区域，沟道区域和漏极区域，在第二衬底上形成隧穿膜在隧道膜上形成至少两个陷阱层，并且以间隔隔开，使得至少一个量子点可以在沟道区域中以相同的间隔形成，并且形成栅电极以接触至少两个陷阱层和至少两个陷阱层之间的隧道膜。由于单电子晶体管简单并且包括单个栅极电极，所以可以简化制造工艺及其操作电路，并且可以降低功耗。

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